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FPGA-Based Implementation of Digital Control for a Magnetic Bearing

F. Krach, B. Frackelton, J. Carletta, and R. Veillette

Department of Electrical and Computer Engineering

The University of Akron

Abstract1

An FPGA-based digital controller is presented for a

magnetic bearing control application. A side-by-side

comparison of the FPGA- and DSP-based controllers

demonstrates the advantages of using an FPGA in terms ofdesign procedures, performance, and hardware utilization.

The FPGA-based controller runs two orders of magnitude

faster than the DSP-based controller does. The flexibility tocustomize the bit-widths of the internal variables makes the

FPGA-based implementation more accurate than the DSP-

based implementation, without increasing total register

space. The increased accuracy in the control computation isespecially important as fast sampling causes increased

computational sensitivity.

1 Introduction

Digital controllers are traditionally implemented using

digital signal processors (DSPs). The field programmablegate array (FPGA) presents an alternative to the DSP for

digital control. FPGAs allow the use of customized bit-

widths for the appropriate level of precision at each point in

the calculation. They also exploit hardware parallelism for

greater computational speed. These characteristics makethe FPGA ideal for high-bandwidth controls applications

such as magnetic bearings.

Previous work has reported FPGA-based implementationsof both digital filters and digital feedback controllers.Although most work in digital filters does not cover the

implementation issues dealt with in this work, many of the

same issues, such as the flexibility that an FPGA affords

and finite bit-width effects with respect to fast sampling, are

addressed in [10]. Finite bit-width issues are alsorecognized in [13] and [14]. The previous work in FPGA-

based digital control presents some of the advantages

available with an FPGA-based control implementation,

including the concurrent mathematical operation [16] [17][15], the flexibility of a VHDL implementation [16] [17],

and the high-speed execution [15] [8]. The authors of [17]

point out the cost disadvantage of FPGAs with respect toDSPs.

This work directly compares FPGA- and DSP-based control

implementations for a magnetic bearing application.

This material is based upon work supported by the NationalScience Foundation under Grant No. 0113168.

Although the FPGA is more expensive, it can operate at a

far greater sampling rate than the DSP can. It also allowsgreater flexibility for choosing the precision of the internal

variables of the controller. The judicious use of non-

uniform bit-widths allows the FPGA to operate with

sufficient precision at the higher sampling rate, without

wasting hardware. The results illustrate the FPGA-basedcontrollers superiority over the DSP.

The magnetic bearing application is introduced in Section

2. The analog control solution is covered in Section 3. Theexperimental set-ups for the DSP- and FPGA-based

controllers are then given in Section 4. Section 5 reviews

the results based on experimental data. Finally, some

conclusions are drawn in Section 6.

2 The Magnetic Bearing

Magnetic bearings are well suited to applications requiringhigh rotational speeds [7], and to those where lubrication is

problematical [1]. Of course, magnetic bearings require

feedback control as the open-loop system is unstable.

The magnetic bearing system used is an MBC 500 made by

Magnetic Moments, LLC. This system consists of a rotor

supported by two active radial magnetic bearings, andincludes the necessary position sensors, power amplifiers,

and controllers. Each bearing has two axes of control, with

separate control loops. The magnetic force along each axisis generated by a pair of opposing horseshoe electromagnets

in a push-pull arrangement. The position of the shaft is

measured by means of a Hall-effect sensor along each axis.

The transfer function from the power-amplifier input

voltage to the sensor output voltage, including the actuator

and sensor gains, and the power-amplifier dynamics [11], is

)6.223)(6.223)(4545(

)10()3.227()(

6

++

=

ssssP . (Eq. 1)

3 The Analog Compensator

The magnetic bearing was controlled using the second-

order, continuous-time compensator

)3226)(10223.3(

)1124)(1093.1()()(

5

4

++

++=

ss

ssKsC . (Eq. 2)

This controller may not be the best one possible; however,

it does stabilize the magnetic bearing. In this study, itserves as the target for digital approximation.

0-7803-7896-2/03/$17.00 2003 IEEE 1080Proceedings of the American Control Conference

Denver, Colorado June 4-6, 2003

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The circuit in Figure 1 was used to test the closed-loop

response of the system to a disturbance input. A plot

showing the disturbance input as a step, along with the

outputs from the plant and the compensator, is shown in

Figure 2. The plots were obtained using a gain factor of

200K , which was chosen experimentally by finding the

narrow middle ground between an overly soft bearing (K

too low) and audible ringing (K too high). Figure 3 shows

the analog controllers experimental open-loop response toa step input. For the step input size chosen, the

compensator output saturates near the 15-Volt supply

voltages during the brief transient following each step.

For digital implementations, discrete-time approximationsof this controller are determined and implemented on FPGA

and DSP platforms. The plots of Figures 2 and 3 provide a

basis for comparison to similar plots for the digitalcontrollers that are included in Section 5.

4 Experimental Set-up

The FPGA- and DSP-based implementations are discretized

versions of the continuous-time second-order compensatorgiven in Equation 2. The basic set-up is the same for both

implementations and can be seen in Figure 4.

P(s)

C(z) ADCDAC

Signal

Conditioning

Signal

Conditioning

Figure 4: Block diagram of digital control system for the

magnetic bearing application

Both digital controllers were implemented on evaluation

boards. Each board had an analog-to-digital converter

(ADC) and a digital-to-analog converter (DAC), in addition

to the processing device used to implement C(z). Ananalog interface signal conditioning circuit is required to

connect the magnetic bearing to the FPGA and DSP boardsdue to a mismatch between the input and output spaces of

the magnetic bearing rig and the respective ADC and DAC.

Table 1 shows a comparison of parts for the FPGA and

DSP platforms with their respective part numbers.

Table 1: Components and part numbers for the

evaluation boards

Device ADC DAC

DSP

Board

Motorola part #

XC56F805FV80Clock: 80 Mhz

Integrated in

the DSPConversion

time: 1.7 s12-bit (10 bitsused)

MAX5251B

Conversiontime: 200 ns10-bit

FPGA

Board

Altera APEX part #

EP20K200EBC652-1XClock: 40 MHz

THS5651AIPW


AD9203ARU


C(s)

P(s)input

disturbanceplant

output

compensator

output

Figure 1: Block diagram of input disturbance

experiment

Figure 2: Closed-loop response of the analog

controller to a step disturbance

Figure 3: Open-loop step response of the analog

controller

1081Proceedings of the American Control Conference


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Discretization was performed in MATLAB using both the

Tustin and matched transform methods. Tustin was the

preferred method; however, the matched transform was

used whenever Tustin resulted in a controller that suffered

from ringing. Both the FPGA- and DSP-based controllerswere implemented in a direct-form realization, which

implements the difference equation

)2()1()2()1()()(

++=

kyekydkuckubkuaky

(Eq. 3)

where u(k)is the input to the controller,y(k) is the output ofthe controller, and athrough eare the constant coefficients.

This realization requires four registers: two for past values

of u(k) and two for past values ofy(k).

At each iteration, the controller must read a sample of

position sensor data from the ADC, compute the

appropriate value of y(k) using Equation (3), and send theresult to the DAC to provide the current amplifier input.

The maximum sample rate is determined by how quickly

the hardware can achieve these three steps. The FPGA far

outperforms the DSP, not only because it computes morequickly, but also because it tolerates more overlap between

operations from one iteration to the next.

4.1 DSP-Based Implementation

To obtain the maximum possible speed, the DSP wasprogrammed for fixed-point arithmetic. The difference

equation is implemented as a C-level instruction and

optimized by the Metrowerks Codewarrior [9] compiler.Three interrupt service routines (ISRs) trigger all

operations. The first starts an analog-to-digital conversion.

The second reads the ADC result, computes y(k), and starts

the DAC. The third forwards the value ofy(k) to the DAC

output. Since two ISRs cannot execute concurrently,overlap of iterations is limited. The timing of the iterations

is shown in Figure 5. The thicker lines depict the actual

execution of instructions on the processor and thedownward pointing arrows indicate the interrupts. The

shortest possible sampling period was found to be 11 s.

4.2 FPGA-based implementation

Two versions of FPGA-based control were implemented.

One maximized the sampling frequency, and the other hadthe same sampling frequency as the fixed-point DSP

version. Both FPGA-based designs were implemented with

VHDL using Alteras Quartus II version 1.1 development

tool [3]. There are three main components to the hardware:conversion functions mapping the ADC to the controller

and the controller to the DAC, miscellaneous overhead, and

the controllers difference equation. The ADC and DACare hard-wired to run continuously, so no additional

VHDL-generated hardware is required for their control. All

numbers relevant to the control of the system are

represented as twos complement.

The controller is programmed to expect an output range of16 Volts from the plant and to produce an input range of 8

Volts to the plant. However, the input space of the ADC

and the output space of DAC are 2 Volts peak-to-peak.

Conversion functions, implemented as simple binary point

shifts, are required because of the mismatch in the ranges of

the controller and the ADC and DAC. Overhead for thecode includes a counter to trigger events and phase-locked

loop code for the DAC clock.

The entire difference equation is computed usingcombinational logic. Each multiplication operation has its

own hardware multiplier. The five resulting products are

computed in parallel and then summed. The ability to

parallelize the computations gives the FPGA a large speed

advantage over the DSP, which must do the multiplicationsone at a time on a single multiplier. The output of the

controller is saturated at 8 Volts, which is the maximummagnitude that the magnetic bearing plant can accept, and

then truncated to 10 bits, to match the input to the DAC.

The recursive feedback is truncated, but not saturated;however, enough bits are used so that overflow does not

occur. Input and output are 10 bits and are registered at the

sampling frequency. Worst-case propagation delays werecalculated at 85 ns. After adding a safety margin, a

sampling time of 100 ns was chosen. The timing for theFPGA system is shown in Figure 6. By comparing this

figure with Figure 5, it is evident that the FPGA allows

significantly more overlap from iteration to iteration thanthe DSP.

Unlike the DSP, the FPGA allows customized bit-widths in

any point of a computation. Although this means that

careful attention must be paid to binary point placement, it

turns out to be a major advantage of FPGA-basedimplementation. There is only one variable that has a fixed

precision: the sample obtained from the ADC, which is

fixed at 10 bits. Other than that, the precision in thecoefficients, the products, and the recursive terms is left upto the designer.

Many bit-widths were experimented with to determine the

appropriate precision for each calculation. The intention

was to use only as many bits as necessary to obtain

ADC

ADC DAC

DACComputation

Computation

iteration i

iteration i+1

time

Figure 5: Timing for DSP-based implementation

ADC

ADC DAC

DACComputation

Computation

iteration i

iteration i+1

time

Figure 6: Timing for FPGA-based implementation



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acceptable controller performance. The representation of

the controller coefficients was considered first. The

resolution of the coefficients was chosen to ensure that the

poles and zeros of the compensator would be sufficiently

close to their nominal values. As sampling frequencyincreases, the poles and zeros approach the unit circle, and

the effect of the truncation on the coefficients become more

critical. As a result, higher resolution coefficients are

required as sampling frequency increases.

The number of bits to feed back in the recursive terms of

the difference equation was considered next. The required

number of bits depends on the maximum range, and the

desired resolution of the variable y(k). The minimumnumber of feedback bits needed to stabilize the system was

experimentally determined for each version of the

controller implemented. As with the coefficients, moreaccuracy, in the form of larger bit-widths, is required as the

sampling time decreases.

5 Results

In terms of speed, the FPGA really shines. The FPGA-based implementation is two orders of magnitude faster

than the DSP-based implementation. For the second-order

magnetic bearing controller, the FPGA has a computationtime of 85 ns and a sampling period of 100 ns, while the

DSP has a computation time of 7 s and a sampling period

of 11 s. Both the 100-ns FPGA and the 11-s DSPrealizations are fully optimized. The difference in speed is

overwhelming, and should bring attention to the use of

FPGA-based controllers for applications where digital

control was previously impractical because of the short

sampling period required.

Figure 7 shows experimental plots of the open-loop stepresponse of the 11-s version of the DSP-based controller,

and the 11-s and 100-ns versions of the FPGA-based

controller. For each controller, the open-loop response

saturates at 8 Volts during the transient following each

step because the code was written to saturate the output of

the compensator at 8 Volts. The FPGA-based controllers

both have less noise than the DSP-based controller has.This is because the DSP implementation requires the use of

16 bits throughout the computation, but the FPGA

implementation uses more resolution in the recursive terms,where the computation is more sensitive to truncation

effects, and less for the coefficients, where the sensitivity is

not as great. Table 2 details the bit-widths used in thedifferent implementations. Fewer total bits are used in the

FPGA-based controller than in the DSP-based controller;

hence, the FPGA gives better performance (less noise),

using less register space (fewer total bits).

To compare the disturbance rejection properties of the

controllers, a step disturbance input was applied to theclosed-loop system using the set-up shown in Figure 1.

Results are shown in Figure 8 for the DSP-based 11-s,

FPGA-based 11-s, and FPGA-based 100-ns controllers.Each plot shows the disturbance, the output from the plant,

and the output from the controller. As with the analog

controller, the gain of each digital controller was chosen byexperimental tuning. The FPGA-based controllers use a

gain factor of 100K , and the DSP-based controller uses a

gain factor 60K . The closed-loop response amplitudes

show that the FPGA-based controllers regulate the plant

output better than the DSP-based controller.

An additional disturbance rejection experiment tested how

large an impulse type disturbance the controller could

tolerate and still control the magnetic bearing. The MBC500 system has a light that turns on to indicate that a

particular axis is floating; for this experiment, the criterion

for tolerating the disturbance is that the light is steadilyon. The results from this experiment can be seen in Table

3. The FPGA-based implementations tolerated largerdisturbances than the DSP-based implementation.

A cost comparison of the two platforms of digital controller

implementation involves only the cost of the hardware

Table 2: Bit-widths used in each implementation. The bit-width notation is (n, f), where there are ntotal bits and

the least significant bit is in the 2fs place

Compensator CoefficientsQuantity

a b c d e

Feedbacky(k-1)

Feedbacky(k-2)

TotalBits

100 nsFPGA

(28, -20) (29, -20) (28, -20) (21, -20) (22, -20) (32, -18) (32, -18) 160

11 sFPGA

(14, -8) (13, -6) (14, -8) (14, -18) (13, -12) (20, -10) (20, -10) 108

11 s

DSP

(16, -10) (16, -10) (16, -11) (16, -15) (16, -15) (16, -6) (16, -6) 112

Table 3: Comparison of tolerance of impulse-type disturbance

Implementation DSP 11 s FPGA 11 s FPGA 100 ns

Largest Amplitude Impulse Disturbance Tolerated 0.77 volts 1.75 volts 1.84 volts



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components. Table 4 breaks down the costs of the required

components. The price of the FPGA reported is not for the

FPGA used. The FPGA used was part of a development

board and much larger than what was required for this

design. Therefore, the price reported is for an AlteraEPF10K30EFC256-1 FPGA, which is large enough to

support the hardware design required for this work. Since

the DSP used has a built-in ADC, that component is not

listed in the table. As seen in the table, the FPGA is moreexpensive than the DSP.

Table 4: Cost breakdown of required components in

U.S. dollars

Processing

Device

ADC DAC Total

Cost

FPGA 122.00 [4] 17.21 [12] 10.81 [12] 150.02

DSP 21.93 [6] N/A 13.94 [6] 35.87

A hardware comparison is difficult to make because the

DSP hardware is fixed and the FPGA hardware is customgenerated. A brief comparison will be presented on ahardware component level. Since ultra-high performance

was sought for the 100-ns FPGA-based controller, all of the

multiplies and adds are done in parallel. This amounts to

five 2-input multipliers and four 2-input adders. However,

this amount of parallelism is not really required; it was usedonly to show the capabilities of an FPGA-based controller.

An FPGA-based controller could be scheduled to use one

multiplier and one adder. It would then have approximately

the same hardware components as the DSP, but would stillbe more than an order of magnitude faster. An advantage

of the FPGA is the ability to make a trade-off betweenhardware size (cost) and speed; high performance systems

utilize parallel hardware, requiring a larger FPGA, while ifcost is an issue, serial hardware can be made to fit on a

smaller, less expensive FPGA.

6 Conclusions

An FPGA-based digital controller was shown to have many

advantages over a DSP-based implementation in a directcomparison of the controllers in a magnetic bearing test rig.

The FPGA offers a computation speed two orders of

magnitude faster than a DSP. In addition, the flexibility in

choosing bit-widths for proper resolution in various pointsof the computation was stressed as a major advantage of the

FPGA-based controller. The results showed that thisflexibility in the resolution resulted in a controller that

contains less noise in its response, and has a higher

tolerance for noise, without using more register space than aDSP-based controller. While the FPGA does cost more, the

benefits achieved out-weigh the cost disadvantage for this

application.

References

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[3] Altera Corporation, www.altera.com.

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(a) the DSP-based 11 s controller

(b) the FPGA-based 11 s controller

(c) the FPGA-based 100 ns controller

Figure 7: Open-loop step responses of the digital

controllers

(a) the DSP-based 11 s controller

(b) the FPGA-based 11 s controller

(c) the FPGA-based 100 ns controller

Figure 8: Closed-loop responses of the digital controllers

to a step disturbance



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