Wireless Security System

Noel CampbellVivek Shah

Raymond Tong

TA: Javier Castro

Video Surveillance Block Diagram

Video Capture Overview

CameraADV7185

Composite Intv_in_ycrcb

[19:0]

Clock_27MHz

tv_clock

Memory Controller

Dual-Port Block

Memory

VGA Controller

ycrcb [29:0]

X

WE

Y

ADDR

YCrCb to RGB

Converter

Display

NTSC Decoder

20 30

Async FIFO

Clock_27MHz

Z

RGB

Syncing and blanking signals

encode_busy

writing_memory

Y isolator

8

Y [7:0]

Technical Considerations

Synchronization of dataADV7185 clock vs lab kit 27 MHz clock

Displaying data in VGAAcquire 240 X 240 real time video

Write data to block memory then continuously read from it

Memory ControllerWrite a frame worth of data into block memory for

encoding and transmission

Video Compression

Discrete Cosine Transform

Inverse Discrete Cosine Transform

512 bits/block

56 bits/block

Video Encoder

8

Dual PortBlock

Memory(64x900)

Dual PortBlock

Memory(64x900)

Dual PortBlock

Memory(64x900)

Dual PortBlock

Memory(64x900)

Dout

64

Dout

64

Dout

64

Dout

64

Multiplier Block

Finite State MachineAddress (10)

Adder BlockAnd

Truncate Module

Matrix_int0

144

Matrix_int1

144

Matrix_int2

144

Matrix_int3

144

144Multiplier

BlockAdder Block

288

288

288

288

DCT Coefficients

DCT Coefficients

Encoding_line (10)

Wireless_busy

Dual PortBlock

Memory(80x900)

Address (10) and WE

Line_write (5)

Wireless Transmission Data is sent serially from the

labkit to the wireless kit

Data is assembled into packets and sent from camera-end to fixed-end via CC2420 radio

Data is then sent serially from receiver wireless kit to the receiver labkit

Transmitter

80 x 900Dual Port

BRAM

80Radio

Transmitter

to receiver

serialcable

Transmitter Control Unit

ShiftRegister

RS232Sender

from encoder

8

FPGA microcontroller

Receiver

80 x 900Dual Port

BRAM

Transmitter Control Unit

RS232Receiver

ShiftRegister

80Radio

Receiverserialcable

from transmitter

to decoder

FPGAmicrocontroller

Video Decoder

Address

Registers(80) Dout

80

Multiplier Block

Finite State Machine

Adder Block

Matrix_int0

144

Matrix_int1

144

144

144

144

144

Multiplier Block

Adder Block

288

288

288

288

DCT Coefficients

DCT Coefficients

LINE_DONE (5)

LINE_READ (5)

Address (10) and WE

Block_done

Ready

Dual PortBlock

Memory(64x900)

Dual PortBlock

Memory(64x900)

Dual PortBlock

Memory(64x900)

Dual PortBlock

Memory(64x900)

64

64

64

64

Video Display Overview

Y [7:0]

Dual-Port Block

Memory

8

VGA Controller

YCrCb to RGB

ConverterDisplay

Z

RGB

Syncing and blanking signals

Addr X

Delay

Z

* Only chrominance (Y) is important if displaying grayscale image

Clock_27MHz

to all modules

decode_done Memory Controller