wire less remote control ing motorrieside scrcu jack system opening &closing system

8/3/2019 Wire Less Remote Control Ing Motorrieside Scrcu Jack System Opening &Closing System

1/86

WIRE LESS REMOTE CONTROLING

MOTORRIESIDE SCRECU JACK

OPENING &CLOSING SYSTEM

Abstract

Now a day's every system is WIRE LESS REMOTE CONTROLING in order to face

new challenges in the present day situation. WIRE LESS REMOTE CONTROLING have

less manual operations, so that the flexibility, reliabilities are high and accurate. Owing to

this the demand, hence every field prefers automated control systems. Especially in the field

of electronics automated systems are doing better performance. In the present scenario of war

situations, unmanned systems plays very important role to minimize human losses. So this

Vehicle is very useful to do operations, such as detection of enemies and to find human

bodies and so many things.

In this system, mechanically aVehicle is fitted withtwomotors. Switches are

used to control all operations. This is based on communication between Switches

and robot and is done through RF. In this project we use two motors are used to

operate the robot.

In this project we will control the direction of the robot. By using the the RF

communication, through the switches, the robot will get communicated. And thereby

the information will be transferred through the switches through the RF. By giving

the commands just like go, Back, left, right the robot will be received through

the RF receiver then the robot will moves in that particular direction.


2/86

Block Diagram:

RF Transmitter Module

For Transmitter Selection

s1

s2

s2

RF Receiver Module:

Circuit Diagram for RF Transmitter Module:

Micro

Controller

DC

Motor

Encoder

HT12E

RF

Transmitter

Module

RF

Receiver

Module

Micro

ControllerDecoder

HT12D

L

2

9

3

D


3/86

X TA L 218

X TA L 119

A L E30

E A31

P S E N29

R S T9

P 0. 0 /A D 0 39

P 0. 1 /A D 138

P 0. 2 /A D 237

P 0. 3 /A D 336

P 0. 4 /A D 435

P 0. 5 /A D 534

P 0. 6 /A D 633

P 0. 7 /A D 732

P 1 .01

P 1 .12

P 1 .23

P 1 .34

P 1 .4

5

P 1 .56

P 1 .67

P 1 .78

P 3 .0 /R X D10

P 3 .1 /TX D11

P 3 .2 /IN T012

P 3 .3 /IN T113

P 3 .4 /T0

14

P 3 .7 /R D17

P 3 .6/W R16

P 3 .5 /T115

P 2 .7 /A 1 528

P 2 .0 /A 821

P 2 .1 /A 922

P 2 .2 /A 1 023

P 2 .3 /A 1 124

P 2 .4 /A 1 225

P 2 .5 /A 1 326

P 2 .6 /A 1 427

U 1

A T 89 C 51

D7

14

D6

13

D5

12

D4

11

D3

10

D2

9

D1

8

D0

7

E

6

RW

5

RS

4

VSS

1

VDD

2

VEE

3

L C D 1L M 0 1 6 L

TLP-434

Transm

itter

H

T

1

2

E

1

2

3

4

5

6

7

8

9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

G N D

R 1

1 M

V C C

1

2

3

4

5

6

v c c

G N D

R F I/P

R F O /P

R F T ra n s m itte r M o d u le

Circuit Diagram for RF Module:


4/86

X T A L 21 8

X T A L 11 9

A L E3 0

E A3 1

P S E N2 9

R S T9

P 0 .0 /A D 03 9

P 0 .1 /A D 13 8

P 0 .2 /A D 23 7

P 0 .3 /A D 33 6

P 0 .4 /A D 43 5

P 0 .5 /A D 53 4

P 0 .6 /A D 63 3

P 0 .7 /A D 73 2

P 1 .01

P 1 .12

P 1 .23

P 1 .34

P 1 .45

P 1 .56

P 1 .67

P 1 .78

P 3 .0 /R X D1 0

P 3 .1 /T X D1 1

P 3 .2 /IN T 01 2

P 3 .3 /IN T 11 3

P 3 . 4 / T01 4

P 3 .7 /R D1 7

P 3 .6 /W R1 6

P 3 . 5 / T11 5

P 2 .7 /A 1 52 8

P 2 .0 /A 82 1

P 2 .1 /A 92 2

P 2 .2 /A 1 02 3

P 2 .3 /A 1 12 4

P 2 .4 /A 1 22 5

P 2 .5 /A 1 32 6

P 2 .6 /A 1 42 7

U 1

A T 8 9 C 5 1

D

7

14

D

6

13

D

5

12

D

4

11

D

3

10

D

2

9

D

1

8

D

0

7

E

6

RW

5

R

S

4

VSS

1

VDD

2

VEE

3

L C D 1L M 0 1 6 L

RL

P

-

434

R

e

ceiver

H

T

1

2

D

1

2

3

4

5

6

7

8

9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1 0

R 1

5 6 K

V C C

1

2

3

4

5

6

G N D

R F I /P

R F O /P

O P E N

7

8

G N D

V C C

G N D

R F R e c e i v e r M o d u le

L

2

9

3

D

1

2

3

4

5

6

7

89

1 6

1 5

1 4

1 3

1 2

1 1

1 0

INDEX

Hardware Used:

89c51 Microcontroller


5/86

Voltage regulator 7805. Diode IN4007 L293D DC Motor RLP-434 TLP-434 HT12E HT12D RF Antenna

Description:

Here in this project, the digital data is transmitted to the Micro controller

through switches for the Vehicle. Here in the transmitter section, an encoder is used

which helps in encoding the parallel digital value to serial digital value and RF

Transmitter module coverts this into the required carrier wave signal.

The RF Receiver fetches the data from the RF Transmitter. When the address

and data pin gets matched the decoder decodes the serial data parallel to the micro

controller. The DC motor gets control through the micro controller using the driver IC

L293D for the robot to move.

MICROCONTROLLERS:

Microprocessors and microcontrollers are widely used in embedded

systems products. Microcontroller is a programmable device. A microcontroller

has a CPU in addition to a fixed amount of RAM, ROM, I/O ports and a timerembedded all on a single chip. The fixed amount of on-chip ROM, RAM and


6/86

number of I/O ports in microcontrollers makes them ideal for many applications

in which cost and space are critical.

The Intel 8051 is Harvard architecture, single chip microcontroller (C)

which was developed by Intel in 1980 for use in embedded systems. It was

popular in the 1980s and early 1990s, but today it has largely been superseded

by a vast range of enhanced devices with 8051-compatible processor cores that

are manufactured by more than 20 independent manufacturers including Atmel,

Infineon Technologies and Maxim Integrated Products.

8051 is an 8-bit processor, meaning that the CPU can work on only 8 bits

of data at a time. Data larger than 8 bits has to be broken into 8-bit pieces to be

processed by the CPU. 8051 is available in different memory types such as UV-

EPROM, Flash and NV-RAM.

The present project is implemented on Keil Uvision. In order to program

the device, Proload tool has been used to burn the program onto the

microcontroller.

The features, pin description of the microcontroller and the software tools

used are discussed in the following sections.

FEATURES OF AT89s52:


7/86

8K Bytes of Re-programmable Flash Memory.

RAM is 256 bytes.

4.0V to 5.5V Operating Range.

Fully Static Operation: 0 Hz to 33 MHzs

Three-level Program Memory Lock.

256 x 8-bit Internal RAM.

32 Programmable I/O Lines.

Three 16-bit Timer/Counters.

Eight Interrupt Sources.

Full Duplex UART Serial Channel.

Low-power Idle and Power-down Modes.

Interrupt recovery from power down mode.

Watchdog timer.

Dual data pointer.

Power-off flag.

Fast programming time.

Flexible ISP programming (byte and page mode).

Description:

The AT89s52 is a low-voltage, high-performance CMOS 8-bit microcomputer

with 8K bytes of Flash programmable memory. The device is

manufactured using Atmels high density nonvolatile memory

technology and is compatible with the industry-standard MCS-51

instruction set. The on chip flash allows the program memory to be

reprogrammed in system or by a conventional non volatile memory

programmer. By combining a versatile 8-bit CPU with Flash on a

monolithic chip, the Atmel AT89s52 is a powerful microcomputer,

which provides a highly flexible and cost-effective solution to many

embedded control applications.

In addition, the AT89s52 is designed with static logic for operation down

to zero frequency and supports two software selectable power saving modes.

The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial portand interrupt system to continue functioning. The power-down mode saves the


8/86

RAM contents but freezes the oscillator disabling all other chip functions until the

next hardware reset.

Fig: Pin diagram


9/86

Fig: Block diagram


10/86

PIN DESCRIPTION:

Vcc Pin 40 provides supply voltage to the chip. The voltage source is +5V.

GND Pin 20 is the ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin

can sink eight TTL inputs. When 1s are written to port 0 pins, thepins can be used as high impedance inputs. Port 0 can also be

configured to be the multiplexed low-order address/data bus during

accesses to external program and data memory. In this mode, P0

has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the

code bytes during Program verification. External pull-ups are

required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port

1 pins, they are pulled high by the internal pull-ups and can be

used as inputs. As inputs, Port 1 pins that are externally being

pulled low will source current (IIL) because of the internal pull-ups.

In addition, P1.0 and P1.1 can be configured to be the

timer/counter 2 external count input (P1.0/T2) and the

timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown

in the following table.

Port 1 also receives the low-order address bytes during Flash programming and

verification.


11/86

Port 2


buffers can sink/source four TTL inputs. When 1s are written to Port2 pins, they are pulled high by the internal pull-ups and can be


pulled low will source current (IIL) because of the internal pull-ups.

Port 2 emits the high-order address byte during fetches from external program

memory and during accesses to external data memory that uses

16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses

strong internal pull-ups when emitting 1s. During accesses toexternal data memory that uses 8-bit addresses (MOVX @ RI), Port

2 emits the contents of the P2 Special Function Register. The port

also receives the high-order address bits and some control signals

during Flash programming and verification.

Port 3


buffers can sink/source four TTL inputs. When 1s are written to Port

3 pins, they are pulled high by the internal pull-ups and can be


pulled low will source current (IIL) because of the pull-ups. Port 3

receives some control signals for Flash programming and

verification.

Port 3 also serves the functions of various special features of the AT89S52, asshown in the following table.


12/86

RST

Reset input. A high on this pin for two machine cycles while the oscillator is

running resets the device. This pin drives high for 98 oscillator

periods after the Watchdog times out. The DISRTO bit in SFR AUXR

(address 8EH) can be used to disable this feature. In the default

state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG

Address Latch Enable (ALE) is an output pulse for latching the low byte of the

address during accesses to external memory. This pin is also the

program pulse input (PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator

frequency and may be used for external timing or clocking

purposes. Note, however, that one ALE pulse is skipped during each

access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH.

With the bit set, ALE is active only during a MOVX or MOVC

instruction. Otherwise, the pin is weakly pulled high. Setting the

ALE-disable bit has no effect if the microcontroller is in external

execution mode.


13/86

PSEN

Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S52 is executing code from external program

memory, PSEN is activated twice each machine cycle, except that

two PSEN activations are skipped during each access to external

data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the

device to fetch code from external program memory locations

starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is

programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions. This pin also

receives the 12-volt programming enable voltage (VPP) during

Flash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock

operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Connections


14/86

C1, C2 = 30 pF 10 pF for Crystals

= 40 pF 10 pF for Ceramic Resonators

External Clock Drive Configuration

XTAL1 and XTAL2 are the input and output, respectively, of an inverting

amplifier that can be configured for use as an on-chip oscillator.

Either a quartz crystal or ceramic resonator may be used. To drive

the device from an external clock source, XTAL2 should be left

unconnected while XTAL1 is driven. There are no requirements on

the duty cycle of the external clock signal, since the input to the

internal clocking circuitry is through a divide-by-two flip-flop, but

minimum and maximum voltage high and low time specifications

must be observed.


15/86

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR)

space is shown in the following table.

It should be noted that not all of the addresses are occupied and unoccupied

addresses may not be implemented on the chip. Read accesses to

these addresses will in general return random data, and write

accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be

used in future products to invoke new features. In that case, the

reset or inactive values of the new bits will always be 0.

Timer 2 Registers:

Control and status bits are contained in registers T2CON and T2MOD for Timer

2. The register pair (RCAP2H, RCAP2L) is the Capture/Reload

register for Timer 2 in 16-bit capture mode or 16-bit auto-reload

mode.

Interrupt Registers:

The individual interrupt enable bits are in the IE register. Two priorities can be

set for each of the six interrupt sources in the IP register.


16/86


17/86


18/86

Dual Data Pointer Registers:

To facilitate accessing both internal and external data memory, two banks of 16-

bit Data Pointer Registers are provided: DP0 at SFR address

locations 82H-83H and DP1 at 84H and 85H. Bit DPS = 0 in SFR

AUXR1 selects DP0 and DPS = 1 selects DP1. The user should

ALWAYS initialize the DPS bit to the appropriate value before

accessing the respective Data Pointer Register.

Power Off Flag:

The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF isset to 1 during power up. It can be set and rest under software

control and is not affected by reset.


19/86

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory.

Up to 64K bytes each of external Program and Data Memory can be

addressed.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external

memory. On the AT89S52, if EA is connected to VCC, program

fetches to addresses 0000H through 1FFFH are directed to internal

memory and fetches to addresses 2000H through FFFFH are to

external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes

occupy a parallel address space to the Special Function Registers.

This means that the upper 128 bytes have the same addresses as

the SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the

address mode used in the instruction specifies whether the CPU

accesses the upper 128 bytes of RAM or the SFR space.Instructions which use direct addressing access the SFR space.


20/86

For example, the following direct addressing instruction accesses the SFR at

location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For

example, the following indirect addressing instruction, where R0

contains 0A0H, accesses the data byte at address 0A0H, rather

than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper

128 bytes of data RAM are available as stack space.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be

subjected to software upsets. The WDT consists of a 14-bit counter

and the Watchdog Timer Reset (WDTRST) SFR. The WDT is

defaulted to disable from exiting reset. To enable the WDT, a user

must write 01EH and 0E1H in sequence to the WDTRST register

(SFR location 0A6H).

When the WDT is enabled, it will increment every machine cycle while the

oscillator is running. The WDT timeout period is dependent on the

external clock frequency. There is no way to disable the WDT

except through reset (either hardware reset or WDT overflow

reset). When WDT overflows, it will drive an output RESET HIGH

pulse at the RST pin.


21/86

Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the

WDTRST register (SFR location 0A6H). When the WDT is enabled, the user

needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT

overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH), and this

will reset the device. When the WDT is enabled, it will increment every machine

cycle while the oscillator is running. This means the user must reset the WDT at

least every 16383 machine cycles.

To reset the WDT the user must write 01EH and 0E1H to WDTRST.

WDTRST is a write-only register. The WDT counter cannot be read or written.

When WDT overflows, it will generate an output RESET pulse at the RST pin. The

RESET pulse duration is 98xTOSC, where TOSC = 1/FOSC. To make the best use

of the WDT, it should be serviced in those sections of code that will periodically

be executed within the time required to prevent a WDT reset.

WDT during Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops.

While in Power down mode, the user does not need to service the

WDT. There are two methods of exiting Power-down mode: by a

hardware reset or via a level-activated external interrupt which is

enabled prior to entering Power-down mode. When Power-down is

exited with hardware reset, servicing the WDT should occur as it

normally does whenever the AT89S52 is reset. Exiting Power-down

with an interrupt is significantly different.

The interrupt is held low long enough for the oscillator to stabilize. When the

interrupt is brought high, the interrupt is serviced. To prevent the


22/86

WDT from resetting the device while the interrupt pin is held low,

the WDT is not started until the interrupt is pulled high. It is

suggested that the WDT be reset during the interrupt service for

the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-

down, it is best to reset the WDT just before entering Power-down

mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to

determine whether the WDT continues to count if enabled. The

WDT keeps counting during IDLE (WDIDLE bit = 0) as the default

state. To prevent the WDT from resetting the AT89S52 while in

IDLE mode, the user should always set up a timer that will

periodically exit IDLE, service the WDT, and reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode

and resumes the count upon exit from IDLE.

UART

The Atmel 80C51 Microcontrollers implement three general purpose, 16-bit

timers/ counters. They are identified as Timer 0, Timer 1 and Timer 2 and can

be independently configured to operate in a variety of modes as a timer or as an

event counter. When operating as a timer, the timer/counter runs for a

programmed length of time and then issues an interrupt request. When

operating as a counter, the timer/counter counts negative transitions on an

external pin. After a preset number of counts, the counter issues an interrupt

request. The various operating modes of each timer/counter are described in the

following sections.

A basic operation consists of timer registers THx and TLx (x= 0, 1) connected in

cascade


23/86

to form a 16-bit timer. Setting the run control bit (TRx) in TCON register turns

the timer on by allowing the selected input to increment TLx. When TLx

overflows it increments THx; when THx overflows it sets the timer overflow flag

(TFx) in TCON register. Setting the TRx does not clear the THx and TLx timer

registers. Timer registers can be accessed to obtain the current count or to enter

preset values. They can be read at any time but TRx bit must be cleared to

preset their values, otherwise the behavior of the timer/counter is unpredictable.

The C/Tx# control bit (in TCON register) selects timer operation, or counter

operation, by selecting the divided-down peripheral clock or external pin Tx as

the source for the counted signal. TRx bit must be cleared when changing the

mode of operation, otherwise the behavior of the timer/counter is unpredictable.

For timer operation (C/Tx# = 0), the timer register counts the divided-down

peripheral clock. The timer register is incremented once every peripheral cycle

(6 peripheral clock periods). The timer clock rate is FPER / 6, i.e. FOSC / 12 in

standard mode or FOSC / 6 in X2 mode. For counter operation (C/Tx# = 1), the

timer register counts the negative transitions on the Tx external input pin. The

external input is sampled every peripheral cycle. When the sample is high in one

cycle and low in the next one, the counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative

transition,

the maximum count rate is FPER / 12, i.e. FOSC / 24 in standard mode or

FOSC / 12 in X2 mode. There are no restrictions on the duty cycle of theexternal input signal, but to

ensure that a given level is sampled at least once before it changes, it should be

held for

at least one full peripheral cycle. In addition to the timer or counter

selection, Timer 0 and Timer 1 have four operating modes from which to select

which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1and 2 are the

same for both timer/counters. Mode 3 is different.


24/86

The four operating modes are described below. Timer 2, has three modes of

operation: capture, auto-reload and baud rate generator.

Timer 0

Timer 0 functions as either a timer or event counter in four modes of operation.

Timer 0 is controlled by the four lower bits of the TMOD register and bits 0, 1, 4

and 5 of the TCON register. TMOD register selects the method of timer gating

(GATE0), timer or counter operation (T/C0#) and mode of operation (M10 and

M00). The TCON register provides timer 0 control functions: overflow flag (TF0),

run control bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For normal timer operation (GATE0= 0), setting TR0 allows TL0 to be

incremented by

the selected input. Setting GATE0 and TR0 allows external pin INT0# to control

timer

operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag, generating

an interrupt request. It is important to stop timer/counter before changing

mode.

Mode 0 (13-bit Timer)


25/86

Mode 0 configures timer 0 as a 13-bit timer which is set up as an 8-bit timer

(TH0 register) with a modulo 32 prescaler implemented with the lower five bits

of the TL0 register. The upper three bits of TL0 register are indeterminate and

should be ignored. Prescaler overflow increments the TH0 register.

As the count rolls over from all 1s to all 0s, it sets the timer interrupt flag TF0.

The counted input is enabled to the Timer when TR0 = 1 and either GATE = 0 or

INT0 = 1. (Setting GATE = 1 allows the Timer to be controlled by external input

INT0, to facilitate pulse width measurements). TR0 is a control bit in the Special

Function register TCON. GATE is in TMOD.

The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The

upper 3

bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0)

does not

clear the registers.

Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different

GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

Timer/Counter x (x = 0 or 1) in Mode 0


26/86


Mode 1 is the same as Mode 0, except that the Timer register is being run with

all 16

bits. Mode 1 configures timer 0 as a 16-bit timer with the TH0 and TL0 registers

connected in cascade. The selected input increments the TL0 register.


Mode 2 (8-bit Timer with Auto-Reload)

Mode 2 configures timer 0 as an 8-bit timer (TL0 register) that automatically

reloads from the TH0 register. TL0 overflow sets TF0 flag in the TCON register

and reloads TL0 with the contents of TH0, which is preset by software.

When the interrupt request is serviced, hardware clears TF0. The reload leavesTH0 unchanged. The next reload value may be changed at any time by writing it

to the TH0 register. Mode 2 operation is the same for Timer/Counter 1.



27/86

Mode 3 (Two 8-bit Timers)

Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-

bit timers. This mode is provided for applications requiring an additional 8-bit

timer or counter. TL0 uses the timer 0 control bits C/T0# and GATE0 in the

TMOD register, and TR0 and TF0 in the TCON register in the normal manner.

TH0 is locked into a timer function (counting FPER /6) and takes over use of the

timer 1 interrupt (TF1) and run control (TR1) bits. Thus, operation of timer 1 is

restricted when timer 0 is in mode 3.

Timer/Counter 0 in Mode 3: Two 8-bit Counters

Timer 1

Timer 1 is identical to timer 0, except for mode 3, which is a hold-count mode.

The following comments help to understand the differences:

Timer 1 functions as either a timer or event counter in three modes of

operation. Timer


28/86

1s mode 3 is a hold-count mode.

Timer 1 is controlled by the four high-order bits of the TMOD register and bits

2, 3, 6 and 7 of the TCON register. The TMOD register selects the method of

timer gating (GATE1), timer or counter operation (C/T1#) and mode of

operation (M11 and M01). The TCON register provides timer 1 control functions:

overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type

control bit (IT1).

Timer 1 can serve as the baud rate generator for the serial port. Mode 2 is best

suited for this purpose.

For normal timer operation (GATE1 = 0), setting TR1 allows TL1 to be

incremented by the selected input. Setting GATE1 and TR1 allows external pin

INT1# to control timer operation.

Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag

generating an interrupt request.

When timer 0 is in mode 3, it uses timer 1s overflow flag (TF1) and run

control bit (TR1). For this situation, use timer 1 only for applications that do not

require an interrupt (such as a baud rate generator for the serial port) and

switch timer 1 in and out of mode 3 to turn it off and on.

It is important to stop timer/counter before changing modes.


Mode 0 configures Timer 1 as a 13-bit timer, which is set up as an 8-bit timer(TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of

the TL1 register. The upper 3 bits of the TL1 register are ignored. Prescaler

overflow increments the TH1 register.


Mode 1 configures Timer 1 as a 16-bit timer with the TH1 and TL1 registersconnected


29/86

in cascade. The selected input increments the TL1 register.

Mode 2 (8-bit Timer with Auto Reload)

Mode 2 configures Timer 1 as an 8-bit timer (TL1 register) with automatic reload

from

the TH1 register on overflow. TL1 overflow sets the TF1 flag in the TCON register

and reloads TL1 with the contents of TH1, which is preset by software. The

reload leaves TH1 unchanged.

Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used

to halt

Timer 1 when TR1 run control bit is not available i.e., when Timer 0 is in mode

3.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event

counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown

in Table 5-2). Timer 2 has three operating modes: capture, auto-reload (up or

down counting), and baud rate generator. The modes are selected by bits in

T2CON, as shown in Table 10-1. Timer 2 consists of two 8-bit registers, TH2 andTL2. In the Timer function, the TL2 register is incremented every machine cycle.

Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of

the oscillator frequency.


30/86

In the Counter function, the register is incremented in response to a 1-to-0

transition at its corresponding external input pin, T2. In this

function, the external input is sampled during S5P2 of every

machine cycle. When the samples show a high in one cycle and a

low in the next cycle, the count is incremented. The new count

value appears in the register during S3P1 of the cycle following the

one in which the transition was detected. Since two machine cycles

(24 oscillator periods) are required to recognize a 1-to-0 transition,

the maximum count rate is 1/24 of the oscillator frequency. To

ensure that a given level is sampled at least once before it

changes, the level should be held for at least one full machine

cycle.

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2

= 0, Timer 2 is a 16-bit timer or counter which upon overflow sets

bit TF2 in T2CON. This bit can then be used to generate an

interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but

a 1-to-0 transition at external input T2EX also causes the current

value in TH2 and TL2 to be captured into RCAP2H and RCAP2L,

respectively. In addition, the transition at T2EX causes bit EXF2 in

T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt.


31/86

Timer in Capture Mode

Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit

auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable)

bit located in the SFR T2MOD. Upon reset, the DCEN bit is set to 0 so that timer

2 will default to count up. When DCEN is set, Timer 2 can count up or down,

depending on the value of the T2EX pin.

T2MOD Timer 2 Mode Control Register

The above figure shows Timer 2 automatically counting up when DCEN = 0. In

this mode, two options are selected by bit EXEN2 in T2CON. If

EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit

upon overflow. The overflow also causes the timer registers to be

reloaded with the 16-bit value in RCAP2H and RCAP2L. The values

in Timer in Capture ModeRCAP2H and RCAP2L are preset by

software. If EXEN2 = 1, a 16-bit reload can be triggered either by


32/86

an overflow or by a 1-to-0 transition at external input T2EX. This

transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can

generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure

10-2. In this mode, the T2EX pin controls the direction of the

count. A logic 1 at T2EX makes Timer 2 count up. The timer will

overflow at 0FFFFH and set the TF2 bit. This overflow also causes

the 16-bit value in RCAP2H and RCAP2L to be reloaded into the

timer registers, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2

and TL2 equal the values stored in RCAP2H and RCAP2L. The

underflow sets the TF2 bit and causes 0FFFFH to be reloaded into

the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used

as a 17th bit of resolution. In this operating mode, EXF2 does not

flag an interrupt.


33/86

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in

T2CON. Note that the baud rates for transmit and receive can be

different if Timer 2 is used for the receiver or transmitter and Timer

1 is used for the other function. Setting RCLK and/or TCLK puts

Timer 2 into its baud rate generator mode.

The baud rate generator mode is similar to the auto-reload mode, in that a

rollover in TH2 causes the Timer 2 registers to be reloaded with the

16-bit value in registers RCAP2H and RCAP2L, which are preset by

software.

The baud rates in Modes 1 and 3 are determined by Timer 2s overflow rate

according to the following equation.

The Timer can be configured for either timer or counter operation. In most

applications, it is configured for timer operation (CP/T2 = 0). The

timer operation is different for Timer 2 when it is used as a baud

rate generator. Normally, as a timer, it increments every machine


34/86

cycle (at 1/12 the oscillator frequency). As a baud rate generator,

however, it increments every state time (at 1/2 the oscillator

frequency). The baud rate formula is given below.

Where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-

bit unsigned integer.

Timer 2 as a baud rate generator is shown in the below figure. This figure isvalid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in

TH2 does not set TF2 and will not generate an interrupt. Note too,

that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but

will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2).

Thus, when Timer 2 is in use as a baud rate generator, T2EX can be

used as an extra external interrupt.

Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate

generator mode, TH2 or TL2 should not be read from or written to.

Under these conditions, the Timer is incremented every state time,

and the results of a read or write may not be accurate. The RCAP2

registers may be read but should not be written to, because a write

might overlap a reload and cause write and/or reload errors. The

timer should be turned off (clear TR2) before accessing the Timer 2

or RCAP2 registers.


35/86

Timer 2 in Baud Rate Generator Mode

Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in

the below figure. This pin, besides being a regular I/O pin, has two

alternate functions. It can be programmed to input the external

clock for Timer/Counter 2 or to output a 50% duty cycle clock

ranging from 61 Hz to 4 MHz (for a 16-MHz operating frequency).

Timer 2 in Clock-Out Mode


36/86

To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must

be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2

(T2CON.2) starts and stops the timer. The clock-out frequency

depends on the oscillator frequency and the reload value of Timer 2

capture registers (RCAP2H, RCAP2L), as shown in the following

equation.

In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This

behavior is similar to when Timer 2 is used as a baud-rate

generator. It is possible to use Timer 2 as a baud-rate generator

and a clock generator simultaneously. Note, however, that the

baud rate and clock-out frequencies cannot be determined

independently from one another since they both use RCAP2H and

RCAP2L.

Interrupts

The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0

and INT1), three timer interrupts (Timers 0, 1, and 2), and the

serial port interrupt. These interrupts are all shown in Figure 13-1.

Each of these interrupt sources can be individually enabled or disabled by setting

or clearing a bit in Special Function Register IE. IE also contains a

global disable bit, EA, which disables all interrupts at once. Note

that Table 13-1 shows that bit position IE.6 is unimplemented. User


37/86

software should not write a 1 to this bit position, since it may be

used in future AT89 products.

Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register

T2CON. Neither of these flags is cleared by hardware when the

service routine is vectored to. In fact, the service routine may have

to determine whether it was TF2 or EXF2 that generated the

interrupt, and that bit will have to be cleared in software.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in

which the timers overflow. The values are then polled by the

circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at

S2P2 and is polled in the same cycle in which the timer overflows.


38/86


39/86

Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction thatinvokes Power-down is the last instruction executed. The on-chip

RAM and Special Function Registers retain their values until the

Power-down mode is terminated. Exit from Power down mode can

be initiated either by a hardware reset or by an enabled external

interrupt. Reset redefines the SFRs but does not change the on-

chip RAM. The reset should not be activated before VCC is restored

to its normal operating level and must be held active long enough

to allow the oscillator to restart and stabilize.

Status of External Pins during Idle and Power-down Modes

SOFTWARE USED

1. Keil u-Vision

Keil Software is used provide you with software development tools for 8051

based microcontrollers. With the Keil tools, you can generate embedded applications

for virtually every 8051 derivative. The supported microcontrollers are listed in the -

vision.


40/86

2. PRO51 Programmer Software

Description of Modules used in this project:

Power Supply:

BR1

100 uf1000 uf

LM7812 LM7805

Red led

100 ohm470 uf

I/P power

O/P power

Power supply

The power supply consists of ac voltage transformer, diode rectifier, ripple

filter, and voltage regulators. The transformer is an AC device, which increases or

decreases the input supply voltage without change in frequency. There are 2 types

of transformers. One of Step-up and the other is Step-down. Here we are using a

Step-down transformer, which decreases the 230 supply volts to 12 volts. Therectifier is a device which converts an AC voltage to the pulsating DC voltage. Here

IN4007 diodes are used as rectifiers. A bridge type full wave rectifier is constructed

using these diodes, as its efficiency is 81.2% and ripple factor is 0.482.

After the rectification, the output voltage signal contains both an average dc

component and a time varying ac component called the ripple. To reduce or

eliminate the ac component, one needs low pass filter(s). The low pass filter allows


41/86

the dc component to pass through it but attenuate the ac at 60 Hz or its harmonics,

i.e., 120 Hz. Here we use 1000Mf, 470Mf & 100Mf capacitors at the o/p and i/p of

regulators. The 12v DC output of the filter is passed through voltage regulators of

7812 & 7805. 78 indicates that it is a regulator for positive voltage. There is a

corresponding 79 model for negative voltage. 12 indicates that it has an output of

12 V. similarly we are connecting a 7805 to the 7812 regulator o/p, to generate

5volts. An LED in series to a 100ohms resistor is connected in parallel to the output

voltage to indicate the supply. And also a switch is connected in series to the o/p

voltage terminal to ON/OFF the supply.

Introduction to 8051 Microcontroller:

An Embedded product uses a microcontroller to do one task and one task

only. In an Embedded system, there is only one application software that is typically

burned into ROM. When we have to learn about a new computer we have to

familiarize about the machine capability we are using, and we can do it by studying

the internal hardware design (devices architecture), and also to know about the size,

number and the size of the registers.

A microcontroller is a single chip that contains the processor (the CPU), non-

volatile memory for the program (ROM or flash), volatile memory for input and output

(RAM), a clock and an I/O control unit. Also called a "computer on a chip," billions of

microcontroller units (MCUs) are embedded each year in a myriad of products from

toys to appliances to automobiles. For example, a single vehicle can use 70 or more

microcontrollers. The following picture describes a general block diagram of

microcontroller.

Criteria for choosing a Microcontroller:


42/86

The first and foremost criterion in choosing a micro controller is that it should

meet the task at hand efficiently and cost effectively. In analyzing the needs of a

microcontroller-based project, we must first see whether an 8-bit, 6-bit or 32-bit micro

controller can best handle the computing needs of the task most effectively.

Considerations in this category are:

1) Speed

2) Packaging i.e., if it is a DIP(dual in line) or QFP(quad flat package) or some

other

3) Power consumption

4) Amount of on chip ROM & RAM,

5) Number of I/O pins & timer on chip, cost per unit(i.e., total kit cost)

6) Availability of software development tools such as assembler, debugger,

compiler, emulator and technical support to the Microcontroller both on in-side

and out-side expertise.

7) Wide availability of Microcontroller which fulfill needed quantities or sources of

both now and in future.

In case of 8051, in leading 8-bit Microcontrollers it satisfies all the above

mentioned criteria as there are multiple suppliers with same code compatible.

The hardware is driven by a set of program instructions, or software. Once

familiar with hardware and software, the user can then apply the microcontroller to

the problems easily.


43/86

Brief History of 8051:

In 1981, Intel Corporation introduced an 8-bit microcontroller called the 8051.

This microcontroller had 128 bytes of RAM, 4K bytes of on-chip ROM, two timers,

one serial port and four ports (each 8-bits wide) all on a single chip. At the time, it

was also referred to as a system on a chip. The 8051 is an 8-bit processor,

meaning the CPU can work on only 8 bits of data at a time. Data larger than 8 bits

has to be broken into 8-bit pieces to be processed by the CPU.

The 8051 has a total of four I/O ports, each 8 bits wide. 8051 can have a

maximum of 64K bytes of ROM. The 8051 became widely popular after Intel allowed

other manufacturers to make and market any flavours of the 8051 they please with

the condition that they remain code-compatible with the 8051. This has led to many

versions of the 8051 with different speeds and amounts of on-chip ROM.

Architecture of 8051:


44/86

The architecture of the 8051 family of microcontrollers is referred to as the

MCS-51architecture, or sometimes simply as MCS-51. The microcontrollers have an

8-bit data bus. They are capable of addressing 64K of program memory and a

separate 64K of data memory. The 8051 has 4K of code memory implemented as

on-chip Read Only Memory (ROM). The 8051 has 128 bytes of internal Random

Access Memory (RAM). The 8051 has two timer/counters, a serial port, 4 general

purpose parallel input/output ports, and interrupt control logic with five sources of

interrupts. Besides internal RAM, the 8051 has various Special Function Registers

(SFR), which are the control and data registers for on-chip facilities. The SFRs also

include the accumulator, the B register, and the Program Status Word(PSW), which

contains the CPU flags. Programming the various internal hardware facilities of the

8051 is achieved by placing the appropriate control words into the corresponding

SFRs.

The 8031 is similar to the 8051, except it lacks the on-chip ROM. As stated,

the 8051 can address 64K of external data memory and 64K of external program

memory. These may be separate blocks of memory, so that up to 128K of memory

can be attached to the microcontroller. Separate blocks of code and data memory

are referred to as the Harvard architecture. The 8051 has two separate read signals,RD (P3.7) and PSEN. The first is activated when a byte is to be read from external

data memory, the other, from external program memory. Both of these signals are

so-called active low signals. That is, they are cleared to logic level 0 when activated.

All external code is fetched from external program memory. In addition, bytes

from external program memory may be read by special read instructions such as the

MOVC instruction. There are separate instructions to read from external data

memory, such as the MOVX instruction. That is, the instructions determine which

block of memory is addressed, and the corresponding control signal, either RD or

PSEN is activated during the memory read cycle. A single block of memory may be

mapped to act as both data and program memory. This is referred to as the Von

Neumann1 architecture. In order to read from the same block using either the RD.


45/86

Figure 1

The pin diagram of the 8051 shows all of the input/output pins unique to microcontrollers:

Pin Description

Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.

Pin 9: RS a logic one on this pin disables the microcontroller and clears the contents

of most registers. In other words, the positive voltage on this pin resets the

microcontroller. By applying logic zero to this pin, the program starts execution from

the beginning.

Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or

output. Besides, all of them have alternative functions:

Pin 10: RXD Serial asynchronous communication input or Serial synchronous

communication output.

Pin 11: TXD Serial asynchronous communication output or Serial synchronous

communication clock output.

Pin 12: INT0 Interrupt 0 input.

Pin 13: INT1 Interrupt 1 input.


46/86

Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM.

Pin 17: RD Read from external RAM.

Pin 18, 19:XTAL2, XTAL1 Internal oscillator input and output. A quartz crystal which

specifies operating frequency is usually connected to these pins. Instead of it,

miniature ceramics resonators can also be used for frequency stability. Later

versions of microcontrollers operate at a frequency of 0 Hz up to over 50 Hz.

Pin 20: GND Ground

Pin 21-28: Port 2If there is no intention to use external memory then these port pins

are configured as general inputs/outputs. In case external memory is used, the

higher address byte, i.e. addresses A8-A15 will appear on this port. Even though

memory with capacity of 64Kb is not used, which means that not all eight port bits

are used for its addressing, the rest of them are not available as inputs/outputs.

Pin 29: PSEN If external ROM is used for storing program then a logic zero (0)

appears on it every time the microcontroller reads a byte from memory.

Pin 30: ALE Prior to reading from external memory, the microcontroller puts the

lower address byte (A0-A7) on P0 and activates the ALE output. After receiving

signal from the ALE pin, the external register (usually 74HCT373 or 74HCT375 add-

on chip) memorizes the state of P0 and uses it as a memory chip address.

Immediately after that, the ALU pin is returned its previous logic state and P0 is now

used as a Data Bus. As seen, port data multiplexing is performed by means of only

one additional (and cheap) integrated circuit. In other words, this port is used for both

data and address transmission.

Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and

address transmission with no regard to whether there is internal memory or not. It

means that even there is a program written to the microcontroller, it will not be

executed. Instead, the program written to external ROM will be executed. By

applying logic one to the EA pin, the microcontroller will use both memories, first

internal then external (if exists).

Pin 32-39: Port 0Similar to P2, if external memory is not used, these pins can be

used as general inputs/outputs. Otherwise, P0 is configured as address output (A0-

A7) when the ALE pin is driven high (1) or as data output (Data Bus) when the ALE

pin is driven low (0).


47/86

Pin 40: VCC +5V power supply

Oscillator Characteristics:

XTAL1 and XTAL2 are the input and output, respectively, of an inverting

amplifier which can be configured for use as an on-chip oscillator, as shown in Fig 1.

Either a quartz crystal or ceramic resonator may be used. To drive the device from

an external clock source, XTAL2 should be left unconnected while XTAL1 is driven

as shown in Fig2. There are no requirements on the duty cycle of the external clock

signal, since the input to the internal clocking circuitry is through a divide-by-two flip-

flop, but minimum and maximum voltage high and low time specifications must be

observed.

Fig 1 Oscillator Connections Fig 2 External Clock Drive

Memory organization:

All 80C51 devices have separate address spaces for program and data

memory, as shown in Figures 1 and 2. The logical separation of program and data

memory allows the data memory to be accessed by 8-bit addresses, which can be

quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit data memory

addresses can also be generated through the DPTR register. Program memory

(ROM, EPROM) can only be read, not written to. There can be up to 64k bytes of


48/86

program memory. In the 80C51, the lowest 4k bytes of program are on-chip. In the

ROMless versions, all program memory is external. The read strobe for external

program memory is the PSEN (program store enable).

Data Memory (RAM)

It occupies a separate address space from Program Memory. In the 80C51,

the lowest 128 bytes of data memory are on-chip. Up to 64k bytes of external RAM

can be addressed in the external Data Memory space. In the ROM less version, the

lowest 128 bytes are on-chip. The CPU generates read and write signals, RD and

WR, as needed during external Data Memory accesses. External Program Memory

and external Data Memory may be combined if desired by applying the RD and

PSEN signals to the inputs of an AND gate and using the output of the gate as the

read strobe to the external Program/Data memory.

Figure 2

Program Memory:

Figure 3 shows a map of the lower part of the Program Memory. After reset,

the CPU begins execution from location 0000H. As shown in Figure 3, each interrupt

is assigned a fixed location in Program Memory. The interrupt causes the CPU to

jump to that location, where it commences execution of the service routine. External


49/86

Interrupt 0, for example, is assigned to location 0003H. If External Interrupt 0 is going

to be used, its service routine must begin at location 0003H. If the interrupt is not

going to be used, its service location is available as general purpose Program

Memory.

The interrupt service locations are spaced at 8-byte intervals: 0003H for

External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for

Timer 1, etc. If an interrupt service routine is short enough (as is often the case in

control applications), it can reside entirely within that 8-byte interval. Longer service

routines can use a jump instruction to skip over subsequent interrupt locations, if

other interrupts are in use.

The lowest 4k bytes of Program Memory can either be in the on-chip ROM or

in an external ROM. This selection is made by strapping the EA (External Access)

pin to either VCC, or VSS. In the 80C51, if the EA pin is strapped to VCC, then the

program fetches to addresses 0000H through 0FFFH are directed to the internal

ROM. Program fetches to addresses 1000H through FFFFH are directed to external

ROM.

If the EA pin is strapped to VSS, then all program fetches are directed toexternal ROM. The ROMless parts (8031, 80C31, etc.) must have this pin externally

strapped to VSS to enable them to execute from external Program Memory.

Figure 3


50/86

The read strobe to external ROM, PSEN, is used for all external program

fetches. PSEN is not activated for internal program fetches. The hardware

configuration for external program execution is shown in Figure 4. Note that 16 I/O

lines (Ports 0 and 2) are dedicated to bus functions during external Program Memory

fetches. Port 0 (P0 in Figure 4) serves as a multiplexed address/data bus. It emits

the low byte of the Program Counter (PCL) as an address, and then goes into a float

state awaiting the arrival of the code byte from the Program Memory. During the time

that the low byte of the Program Counter is valid on Port 0, the signal ALE (Address

Latch Enable) clocks this byte into an address latch. Meanwhile, Port 2 (P2 in Figure

4) emits the high byte of the Program Counter (PCH). Then PSEN strobes the

EPROM and the code byte is read into the microcontroller

.

Figure 4

Program Memory addresses are always 16 bits wide, even though the actual

amount of Program Memory used may be less than 64k bytes. External program

execution sacrifices two of the 8-bit ports, P0 and P2, to the function of addressing

the Program Memory.

Memory addresses can be either 1 or 2 bytes wide. One-byte addresses are

often used in conjunction with one or more other I/O lines to page the RAM, as

shown in Figure 5. Two-byte addresses can also be used, in which case the high

address byte is emitted at Port 2.


51/86

Figure 5

Internal Data Memory addresses are always one byte wide, which implies an

address space of only 256 bytes. However, the addressing modes for internal RAMcan in fact accommodate 384 bytes, using a simple trick. Direct addresses higher

than 7FH access one memory space, and indirect addresses higher than 7FH

access a different memory space. Thus Figure 6 shows the Upper 128 and SFR

space occupying the same block of addresses, 80H through FFH, although they are

physically separate entities. The Lower 128 bytes of RAM are present in all 80C51

devices as mapped in Figure 6. The lowest 32 bytes are grouped into 4 banks of 8

registers. Program instructions call out these registers as R0 through R7. Two bits in

the Program Status Word (PSW) select which register bank is in use. This allows

more efficient use of code space, since register instructions are shorter than

instructions that use direct addressing.


52/86

Figure 6

Addressing Modes

The addressing modes in the 80C51 instruction set are as follows:

Direct Addressing

In direct addressing the operand is specified by an 8-bit address field in the

instruction. Only internal Data RAM and SFRs can be directly addressed.

Indirect Addressing

In indirect addressing the instruction specifies a register which contains the

address of the operand. Both internal and external RAM can be indirectly addressed.

The address register for 8-bit addresses can be R0 or R1 of the selected bank, or

the Stack Pointer. The address register for 16-bitaddresses can only be the 16-bit

data pointer register, DPTR.

Register Instructions

The register banks, containing registers R0 through R7, can be accessed by

certain instructions which carry a 3-bit register specification within the opcode of the

instruction. Instructions that access the registers this way are code efficient, since

this mode eliminates an address byte. When the instruction is executed, one of the

eight registers in the selected bank is accessed. One of four banks is selected atexecution time by the two bank select bits in the PSW.

Register-Specific Instructions

Some instructions are specific to a certain register. For example, some

instructions always operate on the Accumulator, or Data Pointer, etc., so no address

byte is needed to point to it. The opcode itself does that. Instructions that refer to the

Accumulator as Aassemble as accumulator specific opcodes.


53/86

Immediate Constants

The value of a constant can follow the opcode in Program Memory.

For example,

MOV A, #100

loads the Accumulator with the decimal number 100. The same number could be

specified in hex digits as 64H.

Indexed Addressing

Only program Memory can be accessed with indexed addressing, and it canonly be read. This addressing mode is intended for reading look-up tables in

Program Memory A 16-bit base register (either DPTR or the Program Counter)

points to the base of the table, and the Accumulator is set up with the table entry

number. The address of the table entry in Program Memory is formed by adding the

Accumulator data to the base pointer. Another type of indexed addressing is used in

the case jump instruction. In this case the destination address of a jump instruction

is computed as the sum of the base pointer and the Accumulator

Basic Registers

The Accumulator: languages you will be familiar with the concept of an

Accumulator register. The Accumulator, as its name suggests, is used as a general

register to accumulate the results of a large number of instructions. It can hold an 8-

bit (1-byte) value and is the most versatile register the 8051 has due to the sheer

number of instructions that make use of the accumulator. More than half of the

8051s 255 instructions manipulate or use the accumulator in some way.

The "R" registers

The "R" registers are a set of eight registers that are named R0, R1, etc. up to

and including R7. These registers are used as auxiliary registers in many operations.

To continue with the above example, perhaps you are adding 10 and 20. The original

number 10 may be stored in the Accumulator whereas the value 20 may be stored

in, say, register R4.


54/86

The "B" Register

The "B" register is very similar to the Accumulator in the sense that it may

hold an 8-bit (1-byte) value. The "B" register is only used by two 8051instructions:

MUL AB and DIV AB. Thus, if you want to quickly and easily multiply or divide A by

another number, you may store the other number in "B" and make use of these two

instructions. Aside from the MUL and DIV instructions, the B register are often used

as yet another temporary storage register much like a ninth "R" register.

The Data Pointer (DPTR)

The Data Pointer (DPTR) is the 8051s only user- accessible 16-bit (2-byte)

register. The Accumulator, "R" registers, and "B" register are all 1-byte values.

DPTR, as the name suggests, is used to point to data. It is used by a number of

commands which allow the 8051 to access external memory. When the 8051

accesses external memory it will access external memory at the address indicated

by DPTR. While DPTR is most often used to point to data in external memory, many

programmers often take advantage of the fact that its the only true 16- bit register

available. It is often used to store 2- byte values which have nothing to do with

memory locations.

The Program Counter (PC):

The Program Counter (PC) is a 2-byte address which tells the 8051 where the

next instruction to execute is found in memory. When the 8051 is initialized PC

always starts at 0000h and is incremented each time an instruction is executed. It is

important to note that PC isnt always incremented by one. Since some instructions

require 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases. The

Program Counter is special in that there is no way to directly modify its value. That is

to say, you cant do something like PC=2430h. On the other hand, if you execute

LJMP 2340h youve effectively accomplished the same thing.

The Stack Pointer (SP)

The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit

(1-byte) value. The Stack Pointer is used to indicate where the next value to be


55/86

removed from the stack should be taken from. When you push a value onto the

stack, the 8051 first increments the value of SP and then stores the value at the

resulting memory location. When you pop a value off the stack, the 8051 returns the

value from the memory location indicated by SP, and then decrements the value of

SP.

Special Function Register (SFR) Memory:

Special Function Registers (SFRs) are areas of memory that control specific

functionality of the 8051 processor. For example, four SFRs permit access to the

8051s 32 input/output lines. Another SFR allows a program to read or write to the

8051s serial port. Other SFRs allow the user to set the serial baud rate, control and

access timers, and configure the 8051s interrupt system.

What is RF?

Radio frequency (RF) radiation is a subset of electromagnetic radiation with

a wavelength of 100km to 1mm, which is a frequency of 300 Hz to 3000 GHz

respectively. This range of electromagnetic radiation constitutes the radio

spectrum and corresponds to the frequency of alternating current electrical

signals used to produce and detect radio waves. RF can refer to electromagnetic

oscillations in either electrical circuits or radiation through air and space. Like other

subsets of electromagnetic radiation, RF travels at the speed of light.

The frequency of an RF signal is inversely proportional to the wavelength of

the EM field to which it corresponds. At 9 kHz, the free-space wavelength is

approximately 33 kilometers (km) or 21 miles (mi). At the highest radio frequencies,

the EM wavelengths measure approximately one millimeter (1 mm). As the

frequency is increased beyond that of the RF spectrum, EM energy takes the form of

infrared (IR), visible, ultraviolet (UV), X rays, and gamma rays.

Many types of wireless devices make use of RF fields. Cordless and cellular

telephone, radio and television broadcast stations, satellite communications

systems, and two-way radio services all operate in the RF spectrum. Some wireless

devices operate at IR or visible-light frequencies, whose electromagnetic

wavelengths are shorter than those of RF fields. Examples include most television-


56/86

set remote-control boxes, some cordless computer keyboards and mice, and a few

wireless hi-fi stereo headsets.

Designation Abbreviation Frequencies

Free-Space

Wavelengths

Very Low Frequency VLF 9 kHz - 30 kHz 33 km - 10 km

Low Frequency LF 30 kHz - 300 kHz 10 km - 1 km

Medium Frequency MF 300 kHz - 3 MHz 1 km - 100 m

High Frequency HF 3 MHz - 30 MHz 100 m - 10 m

Very High Frequency VHF 30 MHz - 300 MHz 10 m - 1 m

Ultra High Frequency UHF 300 MHz - 3 GHz 1 m - 100 mm

Super High Frequency SHF 3 GHz - 30 GHz 100 mm - 10 mm

Extremely High

FrequencyEHF 30 GHz - 300 GHz 10 mm - 1 mm

The RF spectrum is divided into several ranges, or bands. With the exception

of the lowest-frequency segment, each band represents an increase of frequency

corresponding to an order of magnitude (power of 10). The table depicts the eight

bands in the RF spectrum, showing frequency and bandwidth ranges. The SHF and

EHF bands are often referred to as the microwave spectrum.

Electromagnetic radiation (often abbreviated E-M radiation orEMR) is

a phenomenon that takes the form of self-propagating waves in a vacuum or

in matter. It consists of electric and magnetic field components which oscillate in

phase perpendicular to each other and perpendicular to the direction of

energy propagation. Electromagnetic radiation is classified into several types

according to the frequency of its wave; these types include (in order of increasing

frequency and decreasing wavelength): radio waves, microwaves, terahertz

radiation, infrared radiation, visible light, ultraviolet radiation, X-rays and gamma


57/86

rays. A small and somewhat variable window of frequencies is sensed by the eyes of

various organisms; this is what we call the visible spectrum, or light.

EM radiation carries energy and momentum that may be imparted

to matter with which it interacts.

Frequency Allocation:

The radio frequency (RF) electromagnetic spectrum is an aspect of the

physical world which, like land, water, and air, is subject to usage limitations. Use ofradio frequency bands of the electromagnetic spectrum is regulated by governments

in most countries, in a Spectrum management process known as frequency

allocation or spectrum allocation. Radio propagation does not stop at national

boundaries. Giving technical and economic reasons, governments have sought to

harmonise the allocation of RF bands and their standardisation.

Bandwidth:

Bandwidth is typically measured in hertz, and may sometimes refer to pass

band bandwidth, sometimes to baseband bandwidth, depending on context. Pass

band bandwidth is the difference between the upper and lower cutoff

frequencies of, for example, an electronic filter, a communication channel, or a signal

spectrum. In case of a low pass filter or baseband signal, the bandwidth is equal to

its upper cutoff frequency. The term baseband bandwidth refers to the upper cutoff

frequency. Bandwidth in hertz is a central concept in many fields,


58/86

including electronics, information theory, radio communications, signal processing,

and spectroscopy.

In computer networking and other digital fields, the term bandwidth often

refers to a data rate measured in bits per second, for example network throughput.

The reason is that according to Hartley's law, the digital data rate limit (or channel

capacity) of a physical communication link is related to its bandwidth in hertz,

sometimes denoted frequency bandwidth, analog bandwidth or radio bandwidth.

For bandwidthas a computing term, less ambiguous terms are bit rate, throughput,

maximum, good output or channel capacity.

Analog systems:

For analog signals, which can be mathematically viewed as functions of

time, bandwidth, BW or fis the width, measured in hertz, of the frequency range in

which the signal's Fourier transform is nonzero. Because this range of non-zero

amplitude may be very broad, this definition is often relaxed so that the bandwidth is

defined as the range of frequencies where the signal's Fourier transform has a

power above a certain amplitude threshold, commonly half the maximum value, or

3 dB. The word bandwidth applies to signals as described above, but it could also

apply to systems, for example filters or communication channels. To say that a

system has a certain bandwidth means that the system can process signals of that

bandwidth.

A baseband bandwidth is synonymous to the upper cutoff frequency, i.e. a

specification of only the highest frequency limit of a signal. A non-baseband

bandwidth is a difference between highest and lowest frequencies.

As an example, the (non-baseband) 3-dB bandwidth of the function depicted

in the figure is , whereas other definitions of bandwidth would yield a

different answer.

A commonly used quantity is fractional bandwidth. This is the bandwidth of a

device divided by its center frequency. E.g., a device that has a bandwidth of 2 MHz

with center frequency 10 MHz will have a fractional bandwidth of 2/10, or 20%.

The fact that real baseband systems have both negative and positive

frequencies can lead to confusion about bandwidth, since they are sometimes


59/86

referred to only by the positive half, and one will occasionally see expressions such

as B = 2W, where B is the total bandwidth, and Wis the positive bandwidth. For

instance, this signal would require a low pass filter with cutoff frequency of at

least Wto stay intact.

The 3 dB bandwidth of an electronic filter is the part of the filter's frequency

response that lies within 3 dB of the response at its peak, which is typically at or near

its center frequency.

In signal processing and control theory the bandwidth is the frequency at

which the closed-loop system gain drops 3 dB below peak. In basic electric circuit

theory when studying Band-pass and Band-reject filters the bandwidth represents

the distance between the two points in the frequency domain where the signal

is 1/sqrt(2) of the maximum signal amplitude (half power).

RESISTORS: -

A Resistor is a heat-dissipating element and in the electronic circuits it is

mostly used for either controlling the current in the circuit or developing a voltage

drop across it, which could be utilized for many applications. There are various types

of resistors, which can be classified according to a number of factors depending

upon:

Material used for fabrication

Wattage and physical size

Intended application

Ambient temperature rating

Cost

Basically the resistor can be split in to the following four parts from the constructionview point.

(1) Base

(2) Resistance element

(3) Terminals

(4) Protective means.

The following characteristics are inherent in all resistors and may be

controlled by design considerations and choice of material i.e. Temperature co

efficient of resistance, Voltage coefficient of resistance, high frequency


60/86

characteristics, power rating, tolerance & voltage rating of resistors. Resistors may

be classified as

(1) Fixed

(2) Semi variable

(3) Variable resistor.

CAPACITORS

The fundamental relation for the capacitance between two flat plates

separated by a dielectric material is given by:-

C=0.08854KA/D

Where: -

C= capacitance in pf.

K= dielectric constant

A=Area per plate in square cm.

D=Distance between two plates in cm

Design of capacitor depends on the proper dielectric material with particular

type of application. The dielectric material used for capacitors may be grouped in

various classes like Mica, Glass, air, ceramic, paper, Aluminum, electrolyte etc. The

value of capacitance never remains constant. It changes with temperature,

frequency and aging. The capacitance value marked on the capacitor strictly applies

only at specified temperature and at low frequencies.

LED (Light Emitting Diodes):As its name implies it is a diode, which emits light when forward biased.

Charge carrier recombination takes place when electrons from the N-side cross the

junction and recombine with the holes on the P side. Electrons are in the higher

conduction band on the N side whereas holes are in the lower valence band on the P

side. During recombination, some of the energy is given up in the form of heat and

light. In the case of semiconductor materials like Gallium arsenide (GaAs), Gallium

phoshide (Gap) and Gallium arsenide phoshide (GaAsP) a greater percentage of


61/86

energy is released during recombination and is given out in the form of light. LED

emits no light when junction is reverse biased.

Liquid Crystal Display:

In recent years the LCD is finding widespread use replacing LED's. This is

due to

The declining prices of LCD's.

The ability to display numbers, characters, and graphics. This is in contrast to

LED's which are limited to numbers and a few characters.

Incorporation of a refreshing controller in to the LCD, thereby relieving the

CPU of the task of refreshing the LCD. In contrast, the LED must be refreshed

by the CPU to keep displaying the data.

Ease of programming for characters and graphics.

LCD PIN DESCRITION:

VCC, VSS, VEE:

While Vcc and Vss provide +5V and ground, respectively, Vee is used for

controlling LCD contrast.

RS, register select:

There are two very important registers inside the LCD. The RS pin is used

for their selection as follows. If RS = 0,the instruction command code register is

selected, allowing the user to send a command such as clear display,cursor at

home,etc.If RS=1 the data register is selected ,allowing the user to send data to be

displayed on the LCD.

E, enable:

The enable pin is used by the LCD to latch information presented to its data

pins. When data is supplied to data pins ,a high to low pulse must be applied to this

pin in order for LCD to latch in the data present at the data pins. This pulse must be

a minimum of 450ns wide.


62/86

D0---D7:

The 8--bit data pins ,D0-D7 are used to send information to the LCD or read

the contents of the LCD's internal registers. To display letters and numbers we send

ASCII codes for the letters A - Z, a - z and numbers 0 - 9 to these pins while making

RS = 1.There are also instruction command codes that can be sent to the LCD to

clear the display or force the cursor to the home position or blink the cursor.

We also use RS = 0 to check the busy flag bit to see if LCD is ready to receive

the information. The busy flag is D7 and can be read when R/W = 1 and RS = 0, as

follows, if R/W = 1,RS = 0.When D7 = 1 (busy flag bit=1), the LCD is busy taking

care of internal operations and wil not accept any new inforamtion.

NOTE: It is recommended to check the busy flag before writing any data to the LCD.

Pin Diagram:

HT12E:

Features

_ Operating voltage_ 2.4V~5V for the HT12A

_ 2.4V~12V for the HT12E

_ Low power and high noise immunity CMOS technology

_ Low standby current: 0.1_A (typ.) at VDD=5V

_ HT12A with a 38kHz carrier for infrared transmission medium

_ Minimum transmission word

_ Four words for the HT12E

_ One word for the HT12A


63/86

_ Built-in oscillator needs only 5% resistor

_ Data code has positive polarity

_ Minimal external components

_ Pair with Holtek_s 212 series of decoders

_ 18-pin DIP, 20-pin SOP package

Applications

_ Burglar alarm system

_ Smoke and fire alarm system

_ Garage door controllers

_ Car door controllers

_ Car alarm system

_ Security system

_ Cordless telephones

_ Other remote control systems

Description:

The 212 encoders are a series of CMOS LSIs for remote control system

applications. They are capable of encoding information which consists of N address

bits and 12_N data bits. Each address/data input can be set to one of the two logic

states. The programmed addresses/ data are transmitted together with the header

bits via an RF or an infrared transmission medium upon receipt of a trigger signal.

The capability to select a TE trigger on the HT12E or a DATA trigger on the HT12A

further enhances the application flexibility of the 212 series of encoders. The HT12A

additionally provides a 38kHz carrier for infrared systems.

Selection Table:


64/86

Block Diagram:

Pin Diagram:


65/86

Absolute Maximum Ratings

Supply Voltage (HT12A) ............VSS_0.3V to VSS+5.5V Supply Voltage

(HT12E) ..........................._0.3V to 13V

Input Voltage ................................VSS_0.3 to VDD+0.3V Storage

Temperature ............................_50_C to 125_C

Operating Temperature..........................._20_C to 75_C

Note: These are stress ratings only. Stresses exceeding the range specified under

_Absolute Maximum Ratings_ may cause substantial damage to the device.

Functional operation of this device at other conditions beyond those listed in the

specification is not implied and prolonged exposure to extreme conditions may affect

device reliability.


66/86

Electrical Characteristics:

HT12D:

Features

_ Operating voltage: 2.4V~12V

_ Low power and high no

wire less remote control ing motorrieside scrcu jack system opening &closing system

Documents