winter-spring 2001codesign of embedded systems1 computer-aided co-design methods and tools part of...

Winter-Spring 2001 Codesign of Embedded Syste

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Computer-Aided Co-design Methods and Tools

Part ofHW/SW Codesign of

Embedded Systems Course (CE 40-226)


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Today programme Introduction to HW/SW Codesign

Computer-aided codesign methods and tools


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Motivations System designer goals

Satisfy system-level specifications in a short time

Maximize system value Performance, power consumption,

applicability to various user demands Minimize cost

Number of HW parts, size of silicon die, cost of SW development


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Motivations (cont’d) CAD tools are useful, because

Require formal system-level specification => structured design methodology

Facilitate HW and SW reuse Support analysis and validation tools Facilitate design-space exploration

Overall objective in codesign tool R&D Provide IDE for concurrent specification,

validation, and synthesis of both HW and SW


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Modeling Model of computation vs. HW/SW language

Computation model: Has an underlying mathematical structure: FSM, Petri net

Languages: Some are means of expressing a computation model Some don’t have a formal semantics

Functional modeling of digital systems Normally C or C++, to check generic properties

and derive some measure of performance & cost Too general. Do not capture all necessary

specifications of HW component


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Modeling (cont’d) Some specification models

“FSM or interconnection of FSMs” Model Graphical representation: Statecharts Textual languages: SDL, Esterel

Partial-orders of tasks HW components: Verilog / VHDL Synchronous data-flows: Silage, DFL

A perfect language for system is idealistic Heterogeneity of system components Conflicting interests of CAD developers and users Lack of a formalism to capture well all features


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Validation Validation vs. verification Approaches to validation

Formal verification Simulation (co-simulation) Emulation


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Validation (cont’d) Simulation

cannot ensure correctness, but still useful Heterogeneity

Weakly heterogeneous Lumped, GP computing systems. Simple control

systems Can be simulated by extending HDL simulators

Strongly heteroneous Cellular phones, avionics Require specialized simulation environments


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Validation (cont’d) Simulator features for weakly

heterogeneous systems Adequate timing accuracy Fast execution Visibility of internal registers for debugging

Strategy 1: Use HDL simulator + HDL models for processor and ASICs Long HW simulation time for each

instruction: accuracy vs. speed tradeoff


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Validation (cont’d) Strategy 2: avoid processor HDL

model Use HW/SW comm. Protocol SW is compiled and communicates

with the HDL simulator which models ASIC

HDL simulator is bottle-neck Internal registers not visible


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Validation (cont’d) Strategy 3: Emulate HW on a re-

configurable platform Automatic partitioning tools to

minimize system-simulation time have been developed

Visibility of internal states is limited => probable slow debugging


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Validation (cont’d) Simulation of strongly heterogeneous

and distributed systems Specialized simulators: Ptolemy

Extesible, OO kernel Supports several computation models Models are not implemented in simulation

kernel, but in domains that can interact without knowing their semantics

Some developed domains: data-flow, discrete-event. More domains are user-insertable.


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Synthesis What’s Synthesis/Co-Synthesis System-level Partitioning Hardware synthesis Software synthesis and

retargetable compilation Interface synthesis


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Synthesis (cont’d)

Specification

Detailed Representation of Implementation

Synthesis

HW: HDL (Behavioral, DataFlow,

Structural), Schematic

RTL, Gate level,

Transistors, Layout

SW: Algorithm,Textual/Graphical

representation

Executable or Compilable code: The

program(s), OS routines

Co-Synthesis


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Fabrication Test


Systemdesign

ASIC design

SW design

PCB test

SW test

Time

Tasks

Copyright J. Madsen, some modifications applied

Copyright J. Madsen, some modifications applied

Traditional System Design Process


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Shared Design

Co-Design Process

SW design

ASIC design Fabrication Test

PCB test

SW test

Time

Tasks

Systemdesign

System-Level Partitioning


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Synthesis (cont’d)Some special cases Synthesis of ISPs

HLS techniques are applicable to high-level models of processors

Many high-level decisions are not automatic yet Example: Pipeline organization, Datapath

design Reason:

Few new ISPs compared to ASICs Performance is very sensitive High production-volume recovers high design costs

HLS is, however, used for control functions


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Synthesis (cont’d)Some special cases Design of compilers

Corresponds to the processor architecture Compilers are co-designed with processors

Automated tools for synthesis of pipeline control unit + compiler

Synthesis of lumped embedded systems Natural evolution of HLS Uniform specification + manually or

automatically partitioning into HW+SW+interface


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Synthesis (cont’d)System-Level Partitioning One extreme: Full HW solution

High performance due to Parallelism High cost and long time of ASIC fabrication

Other extreme: Full SW solution High-performance, low-cost processors Operation serialization Lack of support for specific tasks

Best solution is a mix of HW and SW


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Synthesis (cont’d)System-Level Partitioning Major approaches to Partitioning

Co-synthesis of dedicated co-processors for SW execution acceleration

Migration of non-critical functions to SW Complementary objectives

Maximize performance Minimize system cost, subject to required

performance


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Synthesis (cont’d)System-Level Partitioning

Coprocessor approach: COSYMA tool suite

System model in C*

SW implementation of system readily available

Uses CDFG Identifies performance

bottlenecks Migrates bottleneck to

corresponding ASIC Three times faster

execution of an algorithm in HDTV

Migration to SW approach: VULCAN tool suite

System model in HardwareC

System is HW synthesizable using Olympus

Uses CDFG Partitions CDFG into SW

threads and HW circuits Automatically generates

units to interface processor to the ASIC


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Synthesis (cont’d)System-Level Partitioning Problems in Partitioning

Quality of partition depends on performance/cost estimators

Estimators base on abstract system representation (CDFG)

Estimators need to be fast A coarse-grained partition may be of more

interest Module/Unit level partition instead of operation-level

Less degree of freedom Designers’ expertise can be more easily exploited by

allowing macroscopic choices


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Synthesis (cont’d)HW synthesis Mostly based on Graph-theoretic

approaches and algorithms (To be presented as an extra class)


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Synthesis (cont’d)SW synthesis SW Synthesis and Retargetable Compilation

SW synthesis Compilation Maybe preceded by automatic SW generation

steps Compilation specialties in embedded systems

Code is compiled once=> compilation time not important, maximum optimization is desired

RT constraints=>code must be tight and fast => assembly

Embedded systems often use ASIPs=>unordinary architectures=>hard to compilers


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Synthesis (cont’d)SW synthesis Retargetable Compilers

Developing a new compiler for each new ASIP is unreasonable=>retargetable compilers

Classification according to retargeting time Portable compiler Compiler-compiler Machine-independent compiler


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Code-generationback-end

Synthesis (cont’d)SW synthesis Compiler components

Code-generation/optimizationintermediate stage

Source-code-dependantFront-end

instructionselection

registerallocation

instructionscheduling


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Synthesis (cont’d)SW synthesis Other topics in retargetable

compilation Micro-programmed ASIPs

Compacting the micro-program Determine ILP (Instruction-Level Parallelism) Encoding of each word


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Synthesis (cont’d)Interface synthesis Interface Synthesis

Generation of SW routines and/or HW circuits to interface processor and ASIC to a communication channel operating under a given protocol (e.g. PCI, VME)

Several standards available & system-level model should avoid specifying details of comm. mechanism

An approach: model comm. protocol with a language (Promela) and derive C++ routines and gate-level HW out of it


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Synthesis (cont’d)Interface synthesis Interface Synthesis (cont’d)

Specific problems arise from: Partitioning a system into interacting HW and SW

Communication and synchronization Interfacing processors to peripherals (sensors,

actuators) CHINOOK: automatic (processor port allocation,

deciding to implement device drivers in HW or SW) Scheduling the processor communication

Complicated under RT constraints Complicated under data-dependant delays


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Summary

Co-Synthesis

SystemSpecification

Partitioning

HW ParameterEstimation

SW ParameterEstimation

SystemIntegration

Verification

Verification

Verification

Verification

Final Verification

SWSynthesis

HWSynthesis

ASIC OS

EXE Code


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Summary (cont’d) CAD Tools are essential to progress in electrical

system design Design of digital components of systems benefit

from HW/SW Codesign At present, Codesign CAD support is still weak

Co-simulators commercially available Others (co-synthesis, verification, IDEs, etc) growing

up Impact of CAD tools on system-level design will

be more profound than their impact on IC design


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What we learned today CAD tools are essential to success in this field

They must support Modeling (specification), Validation, and Synthesis in a single integrated environment

Major constituents of codesign Modeling (Specification) Validation (Verification) Synthesis (Co-synthesis)

System-level partitioning HW synthesis SW synthesis Interface synthesis


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Complementary notes Postponed Verilog Short Course

Instructor: Farshid Soheili, Emad Semicon. Co.

First session Saturday: Esfand 13th

“CE-202” room, 15 o’clock

Take the first chapter of DeMicheli’s book from “Publications Room”


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Complementary notes (cont’d) Optional paper presentation

Any subtopic from last and today programme:

Computer-Aided Codesign Methods and Tools

Project Today is date to choose and announce

your partner for the final project

winter-spring 2001codesign of embedded systems1 computer-aided co-design methods and tools part of...

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