window annuciator - project report

7/28/2019 Window Annuciator - Project Report

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CONTENTS

1. CHAPTER1: INTRODUCTION

2. CHAPTER2: BLOCKDIAGRAMANDCIRCUITS

3. CHAPTER3: DETAILSOF PCBSUSED

4. CHAPTER4: DETAILSOF ICSUSED

5. CHAPTER5: FLOWDIAGRAM

6. CHAPTER6: CONTROL SOFTWARE

7. CHAPTER7: DETAILSOF MDS FOR8032

8. CHAPTER8: CONCLUSIONS

9. CHAPTER9: BIBLIOGRAPHY

10. ANNEXURE: DATA SHEETS

Project Report: Window annunciator with remote sense


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CHAPTER 1

INTRODUCTION



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INTRODUCTIONTOTHE PROJECT

Generally in an industry there are several stages of productions that need to be

monitored continuously for its proper working. It is impossible for a human operator to keep

watch over such vital parts of production. In case there are several such important points that

need to be monitored, then several operators are to be engaged in this monitoring operation.

This is not a practical solution as the fatigue and carelessness of human operator would lead

to heavy loss. To give an example, a chemical boiler is the main point in the production line

that needed to be monitored. Whenever the chemical in the boiler reaches some critical level,

the heating process should start. When it reaches some critical level of heat, the heater

should be switched off. The temperature of the chemical should never raise beyond a safe

limit. For any reason the initial level is overshot or if the temperature raises beyond safe limit

or if the heater comes on when no chemical is present in this case the chemical enters

hostile environment disaster can occur. The disaster may be a simple wastage of chemical

or as dangerous as boiler exploding causing severe loss.

In industries, several safety precautions are employed to automatically correct the

situation. When a mechanical failure occurs, the human operator is called in to action, as the

complexity of the situation should not be left for the automated process to decide. Here an

arrangement is needed where by the human operator is alerted that something has gone

wrong and his action is called for. The points that need to be monitored may be several

equipments or some parts of the same equipment or a combination of both. So it is advisable

to locate the warning system at centrally located point for the group of persons to act

immediately to avoid damage.



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The equipment that does this type job is named as Annunciator. As it is going to be

centrally located where a team of trained personal waits for the fault condition to occur. They

will immediately swing into action to prevent loss of life and material. So the annunciator

should have the facility to draw their attention to the fault by sounding an alarm. Their

attention will be drawn to the warning system or Annunciator. But how will the operator

know which of the several possible points require attention when a fault condition is

generated? For this reason a window is provided for every point or equipment under

observation on this annunciator. A window here means a rectangle arrangement with some

text written on a photographic film kept at the front. The window has a set of lamps inside it.

The lamps are normally 110 V filament lamps as industry draws its power for the equipment

from the most commonly used voltage source. When the lamp is off, the text on the film is

not readable. When the lamp lights up, the text on the film is illuminated and becomes

visible to the operator.

The term Window Annunciator derives its name from the fact that the central trouble

managing system has several illuminated windows dedicated for each equipment or points of

some equipment under observation where faults can occur and it needs attention of an

operator. When the error or fault conditions are received from a particular machine or point,

the corresponding window lights up and blinks to get the attention of the operator. At the

same time a powerful hooter also starts and this will get the attention of all those present in

that room. When they look at the annunciator, they can find the window dedicated to an

equipment or point of production which has developed fault.

The lamps inside the windows are normally off. When a fault condition occurs in the

equipment related to that window, then the lamp inside the window flashes and the

associated message is displayed and an alarm is sounded. Now the operator is alerted. But



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the alarm need not be on as the operator has taken notice of the situation. The human

operator acknowledges this situation by pressing a switch labeled as ACKNOWLEDGE.

The annunciator knows that somebody has taken note of the situation as Acknowledge

button marked ACK has been pressed. Now the lamp in the window glows steadily and the

alarm is switched off. The lamp inside the window continues to glow indicating that the fault

condition persists, but it is being attended to. So if some other person looks at the

annunciator, he knows that the fault has been noticed and some body is attending to the

situation.

The operator now rectifies the fault and the annunciator should be informed of this

fact. Pressing a switch marked RESET informs annunciator that the situation has been

rectified and the annunciator can resume its normal operation. When the RESET switch is

activated, the window associated with the faulty machine returns to normal. The same

window resumes its monitoring activity and remains alert.

Now let us analyse the situations to find what are the variations that can be

introduced in this monitoring equipment Window Annunciator. At present, the window

annunciator that is available in the market has basic features only available. They are,

1. The operator can set the equipment condition as NC or NO. This means that the

equipment is perceived as faulty if it ON (NO) or OFF (NC).

2. The rate of alarm is fixed. Whatever the fault, the audio alarm sounds in the same

way. There is no way one fault is differentiated from other faults.

3. A pair of wire is run from the equipment or point to the annunciator. The points are to

be potential free that is they should not source or sink any current.



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4. When a fault condition is observed and the audio alarm is started, the alarm remains

on even if the fault condition disappears on its own. The operator Acknowledges

the fault condition goes to the equipment to find the same has rectified itself.

Possible waste of time.

In the proposed design, the point 1 is same as in the conventional window

annunciator. For point 2, the micro controller dedicated a bit for indicating the type of

response that should be generated. The audio alarm can be a high frequency warning or a

low frequency warning. This way the operator knows the fault is a dangerous one (High

frequency alert) or not so dangerous fault (low frequency alert. The micro controller

examines this bit associated with a window, when it sees a fault condition for that window.

The clock frequency for audio alert is set accordingly.

The point 3 is taken care by using a wireless method to convey the message that a

fault has been observed at a particular point or equipment. Replacing the wires with a pair of

FM Transmitter and receivers for each window, the wireless communication is achieved

between the window and the equipment under observation. The present technique used here

is suitable for about 20 windows. When more windows are needed, then the Blutooth

technology that is emerging in the filed of wireless communication can be used. At present

Blutooth ICs are not freely available, but it is only a matter of time for such ready-to-use

Blutooth ICs are available. The number of windows can easily be increased to 255 and more

and the frequency used is also in UHF range of 2.46 GHz. In this design, the ready-to-use

FM transmitter-receiver pair operating in the frequency range of 88 MHz to 108 MHz is

used.



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To attend to point 4, another bit is associated to a window, which is read by the micro

controller when it sees a fault condition of equipment. The micro controller keeps on looking

at the equipment, which is under fault condition. This is called Pooling Method. It first

checks the condition of equipment associated to window 1. If a fault condition is observed

here, it initiates appropriate action for that window. The micro controller then moves on to

check input for window 2, then window 3, then window 4 and it starts all over again by

checking window 1 and so on. Let us look at situation where the micro controller has seen

fault condition on window 1 and set the audio alarm of fast or slow rate (depending on the

condition of the bit associated with that window). It moves on to check other 3 windows.

Next time when it comes to window 1 and if the fault condition still persists, it looks for the

acknowledge button. If it is not yet pressed, it continues to check other windows.

When the acknowledge button is pressed:

When the acknowledge button is pressed, then the micro controller stops the audio

alarm and stops the clock going to the window. The lamp in the window glows steady. This

will enable others to know that a fault has occurred and some one has pressed acknowledged

it by pressing acknowledge button. The window that glows steady indicates which

equipment has developed fault.

When the acknowledge button is NOT pressed, but the fault condition is removed:

This is a tricky situation as micro controller sees that the fault is removed, but the

human operator is not aware that a fault has occurred in the first place. Here again a separate

bit is dedicated associated to that window. If this bit is set, then the micro controller can reset

the window as if acknowledge and reset key are pressed. If this bit is reset, micro controller



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has to wait for a response from the human operator, no matter what is the present condition

of the equipment under observation.

It can be seen that Microcontroller dedicates 4 bits for each equipment under

observation. One bit is its actual condition. This bit is set, if the equipment is OFF and reset

when the equipment is ON. The second bit is to tell the processor what is the fault condition

associated with that equipment if the equipment is ON, it is fault condition or vice versa.

The third bit will indicate a fast clock or slow clock is to be injected to window and audio

alarm when a fault condition for the window is observed. The fourth bit tells the processor

what action it should take when the fault disappears on its own before it is acknowledged.

A `TEST switch is included to periodically check the condition of lamps inside the

window, buzzer alarm and the working of the fast and slow clock and the setting of each

window. This is extremely important. Incase the alarm has failed or the lamps have fused out

or the clock has failed, the human operator may not be alerted and the disasters will be very

high. This TEST button helps the operator to periodically check the conditions of various

parts of the annunciator. When this switch is pressed, the micro controller assumes fault

conditions on all channels and initiates audio alarm, blinks the windows and waits for

acknowledge key press. After the acknowledge key, it expects RESET key is to be pressed.

This way the operator ensures that all systems are okay and as and when a fault condition is

observed, it will alert the human operator properly.

As this project suggests wireless communication between the equipment under

observation and the window annunciator, the medium of transmission should take care noise

and other problems associated with wireless communication. The proposed idea should

ensure that there is no false trigger or a trigger message is missed. The equipment under



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observation will have a FM transmitter whose frequency of transmission is different from

others. There are as many receivers at the window annunciator to receive the signal from the

equipment under observation. All receivers have a common antenna. When the frequency of

transmitter and receiver matches, it gives an output. To ensure that there is no adjacent

channel false trigger, the transmitter sends out a audio tone. The receiver output is fed to a

PLL Phase Locked Loop. If both frequency match only then a signal is issued. This way it

is ensured that the right equipment triggers right bit in the window annunciator. There after,

the procedure described above takes over.

The window annunciator keeps checking the inputs by rotation. As the crystal used is

12 MHz, it takes only 10 S to respond when a fault occurs.



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CHAPTER2:

BLOCKDIAGRAM

AND

CIRCUITS



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WINDOW ANNUNCIATOR BLOCK Diagram


LOAD 1UNDERCHECK

LOAD 2UNDERCHECK

LOAD 3UNDERCHECK

LOAD 4UNDERCHECK

RECEIVER

P LL &status forLOAD 1

PLL &Status forLOAD 2



C (8032) & Its peripheral ICs

SlowClock

Fast

Clock

Alar

Windowfor Load1 withMessage




Ack

ResetTest


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Working Principle:

1. The C initialises required memory location, switches off all windows and starts the

monitoring cycle.

2. The load 1 condition is checked for ON/OFF. The corresponding type bit is now

checked. If both ON/OFF bit and type bit are of same level (i.e. both are high or both are

low), then it is NOT an error condition. The next load condition is checked.

3. If an error condition is detected, then the error type bit is checked to see if it is a

dangerous error or tolerable error. If dangerous error, the fast clock is switched ON. If it

is tolerable error, then slow clock is switched ON. The corresponding window is

activated and the Buzzer is also started.

4. The error window will be on till the acknowledge key is pressed. Once the acknowledge

key is pressed, the window glows steady, till RESET is applied. During the error

condition, if the error is rectified, then the latch bit is checked. This bit tells the processor

to reset the window or not. If this bit is set, then this window will not be checked in

future till a reset is applied. If this bit is low, then the window will reset as soon as the

error condition for a particular window is removed.

5. The process is repeated for all windows.

6. When one window has reported an error of low type and an error in another window with

error of dangerous type occurs, the alarm will be fast over riding the tolerable error.



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02

04

05

06

07

08

09

20

14

13

12

10

01

11 19

18

1703

16

15

20

11

02

03

04

05

06

07

08

09

19

18

17

16

13

12

01

10

15

14

20

02

03

04

05

06

07

08

09

18

17

16

15

14

13

12

11

10

01

19

02

03

04

06

07

08

09

20

05

18

17

16

15

14

13

12

11

10

01

19

74LS245

74LS245

74LS573

74LS573

p3.4

p3.5

p3.3

p1.7

p1.6

p1.5

p3.2

p1.0

p1.1p1.2

p1.4

p1.3

Signal IN

Nc/No

Trip/Pool

Slow/Fast

9 pin sip resistor - 2 k

All Channels are identical.The bar on top indicatesthe type when input is low

+5

Window ON/OFF

Fast/Slow Clock

C h a n n e l 3

C h a n n e l 4

C h a n n e l 2

C h a n n e l 1

Acknowledge

Reset

Test


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On/Off

Slow/Fast

Window

Lamp 1

Control for window1

1K

BC558

5 5 5 5 5 5

4 S e t s o f c o n t r o l c i r c u i t s a r e r e p e a t e d - o n e e a c h f o r a w i n d o w

1K

1N4148 x 2

7 4 0 03

4

12

1311

8

10921

65

100K

100K

0.1 F

330K

330K

0.1 F

Fast

Clk

Slow

Clk

2

6

47

8

3

1

4 8

2

7

16

3

0.1F

F MR x

5K PRESET

1F 0.01 F

+ 1

+

5

10K

+5

4

2

12

67

8

4 3

5

0.01

F

N E

5 6 7

P L L

M C T

2 E

LED

220E 6K8

LED 220E

To 74LS245 as Window Input

Osc Tx

+5V supply

On/Off control

T r a n s m i t t e r U n i t a t t h e m o n i t o r i n g P o i n t

R e c e i v e r f o r o n e w i n d o w i s s h o w n h e r e . T h r e e m o r e u n i t s a r e r e p e a t e d


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CHAPTER3:

DETAILSOF PCBSUSED



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Description of Boards

usedMICRO CONTROLLER BOARD

The C board, which acts as a mother board by excising control over all other boards,

Consists of a C Chip 80C31, an 8 bit latch and an EPROM. It is connected to other boards

through a 20-pin FRC (Flat Ribbon Cable) connector, which carries the 8 bits of PORT-1

and 8 chip-selects from Port 3. Also this board has the four Port 3 bits of INT0, INT1 and T0

and T1 brought out separately through a 6 pin rely mate connector for future use. The C

80C31 is a 40 Pin Chip, which works on + 5V DC supply and has a 12 MHz crystal

connected as clock source. It has four 8-bit Ports, named Port 0 through Port 3. The reset pin

is connected to ground through a 47K resistor and a 0.1 F/Tantalum capacitor is connected

between reset pin and positive supply. A push switch is connected across this capacitor to

apply reset manually when ever required. The supply to this board is through a 3 pin rely

mate connector. It connects the micro controller board with power supply. The power supply

will supply 5 V DC @ 1.0 amps and 12 V DC @ 200 mA. An LED on the micro controller

board indicated that the power is applied to the board.

The Port 0 is used as multiplexed Address-Data lines AD0 to AD7, as in 8085 and

the PORT-2 will be used by the C to emit higher order address bits - A8 to A15. These two

ports would have been available to us if we elected to use 89C51 (From ATMEL, USA) or

87C51 or 80C51 (From Intel USA). But the Micro controller development system that we

have used supported only 80C31 and we have decided to stick to the same C in our project

design for the sake of simplicity. A 27C64 is used, which is an 8K byte EPROM, to store and



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generate the required sequence of hex byte command and data for the C. This is the least

capacity EPROM presently available in the market.

Using an 8 bit latch 74HC573, along with ALE of 80C32 like in 8085 systems, the

address and data lines are separated and latched. As explained in earlier chapters, the Port 3

bits of 80C32 have additional usage or alternate uses. The ICE for 80C32 that we have used

has given us the control over entire port 1 bits and port 3 bits. The Emulator was driven by a

serial communication port (RS 232) of the PC. It was very easy for us to connect the

emulator to the Microcontroller board as there was no need to effect any change.

Had we not used ICE for 80C32, we would have to have to try the control software in

the simulator and having perfected to the extend possible, the same should have been burned

into an EPROM. If the circuit works after power up, then every thing is OK. Generally the

electronics circuit does not work on the first try and the emulator had given us a chance to

run the programme under our control. The emulator uses an 8 K RAM for downloading the

programme from the computer and configures this RAM as EPROM and connects it to the

micro controller inside for real time emulation. The additional control circuitry takes the

command on the computer keyboard and controls the way the micro controller works. This

micro controller board has a 20 pin connector on its side. The other boards that need to be

connected will also have an identical 20 pin connector, so that the data and control lines

along with supply lines may be interconnected between boards. This type of arrangement is

easy to implement and messy interconnecting wiring of individual points are avoided.

The reset switch is brought out on the panel board for applying manual reset by the

user. The housing in which the project is enclosed will have an LED on the panel to indicate

the status of power to the micro controller board.



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INPUT/OUTPUT BOARD

As explained earlier in this chapter, the micro-controller board can only support 16

lines in the test target board for interfacing the controller with other devices. As we need

several 8-bit ports to realize the required functions for our project, we are forced to find a

solution for this problem. One solution is to connect an 8255 PPA with two 8-bit ports and

two 4-bit ports. The 8255 IC draws considerable amount of power. We have decided to use

8-bit latches and transceivers in the place of 8255 to realise the required port implement.

We have chosen 74LS573, an 8-bit latch to be used as an output port. This IC has its

pin 1 grounded to make the chip always selectable. The chip enable pin 11 will be used to

latch on to the new data as and we require. This IC suits our requirement for output port. For

realizing an input port, we have chosen 74LS245, an 8-bit transparent bus transceiver. This

IC has the capacity to transmit or receive the signals in 8-bit groups. This means that the

direction of data flow can be controlled. It can transmit or receive data. That is why this IC is

classified as Transceiver (Combination of TRANSmitter reCEIVER. We have grounded its

direction pin (Pin 1) to make it only receive the signals. This way we use this IC as an input

buffer. The advantage in using such an arrangement is that the ports need not be initialised

and only setting or clearing the corresponding bit in port 3, which acts as CS for the port

under use, we can operate the appropriate ports. Consequently the power consumed by this

arrangement is far below the 40 pins IC 8255. Additionally, there is no reset or clock

required as in 8255 for synchronising. The hand shaking capabilities of 8255 is missing in

this simple-to-implement port buffers. As our requirement for this particular project is

minimum resources requirement, we really do not the sophistications of 8255.



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For both the ICs (74LS245 and 74LS573), the Data input pins are pin 2 to pin 9,

which are multiplexed that is pin2 of all buffers are connected together, pin3 off all buffers

are connected together and so on. The multiplexed lines are terminated in the 20-pin FRC

connector. The connection on 20 Pin FRC on this Input/Output board is identical to the

connections on 20 Pin FRC connector on the micro controller board. When the two boards

are inter connected by a 20 pin FRC, the pins of 80C32 and the input pins of the buffers are

connected. This connection will ensure that pin1 of 80C32 will connect to pin2 of all buffers

(D0). Similarly pin2 of 80C32 will connect to common pin3 of buffers as D1. Similarly pin3

to pin 8 of 80C32 will connect to Pin4 to pin 9 of buffers. The chip selects of all the buffers

are yet to be connected. The appropriate bits of port 3 from 80C32 will be used as chip

select.

This board houses four devices, two each of 74LS245 and 74LS573. This

arrangement will enable us to connect two such boards in parallel by choosing different Port

3 pins for chip select. The input side of the 74LS245 (Pin 18 to Pin 11) has a SIP resistor of

10K pull-up (The pins are pulled up by default to read a high, when there is no signal

present). The output latches and the input of the transceiver are terminated in a 10 pin rely

mate connector each for external connection. This board also has an LED indicator to give

the visual indication of power being connected to this board.

The 10 pin connector on the buffer has the 8 bit data and supply lines. This will

ensure that the devices connected to the buffers are properly powered up.



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INTERFACE BOARD for INPUT & OUTPUT operations

The micro-controller board along with port ICs for INPUT and OUTPUT operations

needs to get their data from this board. This board supplies following data regarding the

status of equipment under observation.

1. The present Status of the equipment is it ON or OFF

2. The type of equipment error if ON or OFF. (The two messages together taken to

decide if an error has occurred or not for example, if the equipment is expected to

be generally in OFF condition and we find that it is OFF condition, then there is NO

error)

3. The error type dangerous or tolerable this is used for auto resetting. That is, if the

error rectifies itself before the operator presses acknowledge button, should it switch

off the warning or not. If it dangerous, then once the error occurs the warning will be

given continuously till the operator acknowledges.

4. The type of warning slow or fast alarm pulses to be injected into warning system

The receiver section of this board will have 4 FM receivers that will be receiving

signals from the equipment under observation, if the equipment is ON, then a signal from

that equipment is received. This signal will have an audio tone modulated into it. The PLL

Decoder associated with that receiver should get a corresponding tone. Only then the

condition of the equipment will be ascertained. This sort of double check the frequency of

the transmitter and receiver should match and the tone generated by the equipment and sent

via the transmitter should match with the frequency of the decoder. This is called the double

check. Once we get the signal that the equipment is ON, it is sure that there is no ambiguity

about false signalling. The other details listed in item 2 to 4 are actually jumper settings.



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The jumpers to indicate item 2 to 4 will give a high or low status to the processor

whenever it reads them. It is fixed as follows. The jumper for item 2 if it is high it means

the equipment is expected to be OFF normally. If this bit is low, then the equipment is

expected to be ON always. When the status of the equipment as seen by the window

annunciator is otherwise, then it is perceived as a fault or error condition.

When the error condition is detected then the bit 4 is read. If this bit is set that it is

high then the slow clock is activated and this slow clock is sent to the audio beeper and

also to the window. Next time when the processor reads this equipment condition, it will see

that the fault condition has already been activated. So the processor will first look for

acknowledge button to be pressed. When the processor checks that the error condition is

NOT yet acknowledged, but the error or fault condition does not exist, the processor reads

the 3rd bit. If this bit is set that is high, then the processor can reset the condition, without

waiting for the human operator. If this bit is reset that is, LOW then the human response

only will reset the condition for that window.

This repeated pooling of the condition of window ensures that the fault condition is

detected within 50 S. The processor checks 4 bits associated with each equipment, as

detailed in the above 4 steps. The proposed project would cater to 4 equipments and hence

requires 4 x 4 bits or 16 bits. Two input ports built around 74LS245 is used for interfacing

this detail to micro controller. The output ports built around 74LS573 is used to drive the

buzzer, window lamps etc and the associated circuit is also located in this board.

When a fault condition is identified and the type of clock is decided, the processor

will activate that particular clock. It now switches the window on and also connects the audio

alarm to the clock output. The processor requires 2 bit for each window. The first bit is used



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to switch on the window. When this bit is on, the associated window lamp glows. When the

second bit associated with the same window is low, the fast clock is activated. This makes

the window lamp flash at fast rate. This also ensures that the audio beeper beeps at a faster

rate. When the acknowledge button is pressed by the human operator, the clock fast or

slow is switched off. This ensures that window lamp glows steady. The audio beeper stops.

The processor now waits for reset button to be pressed. When this button is pressed, the

window lamp is switched off. The normal routine check for fault on this equipment is

resumed.

When the TEST button is activated, the processor assumes fault on all windows and

activates the clock accordingly. All windows now flash. This ensures that the window lamps

and Beeper are in working condition. When acknowledge button is pressed, all windows now

glow steady. This ensures that the Acknowledge button is in working condition. When

RESET button is pressed, all window lamps go OFF. This ensures that the RESET switch is

in working condition. This TEST button is activated periodically to ensure that all elements

of this warning system are in working condition and as and when fault condition is detected,

there will not a failure of this equipment to alert the human operator.

POWER SUPPLY BOARD

The DC power for the entire equipment is supplied by a linear Power supply built

around a Transformer of 0 10 V AC, secondary at 1 Amp capacity. A bridge rectifier

formed by four power diodes 1N4007 converts the AC into fluctuating DC. The filtering of

this pulsating DC is done by the capacitor of 2200 F/25 V DC. A 3-pin regulator IC 7805,

with suitable heat sink is connected to the output of the bridge-filter capacitor. The resultant



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5 V DC is supplied to the C board and through 20-pin FRC connector to other boards. The

unregulated DC is used to power any device that needs 12 V for its operation.

THE TRANSMITTERBOARD

The equipment under observation will have a potential free contact associated with its

working condition. Potential free condition means the contact will not source or sink any

electrical potential. It may a relay contact. The equipment may be generally ON and the

contacts will be in closed condition. As and when this contact opens, the fault condition is

generated. In some equipment, the equipment may normally be OFF and when the fault

occurs, it comes ON. In such conditions, the contacts will normally be open and when they

close, the fault condition is generated. In reality different parts of the same equipment may

be under observation. For example a chemical tank is under observation. The lower limit and

upper limit are being monitored. The probe for the lower limit is always immersed and the

associated relay will always be on. The upper limit probe should not be on and the associated

relay will always be off. When the lower limit relay open an error condition is generated.

In the way, if the relay associated with upper limit closes, the fault condition is generated.

For each equipment or points to be monitored, a transmitter with an audio oscillator

is associated. As long as the relay is ON, the transmitter is also ON and the window

annunciator receives this FM carrier wave and also the audio frequency modulated. The

audio oscillator is built around the Timer IC 555 in free running mode. The audio range

frequency generated is fed to the FM transmitter. The power for the entire circuit is given

through the relay contact. When the relay is ON, power for this circuit is supplied and the



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transmission is done. In the actual circuit a switch is provided as there is no equipment is

monitored. The switch is used to send or stop the transmission.



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CHAPTER4:

DETAILSOF ICSUSED



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ICS USED INTHE PROJECT

INTEL 80C31 - C

The heart of any project is the brain or the C which combines the functions of

P and an I/O process. In this project the central command is INTELs industrial standard

C 80C31. This is an 8 bit controller, that is it communicates internally as well as externally

through an 8 bit data bus. There are several variations to this family of controllers and this

particular controller is chosen because the controller does not have internal ROM. The

control programme should be stored in an external ROM or EPROM. It is easy to

programme conventional EPROMs in comparison to special devices needed forprogramming 87C51 or 89C51, which can have up to 4K of internal programme memory.

This consideration is the main reason for choosing this particular micro controller. Another

reason is the availability of In-Circuit-Emulator or ICE for 8032. The ICE for 8032 is a

versatile tool that would make developing control software for 8032 an easy task. The

working of the ICE for 8032 is explained in detail in the MDS for 8032 chapter of this

report.

This 40 pin IC comes in different flavours and the generic type number is 80C31. In this

version, the ports P0 and P2 of the micro controller are NOT available for the designer.

These ports will serve as multiplexed Address-Data BUS, AD0-AD7 (Port 0) and Address

Bus A8 to A15 (port 2). Using an octal latch, the DATA and ADDRESS bus can be

separated, like in 80C85 circuits. The Other two ports are used to expand the usable port to 8

numbers of 8 bit ports. This is done by using 74LS245 8-bit transceiver as an input buffer

and 74LS573 8-bit latch as an output buffer. The port 1 (P1) is used as 8-bit data bus to

send and receive information to output buffer or to read 8-bit data from input buffer. Port 3

(P3) is used as chip select and up to 8 such devices in any combination of input and output

can be used. The provision is made for 8 input/output buffers.

The capacity of this processor to address individual bit locations made it a very

versatile IC. For this reason this IC is also called as Boolean Processor or Bit processor.

Several instruction to handle bit related process makes it a unique processor. The final

control programme becomes very compact and it can be executed very efficiently. The two-

byte instruction in the traditional three bytes instructions of 80C85 makes the resultant



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EPROM memory extremely small. Using page concepts and defining 3 types of jumps, the

designer of this processor had given high speed processing capabilities. The speed with

which the instructions are executed can be compared with conventional processor. In the

coming pages, an attempt to explain some of the salient features of this IC has been made,

which is the favourite of the Electronic Industry.

Another reason for choosing this C is the availability of resources for developing

control programmes. The computer screen based simulator downloaded from the Internet,

the in-circuit-emulator for 80C31 controller, several data sheets, assemblers etc, made us use

this IC for this project. The details are given in the following pages on the salient points that

are markedly different from the popular P IC 80C85.

We start the discussion about this controller, with the type of memory it offers to the

designers and explain the SFRs and BIT manipulation techniques. In order to keep the

explanation short, we have not explained the full working of this IC. It has several features

that makes it the industry standards, but as explained we limit it to the required features for

carrying out this project.

TYPESOF MEMORY

The 8051 has three very general types of memory. To effectively program the 8051 it is

necessary to have a basic understanding of these memory types.

The memory types are illustrated in the following graphic.

They are: On-Chip Memory, External Code Memory, and

External RAM.

On-Chip Memory refers to any memory (Code, RAM, or

other) that physically exists on the microcontroller itself. On-

chip memory can be of several types, but we'll get into that

shortly.

External Code Memory is code (or program) memory that resides off-chip. This is often in

the form of an external EPROM.



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External RAM is RAM memory that resides off-chip. This is often in the form of standard

static RAM or flash RAM.

Code Memory

Code memory is the memory that holds the actual 8051 program that is to be run. This

memory is limited to 64K and comes in many shapes and sizes: Code memory may be found

on-chip, either burned into the microcontroller as ROM or EPROM. Code may also be stored

completely off-chip in an external EPROM. That is, it is possible to have 4K of code memory

on-chip and 64k of code memory off-chip in an EPROM.

However, code memory is most commonly implemented as off-chip EPROM. This is

especially true in low-cost development systems and in systems developed by students.

External RAM

As an obvious opposite ofInternal RAM, the 8051 also supports what is called External

RAM.

As the name suggests, External RAM is any random access memory, which is found off-

chip. Since the memory is off-chip it is not as flexible in terms of accessing, and is also

slower. For example, to increment an Internal RAM location by 1 requires only 1 instruction

and 1 instruction cycle. To increment a 1-byte value stored in External RAM requires 4

instructions and 7 instruction cycles. In this case, external memory is 7 times slower!

On-Chip Memory

8051 includes a certain amount of on-chip memory. On-chip memory is really one of two

types: Internal RAM and Special Function Register (SFR) memory. The layout of the 8051's

internal memory is presented in the following memory map:

As is illustrated in this map, the 8051 has a bank of 128 bytes ofInternal RAM. This Internal

RAM is found on-chip on the 8051 so it is the fastest RAM available, and it is also the most

flexible in terms of reading, writing, and modifying its contents. Internal RAM is volatile,

so when the 8051 is reset, this memory is cleared.



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The 128 bytes of internal ram is

subdivided as shown on the memory

map. The first 8 bytes (00h - 07h)

are "register bank 0". By

manipulating certain SFRs, a

program may choose to use register

banks 1, 2, or 3. These alternative

register banks are located in internal

RAM in addresses 08h through 1Fh.

Bit Memory also lives and is part of

internal RAM. The bit addressable

memory resides in internal RAM,

from addresses 20h through 2Fh.

The 80 bytes remaining of Internal

RAM, from addresses 30h through 7Fh, may be used by user variables that need to be

accessed frequently or at high-speed. This area is also utilized by the Microcontroller as a

storage area for the operating stack. This fact severely limits the 8051s stack since, as

illustrated in the memory map, the area reserved for the stack is only 80 bytes--and usually it

is less since these 80 bytes has to be shared between the stack and user variables.

Register Banks

The 8051 uses 8 "R" registers which are used in many of its instructions. These "R" registers

are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7). These registers are

generally used to assist in manipulating values and moving data from one memory location

to another. For example, to add the value of R4 to the Accumulator, we would execute the

following instruction:

ADD A, R4

Thus if the Accumulator (A) contained the value 6 and R4 contained the value 3, the

Accumulator would contain the value 9 after this instruction was executed.



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However, as the memory map shows, the "R" Register R4 is really part of Internal RAM.

Specifically, R4 is address 04h. This can be see in the bright green section of the memory

map. Thus the above instruction accomplishes the same thing as the following operation:

ADD A, 04h

This instruction adds the value found in Internal RAM address 04h to the value of the

Accumulator, leaving the result in the Accumulator. Since R4 is really Internal RAM 04h,

the above instruction effectively accomplished the same thing.

But watch out! As the memory map shows, the 8051 has four distinct register banks. When

the 8051 is first booted up, register bank 0 (addresses 00h through 07h) is used by default.However, your program may instruct the 8051 to use one of the alternate register banks; i.e.,

register banks 1, 2, or 3. In this case, R4 will no longer be the same as Internal RAM address

04h. For example, if your program instructs the 8051 to use register bank 3, "R" register R4

will now be synonymous with Internal RAM address 1Ch.

The concept of register banks adds a great level of flexibility to the 8051, especially when

dealing with interrupts (we'll talk about interrupts later). However, always remember that the

register banks really reside in the first 32 bytes of Internal RAM.

Bit Memory

The 8051, being a communications-oriented microcontroller, gives the user the ability to

access a number ofbit variables. These variables may be either 1 or 0.

There are 128 bit variables available to the user, numbered 00h through 7Fh. The user may

make use of these variables with commands such as SETB and CLR. For example, to set bit

number 24 (hex) to 1 you would execute the instruction:

SETB 24h

It is important to note that Bit Memory is really a part of Internal RAM. In fact, the 128 bit

variables occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if you write the

value FFh to Internal RAM address 20h youve effectively set bits 00h through 07h. That is

that:



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MOV 20h, #0FFh => SETB 00h, SETB 01h, SETB 02h, SETB 03h, SETB 04h,

SETB 05h, SETB 06h, SETB 07h

As illustrated above, bit memory isnt really a new type of memory. Its really just a subset

of Internal RAM. But since the 8051 provides special instructions to access these 16 bytes of

memory on a bit by bit basis it is useful to think of it as a separate type of memory. However,

always keep in mind that it is just a subset of Internal RAM--and that operations performed

on Internal RAM can change the values of the bit variables.

Bit variables 00h through 7Fh are for user-defined functions in their programs. However, bit

variables 80h and above are actually used to access certain SFRs on a bit-by-bit basis. Forexample, if output lines P0.0 through P0.7 are all clear (0) and you want to turn on the P0.0

output line you may either execute:

MOV P0, #01h (or) SETB 80h

Both these instructions accomplish the same thing. However, using the SETB command will

turn on the P0.0 line without affecting the status of any of the other P0 output lines. The

MOV command effectively turns off all the other output lines, which, in some cases, may not

be acceptable. The Best way is to make the full use of the processor its bit handling

capacity. 80C32 family of processors are called as Boolean processors and the bit handling

commands will be used straight away, rather than masking technique used in byte oriented

processor like 80C85

SFRs

The 8051 is a flexible Microcontroller with a relatively large number of modes of operations.

Your program may inspect and/or change the operating mode of the 8051 by manipulating

the values of the 8051's Special Function Registers (SFRs). SFRs are accessed as if they

were normal Internal RAM. The only difference is that Internal RAM is from address 00h

through 7Fh whereas SFR registers exist in the address range of 80h through FFh.

Each SFR has an address (80h through FFh) and a name. The following chart provides a

graphical presentation of the 8051's SFRs, their names, and their address.



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Although the address range of 80h through FFh offers 128 possible addresses, there are only

21 SFRs in a standard 8051. All other addresses in the SFR range (80h through FFh) are

considered invalid. Writing to or reading from these registers may produce undefined values

or behaviour.

SFR Descriptions

P0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit of this

SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0 is pin

P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the

corresponding I/O pin whereas a value of 0 will bring it to a low level.

PCON (Power Control, Addresses 87h): The Power Control SFR is used to control the

8051's power control modes. Certain operation modes of the 8051 allow the 8051 to go into a

type of "sleep" mode, which requires much, less power. These modes of operation are

controlled through PCON. Additionally, one of the bits in PCON is used to double the

effective baud rate of the 8051's serial port.

TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFR is used

to configure and modify the way in which the 8051's two timers operate. This SFR controls



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whether each of the two timers is running or stopped and contains a flag to indicate that each

timer has overflowed. Additionally, some non-timer related bits are located in the TCON

SFR. These bits are used to configure the way in which the external interrupts are activated

and also contain the external interrupt flags, which are set when an external interrupt has

occurred.

TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configure the

mode of operation of each of the two timers. Using this SFR your program may configure

each timer to be a 16-bit timer, an 8-bit auto reload timer, a 13-bit timer, or two separate

timers. Additionally, you may configure the timers to only count when an external pin is

activated or to count "events" that are indicated on an external pin.

TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Bh): These two SFRs, together, represent

timer0. Their exact behaviour depends on how the timer is configured in the TMOD SFR;

however, these timers always count up. What is configurable is how and when they

increment in value.

TL1/TH1 (Timer 1 Low/High, Addresses 8Ch/8Dh): These two SFRs, together, represent

timer1. Their exact behaviour depends on how the timer is configured in the TMOD SFR;

however, these timers always count up. What is configurable is how and when they

increment in value.

P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this




SCON (Serial Control, Addresses 98h, Bit-Addressable): The Serial Control SFR is used

to configure the behaviour of the 8051's on-board serial port. This SFR controls the baud rate

of the serial port, whether the serial port is activated to receive data, and also contains flags

that are set when a byte is successfully sent or received.

SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and receive

data via the on-board serial port. Any value written to SBUF will be sent out the serial port's

TXD pin. Likewise, any value, which the 8051 receives via the serial ports RXD pin, will be



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delivered to the user program via SBUF. In other words, SBUF serves as the output port

when written to and as an input port when read from.

P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this




IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable and

disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific

interrupts, where as the highest bit is used to enable or disable ALL interrupts. Thus, if the

high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt isenabled by setting a lower bit. The required interrupts bits are set for being processed or

ignored if reset.

P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3. Each bit of this




IP (Interrupt Priority, Addresses B8h, Bit-Addressable): The Interrupt Priority SFR is

used to specify the relative priority of each interrupt. On the 8051, an interrupt may either be

of low (0) priority or high (1) priority. An interrupt may only interrupt interrupts of lower

priority. For example, if we configure the 8051 so that all interrupts are of low priority

except the serial interrupt, the serial interrupt will always be able to interrupt the system,

even if another interrupt is currently executing. However, if a serial interrupt is executing no

other interrupt will be able to interrupt the serial interrupt routine since the serial interruptroutine has the highest priority.

PSW (Program Status Word, Addresses D0h, Bit-Addressable): The Program Status

Word is used to store a number of important bits that are set and cleared by 8051

instructions. The PSW SFR contains the carry flag, the auxiliary carry flag, the overflow

flag, and the parity flag. Additionally, the PSW register contains the register bank select

flags which are used to select which of the "R" register banks are currently selected.

The Accumulator



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The Accumulator, as its name suggests, is used as a general register to accumulate the

results of a large number of instructions. It can hold an 8-bit (1-byte) value and is the most

versatile register the 8051 has due to the shear number of instructions that make use of the

accumulator. More than half of the 8051s 255 instructions manipulate or use the

accumulator in some way.

The "R" registers

The "R" registers are a set of eight registers that are named R0, R1, etc. up to and including

R7. These registers are used as auxiliary registers in many operations. To continue with the

above example, perhaps you are adding 10 and 20. The original number 10 may be stored in

the Accumulator whereas the value 20 may be stored in, say, register R4. To process the

addition you would execute the command:

ADD A, R4

After executing this instruction the Accumulator will contain the value 30.

The "B" Register

The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-

byte) value. The "B" register is only used by two 8051 instructions: MUL AB and DIV AB.

Thus, if you want to quickly and easily multiply or divide A by another number, you may

store the other number in "B" and make use of these two instructions.

Aside from the MUL and DIV instructions, the "B" register is often used as yet another

temporary storage register much like a ninth "R" register.

The Data Pointer (DPTR)

The Data Pointer (DPTR) is the 8051s only user-accessible 16-bit (2-byte) register. The

Accumulator, "R" registers, and "B" register are all 1-byte values.

DPTR, as the name suggests, is used to point to data. It is used by a number of commands,

which allow the 8051 to access external memory. When the 8051 accesses external memory

it will access external memory at the address indicated by DPTR.



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While DPTR is most often used to point to data in external memory, many programmers

often take advantage of the fact that its the only true 16-bit register available. It is often used

to store 2-byte values, which have nothing to do with memory locations.

The Program Counter (PC)

The Program Counter (PC) is a 2-byte address, which tells the 8051 where the next

instruction to execute is found in memory. When the 8051 is initialised PC always starts at

0000h and is incremented each time an instruction is executed. It is important to note that PC

isnt always incremented by one. Since some instructions require 2 or 3 bytes the PC will be

incremented by 2 or 3 in these cases.

The Stack Pointer (SP)

The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value.

The Stack Pointer is used to indicate where the next value to be removed from the stack

should be taken from. When you push a value onto the stack, the 8051 first increments the

value of SP and then stores the value at the resulting memory location. When you pop a

value off the stack, the 8051 returns the value from the memory location indicated by SP,

and then decrements the value of SP.

This order of operation is important. When the 8051 is initialised SP will be initialised to

07h. If you immediately push a value onto the stack, the value will be stored in Internal

RAM address 08h. This makes sense taking into account what was mentioned two

paragraphs above: First the 8051 will increment the value of SP (from 07h to 08h) and then

will store the pushed value at that memory address (08h).

SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET,

and RETI. It is also used intrinsically whenever an interrupt is triggered.

Addressing Modes

An "addressing mode" refers to how you are addressing a given memory location. It may be

recalled that 8085 has direct, indirect, memory, immediate, indexed addressing modes. In

summary, the addressing modes are as follows, with an example of each:



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Immediate Addressing MOV A,#20h

Direct Addressing MOV A,30h

Indirect Addressing MOV A,@R0

External Direct MOVX A,@DPTR

Code Indirect MOVC A,@A+DPTR

Each of these addressing modes provides important flexibility.

Immediate Addressing

Immediate addressing is so-named because the value to be stored in memory immediately

follows the operation code in memory. That is, the instruction itself dictates what value will

be stored in memory. For example, the instruction:

MOV A, #20h

This instruction uses Immediate Addressing because the Accumulator will be loaded with the

value that immediately follows; in this case 20 (hexadecimal).

Immediate addressing is very fast since the value to be loaded is included in the instruction..

Direct Addressing

Direct addressing is so-named because the value to be stored in memory is obtained by

directly retrieving it from another memory location. For example:

MOV A, 30h

This instruction will read the data out of Internal RAM address 30 (hexadecimal) and store it

in the Accumulator. Direct addressing is generally fast since, although the value to be loaded

isnt included in the instruction, it is quickly accessible since it is stored in the 8051s

Internal RAM. It is also much more flexible than Immediate Addressing since the value to beloaded is whatever is found at the given address--which may be variable.

Indirect Addressing

Indirect addressing is a very powerful addressing mode which in many cases provides an

exceptional level of flexibility. Indirect addressing is also the only way to access the extra

128 bytes of Internal RAM found on an 8052.

Indirect addressing appears as follows:



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MOV A, @R0

This instruction causes the 8051 to analyse the value of the R0 register. The 8051 will then

load the accumulator with the value from Internal RAM, which is found at the address

indicated by R0.

External Direct

External Memory is accessed using a suite of instructions, which use what I call "External

Direct" addressing. I call it this because it appears to be direct addressing, but it is used to

access external memory rather than internal memory.

There are only two commands that use External Direct addressing mode:

MOVX A, @DPTR

MOVX @DPTR, A

As you can see, both commands utilize DPTR. In these instructions, DPTR must first be

loaded with the address of external memory that you wish to read or write. Once DPTR

holds the correct external memory address, the first command will move the contents of that

external memory address into the Accumulator. The second command will do the opposite: it

will allow you to write the value of the Accumulator to the external memory address pointed

to by DPTR.

External Indirect

External memory can also be accessed using a form of indirect addressing which I call

External Indirect addressing. This form of addressing is usually only used in relatively small

projects that have a very small amount of external RAM. An example of this addressing

mode is:

MOVX @R0,A

Once again, the value of R0 is first read and the value of the Accumulator is written to that

address in External RAM. Since the value of @R0 can only be 00h through FFh the project

would effectively be limited to 256 bytes of External RAM. There are relatively simple

hardware/software tricks that can be implemented to access more than 256 bytes of memory

using External Indirect addressing; however, it is usually easier to use External Direct

addressing if your project has more than 256 bytes of External RAM.



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Interrupts

An interrupt is a special feature, which allows the 8051 to provide the illusion of "multi-

tasking," although in reality the 8051 is only doing one thing at a time. The word "interrupt"

can often be substituted with the word "event."

An interrupt is triggered whenever a corresponding event occurs. When the event occurs, the

8051 temporarily puts "on hold" the normal execution of the program and executes a special

section of code referred to as an interrupt handler. The interrupt handler performs whatever

special functions are required to handle the event and then returns control to the 8051 at

which point program execution continues as if it had never been interrupted.

TimersThe 8051 comes equipped with two timers, both of which may be controlled, set, read, and

configured individually. The 8051 timers have three general functions: 1) Keeping time

and/or calculating the amount of time between events, 2) Counting the events themselves, or

3) Generating baud rates for the serial port.

The three timer uses are distinct so we will talk about each of them separately. The first two

uses will be discussed in this chapter while the use of timers for baud rate generation will be

discussed in the chapter relating to serial ports.

How does a timer count?

How does a timer count? The answer to this question is very simple: A timer always counts

up. It doesnt matter whether the timer is being used as a timer, a counter, or a baud rate

generator: A timer is always incremented by the microcontroller.

USING TIMERS TO MEASURE TIME

Obviously, one of the primary uses of timers is to measure time. We will discuss this use of

timers first and will subsequently discuss the use of timers to count events. When a timer is

used to measure time it is also called an "interval timer" since it is measuring the time of the

interval between two events.

Timer SFRs



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As mentioned before, the 8051 has two timers which each function essentially the same way.

One timer is TIMER0 and the other is TIMER1. The two timers share two SFRs (TMOD and

TCON) which control the timers, and each timer also has two SFRs dedicated solely to itself

(TH0/TL0 and TH1/TL1).

Weve given SFRs names to make it easier to refer to them, but in reality an SFR has a

numeric address. It is often useful to know the numeric address that corresponds to an SFR

name. The SFRs relating to timers are:

SFR Name Description SFR Address

TH0 Timer 0 High Byte 8Ch

TL0 Timer 0 Low Byte 8AhTH1 Timer 1 High Byte 8Dh

TL1 Timer 1 Low Byte 8Bh

TCON Timer Control 88h

TMOD Timer Mode 89h

When you enter the name of an SFR into an assembler, it internally converts it to a number.

For example, the command: MOV TH0,#25h moves the value 25h into the TH0 SFR.

However, since TH0 is the same as SFR address 8Ch this command is equivalent to:

MOV 8Ch,#25h

Timer 0 has two SFRs dedicated exclusively to itself: TH0 and TL0. That is, when Timer 0

has a value of 0, both TH0 and TL0 will contain 0. When Timer 0 has the value 1000, TH0

will hold the high byte of the value (3 decimal) and TL0 will contain the low byte of the

value (232 decimal). Reviewing low/high byte notation, recall that you must multiply the

high byte by 256 and add the low byte to calculate the final value. That is:

TH0 * 256 + TL0 = 1000

3 * 256 + 232 = 1000

Timer 1 works the exact same way, but its SFRs are TH1 and TL1.

Since there are only two bytes devoted to the value of each timer it is apparent that the

maximum value a timer may have is 65,535. If a timer contains the value 65,535 and is

subsequently incremented, it will reset--oroverflow--back to 0.



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The TMOD SFR(89h)

TMOD (Timer Mode). The TMOD SFR is used to control the mode of operation of both

timers. Each bit of the SFR gives the microcontroller specific information concerning how to

run a timer. The high four bits (bits 4 through 7) relate to Timer1 whereas the low four bits

(bits 0 through 3) perform the same functions, for timer0. The individual bits of TMOD have

the following functions:

Bit Name Explanation of Function Timer

7 GATE1When this bit is set the timer will only run when INT1 (P3.3) is high.When this bit is clear the timer will run regardless of the state of INT1.

1

6 C/T1

When this bit is set the timer will count events on T1 (P3.5). When this

bit is clear the timer will be incremented every machine cycle. 1

5 T1M1 Timer mode bit (see below) 1


3 GATE0When this bit is set the timer will only run when INT0 (P3.2) is high.When this bit is clear the timer will run regardless of the state of INT0.

0

2 C/T0When this bit is set the timer will count events on T0 (P3.4). When this

bit is clear the timer will be incremented every machine cycle.0



As you can see in the above chart, four bits (two for each timer) are used to specify a mode

of operation. The modes of operation are:

TxM1 TxM0 Timer Mode Description of Mode

0 0 0 13-bit Timer.

0 1 1 16-bit Timer

1 0 2 8-bit auto-reload

1 1 3 Split timer mode

16-bit Time Mode (mode 1)

Timer mode "1" is a 16-bit timer. This is a very commonly used mode. TLx is incremented

from 0 to 255. When TLx is incremented from 255, it resets to 0 and causes THx to be

incremented by 1. Since this is a full 16-bit timer, the timer may contain up to 65536 distinct

values. If you set a 16-bit timer to 0, it will overflow back to 0 after 65,536 machine cycles.



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8-bit Time Mode (mode 2)

Timer mode "2" is an 8-bit auto-reload mode. When a timer is in mode 2, THx holds the

"reload value" and TLx is the timer itself. Thus, TLx starts counting up. When TLx reaches

255 and is subsequently incremented, instead of resetting to 0 (as in the case of modes 0 and

1), it will be reset to the value stored in THx.

Whats the benefit of auto-reload mode? Perhaps you want the timer to always have a value

from 200 to 255. If you use mode 0 or 1, youd have to check in code to see if the timer had

overflowed and, if so, reset the timer to 200. This takes precious instructions of execution

time to check the value and/or to reload it. When you use mode 2 the microcontroller takes

care of this for you. Once youve configured a timer in mode 2 you dont have to worry

about checking to see if the timer has overflowed nor do you have to worry about resetting

the value--the microcontroller hardware will do it all for you. The auto-reload mode is very

commonly used for establishing a baud rate, which we will talk more about in the Serial

Communications chapter.

The TCON SFR

Finally, theres one more SFR that controls the two timers and provides valuable information

about them. The TCON SFR has the following structure:

TCON (88h) SFR

Bit NameBit

AddressExplanation of Function Timer

7 TF1 8FhTimer 1 Overflow. This bit is set by the microcontroller whenTimer 1 overflows.

1

6 TR1 8Eh

Timer 1 Run. When this bit is set Timer 1 is turned on. When

this bit is clear Timer 1 is off. 1

5 TF0 8DhTimer 0 Overflow. This bit is set by the microcontroller whenTimer 0 overflows.

0

4 TR0 8ChTimer 0 Run. When this bit is set Timer 0 is turned on. Whenthis bit is clear Timer 0 is off.

0

As you may notice, weve only defined 4 of the 8 bits. Thats because the other 4 bits of the

SFR dont have anything to do with timers--they have to do with Interrupts and they will be

discussed in the chapter that addresses interrupts.



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A new piece of information in this chart is the column "bit address." This is because this SFR

is "bit-addressable." What does this mean? It means if you want to set the bit TF1--which is

the highest bit of TCON--you could execute the command:

MOV TCON, #80h

... or, since the SFR is bit-addressable, you could just execute the command:

SETB TF1

This has the benefit of setting the high bit of TCON without changing the value of any of the

other bits of the SFR. Usually when you start or stop a timer you dont want to modify the

other values in TCON, so you take advantage of the fact that the SFR is bit-addressable.

Reading the Timer

There are two common ways of reading the value of a 16-bit timer; which you use depends

on your specific application. You may either read the actual value of the timer as a 16-bit

number, or you may simply detect when the timer has overflowed.

Detecting Timer Overflow

Often it is necessary to just know that the timer has reset to 0. That is, you are not

particularly interest in the value of the timer but rather you are interested in knowing when

the timer has overflowed back to 0.

Whenever a timer overflows from its highest value back to 0, the microcontroller

automatically sets the TFx bit in the TCON register. This is useful since rather than checking

the exact value of the timer you can just check if the TFx bit is set. If TF0 is set it means that

timer 0 has overflowed; if TF1 is set it means that timer 1 has overflowed.

We can use this approach to cause the program to execute a fixed delay. As youll recall, we

calculated earlier that it takes the 8051 1/20th of a second to count from 0 to 46,079.

However, the TFx flag is set when the timer overflows back to 0. Thus, if we want to use the

TFx flag to indicate when 1/20th of a second has passed we must set the timer initially to

65536 less 46079, or 19,457. If we set the timer to 19,457, 1/20th of a second later the timer

will overflow. Thus we come up with the following code to execute a pause of 1/20th of a

second:



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MOV TH0,#76 ;High byte of 19,457 (76 * 256 = 19,456)MOV TL0,#01 ;Low byte of 19,457 (19,456 + 1 = 19,457)MOV TMOD,#01 ;Put Timer 0 in 16-bit modeSETB TR0 ;Make Timer 0 start countingJNB TF0,$ ;If TF0 is not set, jump back to this same instruction

In the above code the first two lines initialise the Timer 0 starting value to 19,457. The next

two instructions configure timer 0 and turn it on. Finally, the last instruction JNB TF0,$,

reads "Jump, if TF0 is not set, back to this same instruction." The "$" operand means, in

most assemblers, the address of the current instruction. Thus as long as the timer has not

overflowed and the TF0 bit has not been set the program will keep executing this same

instruction. After 1/20th of a second timer 0 will overflow, set the TF0 bit, and program

execution will then break out of the loop.



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EPROM 27C64

Currently available EPROM in the market is 8K byte type 27C64. As indicated in the

figure below, this IC needs 13 data lines and 8 data lines apart from an OE (output

Enable) and CS (Chip select) line. Two pins are devoted to VCC and Gnd of the supply.

The remaining pins are left unused in this IC.

The designers have assigned the pins of the memory ICs in such a way, the IC can have

up to 64 Kbytes of memory in the same 28 pin version. The least available capacity is

only 8Kbites and we have used this IC, even though our programme does not occupy

even 5% of its capacity. The PSEN (Programme Store Enable) pin of 80C31 will drive

the chip select of this memory IC. The OE is permanently grounded, as there is no other

memory device to create problem with timing requirement.

The EPROM lends itself to intelligent programming due to increased speed in its

operations. In earlier EPROMs, the bytes are written for a fixed length of time, say 50

mS. In the intelligent programming mode, the bytes are written for a 1 mS only and

verified for correctness. In case it is not written correctly, then the same data is written at

the same location for the next 1 mS. The EPROM is programmed by using a PC based

EPROM programmer, which can programme up to 1 MB of EPROM capacity. The

details are given in the later pages about the EPROM programmer and its operations. The

EPROM can be erased y exposing it to UV light (Shining on the crystal window) for

about 20 Minutes.



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combination of 4 ICs, (2 nos of 74LS573 and 2 nos of 74LS245) to share the port 1 as data

bus. Pin 2 of the combination behaves like D0, pin 3 as D1and so on up to pin 9 as D7.

OCTAL LATCH 74LS573

74LS573 - Octal latch

The Latch IC is used in our design as a Fixed OUTPUT Port to augment the

resources of the micro controller. This IC is also used to separate ADDRESS and DATA

from the multiplexed AD0 to AD7 of the controller. This is an improved version of the

earlier octal latch IC 74LS373. In the earlier version, four input and four outputs are located

on side and the remaining four input and inputs are located on the other side. But this IC hasall inputs located on one side and all output located on other side. Apart from these the

TWO ICs are electrically same. It suits our requirements adequately.

This IC functions as a latch when the pin 11 Latch enable pin goes high. In this

state, the signals present in the pin 2 to pin 9 is transmitted to pin 19 to 12. When the pin 11

LE goes low, this value is latched at the output.

As an address-data separator, this IC gets the latch signal from the ALE pin of the

controller. When the controller is outputting the Address A0 to A7, the ALE goes high and

the address is latched. ALE goes low and the same bus is used for DATA.

This IC is used as an output port in the following way. We connect the pin 11 LE

to a control pin from controller. Pin 2 to pin 9 are connected to pin 1 to pin 8 (Port 1) of the

controller. We put the data to be latched on Port 1 of the controller. We make the pin 11 of

the latch high and then low. The value on Port 1 is now latched at the output. There are two

such OUTPUT ports are used in our design. One of the latch is used to drive the LCDdisplay and we have named this as LCDOUT. The other latch is used for control purpose and



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we have named the latch as CNTOUT. Pin 16 of controller is used to control CNTOUT port

and pin 17 of the controller is used to operate LCDOUT latch.

7805 3 Pin - 5V REGULATOR

This three pin regulator is a boom to power supply

design, when a strict control is needed about the quality

of the output. The simple regulator gets its input from a

bridge connected across a 10 V 1 A transformer. The

pre filtering is done by a 2200 F/25 V capacitor. This IC

gives a constant 5 V DC for the central processor board.

Other parts of the circuit get this regulated voltage from the central processor board.

Adequate heat sink is used to keep the IC operating within safety limits. This IC can supply

constant 5 V DC at about 500 mA (safe value) with simple heat sink. The output remains

same for the range of input from about 6.5 V DC (about 1.5 V DC above the required output

voltage) to 35 V DC.

This IC acts as a series regulator. This means that the IC drops the extra voltage from

the supply and gives constant 5 V DC to the load. So, when the input voltage output

voltage is very high, the IC heats up quickly and a heavy heat sink is needed. The ground pin

is connected to the casing of the IC, making it easy to fix heat sink, which will also be at

ground potential. In this design, using a 10 V secondary transformer would give about 14 V

unregulated DC as input to 7805. As 5 V is the output, about 9 V is the voltage drop on the

regulator. When about 500 mA (0.5 A) current is drawn, the regulator would have to

dissipate heat equivalent to 9 x 0.5 W or about 4.5 W. A simple heat sink will take care of

this dissipation.

These regulators can provide local on-card regulation, eliminating the distribution

problems associated with single point regulation. That is the noise associated with several

circuits drawing power from one point is taken care off. These regulators employ internal

current limiting, thermal shutdown and safe area protection, making it essentially

indestructible. If adequate heat sinking is provided, they can deliver over 1A output current.

Although designed primarily as fixed voltage regulators, these devices can be used with

external components to obtain adjustable voltages and currents. These regulators come invarious packages essentially the difference is the ability to deliver this constant voltage at


The 3 pin Regulator IC


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CHAPTER5:

FLOWDIAGRAM



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WINDOW ANNUNCIATOR FLOW DIAGRAM

YesN No

Yes

Repeated for Ch2, Ch3, & Ch4, Alarm, Clock & Error bit set if detected

No No No

Yes Yes


Start

InitialiseMemoryLocation

Switchoffclocks &windows

IsCh1

=0

Rea

dCh1

Is1T

NCtype

Is itNOType

Clock=fast

Switc

h onfastClock

Switch

onwindow& Alarm

Set Ch1Error bit

Switchon Slowclock

IsReset=0

Istest=0

IsAck=0

Switchoff clock

andBuzzer

Switch offall windows

Switch ONall windows

& fast clock

No

Yes

No

No

Yes


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CHAPTER6:

CONTROL SOFTWARE

(This being copy right portion of the Company, it will be supplied only on request to theHOD and NOT to the students otherwise another 10 pages will be added)



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CHAPTER7:

DETAILSOF MDS FOR8032



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MICRO CONTROLLER DEVELOPMENT SYSTEM

Generally, engineering and other education institutions teach students about 8085

microprocessor using a basic development kit. The kit has a startup program and all required

programs for keyboard entry and output to display units. Students do not get access to any

other microprocessor development system using computers and computer assisted

equipments. So it is an entirely a new experience working with a windows based Simulator,

IN-CIRCUIT EMULATOR (ICE), EPROM PROGRAMMER and assembler software. The

circuits under test can be tested individually, software can be written using a text editors,

assembled and executed the software from the Windows based simulators and ICE to check

for errors. Once perfected, the hex code generated from the control software is then, put inan EPROM. This EPROM supplies the hex code to C. The C now works on its own in the

same it worked with the hardware emulator. The complete project is now ready to be used.

It is thus possible to take up even more complicated assignments with the help of such

development system for a micro controller. Here, a brief explanation is given about the

windows based simulators, ICE, EPROM PROGRAMMER and assembler software that has

been used.

ASSEMBLER AND TEXT EDITOR SOFTWARE:

As students we were exposed only to enter the software to the development kit and

run the same. But first we were to write the mnemonics and find the hex code of the op-code

and fill up the same using this technique. We have to correctly enter the jump addresses and

also the hex code is only entered byte by byte into the MDS (Microprocessor Development

System). To enter the hex code itself is a tedious job and there were fair chances of wecommitting mistake in data entry stage itself. The display is usually a single line display and

not much information is seen in a line. If programme analysis is to be done, then it is

marathon task as register examination or single step is nightmare experience. So it is

altogether a new experience to write the software in a text file and assemble the same using

an assembler and generate HEX and LST file. The HEX file will be in the Industry standard

HEX format and the list file give a neat line number, location of the opcode, our mnemonics

and our comments. The required branching locations are labelled and referring the jump

location by name to the assembler carries out the programme branching.



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The Assembly program required for the project is written by using a simple text

editor like Norton Editor (NE.EXE) part of NORTON utilities. Though any text editing

software can be used, this editor is used for its simplicity and also it is only 64K byte long! It

contains File related commands to save, save as, load, merge and all other related common

commands. This is a DOS based programme like the assembler software. So it is easy to

operate the text editor and assembler in the same operating mode. This editor lends it to be

configured for any specific use and the tab setting allows us to write a very legible

programme without much effort.

ASSEMBLER DIRECTIVE:

The cross assembler that is used to assemble our programme is supplied along with

the book - The 8051 Microcontroller Architecture, Programming & Applications By

Kenneth J Ayala. The floppy disk accompanying the book contains this software and a

wealth of information about how to use this assembler software. This assembler is

specifically designed for 8051 family of controllers. There is no need to specify the

processor for which the assembly is to be done. The assembler has several features that make

writing mnemonics very easy.

This assembler assembles the program in a TWO-pass assembly. This is because, in

the first pass the assembler may encounter a forward referenced label, for which it cannot

substitute a memory a

window annuciator - project report

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