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(When) Will FPGAs Kill (When) Will FPGAs Kill ASICs? ASICs? Rajeev Jayaraman Rajeev Jayaraman Xilinx Inc. Xilinx Inc. DAC DAC - - 2001 2001 1 1

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FPGA vs ASIC

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Page 1: Will Asic kill FPGA

(When) Will FPGAs Kill (When) Will FPGAs Kill ASICs?ASICs?

Rajeev JayaramanRajeev JayaramanXilinx Inc.Xilinx Inc.

DACDAC--20012001

11

Page 2: Will Asic kill FPGA

DAC-RJ 6/20/012

FPGAs vs. ASICsFPGAs vs. ASICs

�� Cost Cost –– the real story.the real story.�� Time to marketTime to market�� Why choose ASICs?Why choose ASICs?�� Where are FPGAs going?Where are FPGAs going?

Page 3: Will Asic kill FPGA

DAC-RJ 6/20/013

Unit Cost AnalysisUnit Cost Analysis

Volume K units

Total cost

ASIC .25µ

FPGA .25µFPGA .15µ

ASIC .15µ

ASIC Costs Start higher,

but slope is flatter

For each technology advance, crossover volume moves higher

Page 4: Will Asic kill FPGA

DAC-RJ 6/20/014

Cost: The exploding ASIC NRECost: The exploding ASIC NRE

$0

$1,000,000

$2,000,000

$3,000,000

$4,000,000

0.050.10.150.20.25

Process Geometry (Micron)

NRE

and

Mask

Cos

ts

0.35

Source: Dataquest

Page 5: Will Asic kill FPGA

DAC-RJ 6/20/015

Time to market is criticalTime to market is critical

Start of market window End of market

Reve

nue

Time

Long time to market is a cost

Missing the market window will wipe out all savings fromdevelopment and production

Potential profit if you come early to the market

FPGA

What you get if youdesign with an ASICand come late to the market

ASIC

Page 6: Will Asic kill FPGA

DAC-RJ 6/20/016

Extend the market window with reconfigurability(with FPGAs)

COST: System ReconfigurabilityCOST: System ReconfigurabilityRe

venu

e

TimeLack of reconfigurability is a huge opportunity cost of ASICsFPGAs offer flexible life cycle management

Without reconfigurability(with ASICs)

Page 7: Will Asic kill FPGA

DAC-RJ 6/20/017

Breakeven Cost: Just the factsBreakeven Cost: Just the facts

Total cost ASIC

Volume K units

Time-to-market Re-spins & Inventory

Unit cost

Page 8: Will Asic kill FPGA

DAC-RJ 6/20/018

Time To Market: Design CycleTime To Market: Design Cycle

Spec Design & verification SiliconPrototype

System Integration

Production FirstShip

ASIC

Spec Design andverification

System Integration

Production FirstShip

FPGA

Freeze design

• ASIC Methodology is very unforgiving• FPGA flexibility allows late design changes

Iterations?

Freeze design

Page 9: Will Asic kill FPGA

DAC-RJ 6/20/019

Designing with ASICsDesigning with ASICs

Timing Closure is a very serious problem in DSM

DSMEffects

ProcessissuesVerification

Page 10: Will Asic kill FPGA

DAC-RJ 6/20/0110

is much simpler

Designing with FPGAsDesigning with FPGAs

Timing Closure is a much simpler problem in FPGAs

Super fast compile times~1M gates in < 1hr

DSMEffects

Processissues

Verification

Page 11: Will Asic kill FPGA

DAC-RJ 6/20/0111

Why do people design ASICs?Why do people design ASICs?

DensityDensity

PerformancePerformanceCost/VolumeCost/Volume

IP LibrariesIP Libraries

Page 12: Will Asic kill FPGA

DAC-RJ 6/20/0112

Volume requirement for ASICsVolume requirement for ASICsCostCost

DensityDensity

PerformancePerformance

IP LibrariesIP Libraries

48.1

6

45.9<100K100-250K>250K

>50% of market is available today for FPGAs

Source: IMS 2000

Page 13: Will Asic kill FPGA

DAC-RJ 6/20/0113

Gate count requirement for ASICsGate count requirement for ASICsCostCost

DensityDensity

PerformancePerformance

IP LibrariesIP Libraries

73

20

7

<3M3-5M>5M

FPGAs can address very large part of the ASIC market today

Source: IMS 2000

Page 14: Will Asic kill FPGA

DAC-RJ 6/20/0114

Performance requirement for ASICsPerformance requirement for ASICsCostCost

DensityDensity

PerformancePerformance

IP LibrariesIP Libraries

53.938.5

10.8

<100Mhz100-200Mhz>200Mhz

FPGAs can address very large part of the ASIC market today

Source: IMS 2000

Page 15: Will Asic kill FPGA

DAC-RJ 6/20/0115

IP in FPGAsIP in FPGAsCostCost

DensityDensity

PerformancePerformance

IP LibrariesIP Libraries

5 Years ago FPGAs were only gates and routing~25000 gates

Multipliers

RAM

Clock management FIFO/CAM

Processors

Multiple I/O Standards

High Speed I/O: LVDS, Gigabit

Today, there are several system-level features.~10,000,000 gates

The trend to add more IP in FPGAs continues

Page 16: Will Asic kill FPGA

DAC-RJ 6/20/0116

The Question is …The Question is …�� The question is not if FPGAs will kill ASICsThe question is not if FPGAs will kill ASICs

—— Everyone understands the advantages of Everyone understands the advantages of programmabilityprogrammability

�� The real question is “How can I get programmability The real question is “How can I get programmability in my system?”in my system?”

�� More IP on an FPGA or More IP on an FPGA or Progammability Progammability on an on an ASIC?ASIC?

Page 17: Will Asic kill FPGA

DAC-RJ 6/20/0117

What is the future? You decide…What is the future? You decide…

Design Design methodology/methodology/SoftwareSoftware

CostCost

TimeTime--toto--marketmarket

More More ProgProg. On ASIC. On ASICMore IP on FPGAMore IP on FPGA

Verification remains simpleTiming closure is easier

Verification remains a problemTiming closure remains an issue

NRE not reducedVery limited reconfigurability

NRE is non-existentExtensive reconfigurability

Simple methodologyEase of useExtremely fast SW runtimes

Still a complex methodologyEase of use is still lacking


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