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Width Quantization Aware FinFETCircuit Design

Jie Gu, John Keane, Sachin Sapatnekar, and Chris H. Kim

University of MinnesotaDepartment of Electrical and Computer Engineering

jiegu@ece.umn.edu

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Outline• Width quantized FinFET overview• Conventional leakage estimation• Proposed leakage estimation approach• Statistical leakage comparison• Applications on FinFET circuit design

– Dynamic circuits– Subthreshold logic

• Conclusions

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Double-gate FinFET Device

• Advantages:– Excellent short-channel behavior– Ideal subthreshold swing– Independent gate control

N. J. Nowak, IBM

• Challenges:– Increased process complexity– Width quantization

I DS(

A/µ

m)

VGS(V)

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Width Quantization of FinFET DeviceN. J. Nowak, IBM

FinFET fabrication processFinFET layout

• Same fin height due to process requirement• One large device built from multiple unit fins• Random VT variation among fins, e.g. random dopant

fluctuation (RDF)

Bulk CMOS layout

I

II

III

IV

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Problems in Conventional Leakage Estimation

Tx

Tx

Ti

VTi

VTi

4

1i

/mkTqVleak

)(V

)µ(V

WeI

σσ

µ

=

=

= ∑=

−

4/)(V

)µ(V

We4I

Tx

Tx

T

VT

VT

/mkTqVleak

σσ

µ

=′

=′=

′−

• Conventional approach assume:– Mean µ of effective V'T does not change; Inaccurate– Sigma σ of effective V'T is proportional to ; Inaccurate

• 3σ leakage can be underestimated by 50%LW/1 ⋅

6

Proposed Statistical Leakage Estimation

Tx

Tx

Ti

VTi

VTi

n

1i

/mkTqVleak

)(V

)µ(V

WeI

σσ

µ

=

=

= ∑=

−

n/)(V

)µ(V

WenI

Tx

Tx

T

VT

VT

/mkTqVleak

σσ

µ

=′

=′=

′−

)n,(f)(V

)n,,(f)µ(V

WenI

Tx

TxTx

T

VT

VVT

/mkTqVleak

σσ

σµ

σ

µ

=″

=″=

′′−

• Accurate modeling of fin-to-fin VT variation• Sum of individual fin leakages modeled using a single

device effective VT’’

• VT’’ distribution is a function of the # of fins, µ, and σ

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Wilkinson’s Method

2/m2/mn

1i1

2yy

2ixix nee)S(Eu σσ ++

=

=== ∑

2yyjxixij

2jx

2ixjxix

2ixix 2m222/)r2(mm

n

1ij

1n

1i

2m2n

1i

22 enee2e)S(Eu σσσσσσ ++++

+=

−

=

+

=

=+== ∑∑∑

122y

21y

uln2ulnuln2/1uln2m

−=−=

σ

),m(ii xx σ ),m( yy σand are the mean and standard deviation

of the original Gaussian variables xi and the new Gaussian variable y of the lognormal functions, respectively rij is the correlation coefficient of each random variable

First moment:

Second moment:

Moment matching result:

yxn

1i

nWeeW i ≅∑=

• In Wilkinson’s approach, a sum of lognormals can be approximated as another lognormal with a calculable mean and standard deviation

(y is a new Gaussian variable calculated by moments matching)

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200

150

100

50TyVσ

B∆/21

TxVσ

VT (V)

TyVµ

TxVµ

Proposed Leakage Distribution Model

0)(∆∆/Bσσ

∆/B21µµ

22V

2V

VV

TxTy

TxTy

≥−=

−=

)n

e1)(neln(σB∆2TxV

22TxV

2

Tx

σrBσB2V

2 ⋅−+−=

where

mkTqV

mkTqVn

1i

TyiTx

nWeeW−−

=

≅∑VTy: device effective VTVTx: VT of unit fin

# of

Dev

ices

• From Wilkinson’s method, we find the distribution of VTy

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FinFET Model for Device Simulation

Simulated Ids–Vgs characteristics

0.22VVT

0.8VVdd

30nmDevice Height H5nmBody Thickness TSi

14ÅOxide Thickness Tox

21nmEffective Channel Length Leff

25nmDrawn Channel Length Ldrawn

Device parameters in FinFET model

Taurus model

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Simulation Results (w/o VT Correlation)

• Conventional approach underestimates leakage by up to 58%

• Our work estimates leakage with an error less than 5%

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Simulation Results (w/ VT Correlation)

• Proposed work’s estimation error is less than 2% for a wide-range of VT correlation

• As the correlation coefficient r increases towards 1, the distribution converges to a single device distribution

(r: correlation coefficient)

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Error Comparison Varying the # of Fins and σ

• Error from conventional approach grows quickly with an increased

• Proposed approach consistently exhibits small error in leakage estimation

TxVσ

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FinFET Design Example: Dynamic Circuits ─ Keeper Sizing

• Static keeper prevents the dynamic node droop• Keeper has to be properly sized for sufficient noise margin• Accurate leakage estimation is critical for meeting noise margin

requirements

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FinFET Design Example: Dynamic Circuits ─ Keeper Sizing

• Conventional approach predicts insufficient keeper size because of the underestimation of leakage

• This work shows that 10%–108% sizing up of keeper is needed to meet the target SNM

(SNM: Static Noise Margin)

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FinFET Design Example: Subthreshold Logic ─ Timing Analysis

∑=

−=∝

#fin

1i

mkTqV

leakstage_one_delay

Txi

We

1I1T

∑∑

∑=

=

−=

=∝#stage

1j#fin

1i

mkTqV

#stage

1j j,leakstages_multi_delay

j,Txi

We

1I1T

One stage:

Multi-stages:

leak

dddelay I

VCT

⋅∝

Subthreshold circuit operates using leakage current for maximum power saving.

(Apply Wilkinson’s method twice)

• Delay in subthreshold circuit is an exponential function of VT

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FinFET Design Example: Subthreshold Logic ─ Timing Analysis

Delay distribution of 20-stage inverter chain

• Conventional approach overestimates delay by 24%• Statistical timing analysis is accurately performed in this

work

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Conclusions• FinFETs are promising for sub-25nm technologies• Conventional leakage estimation fails to accurately model

the effects of :– large random VT variation– width quantization

• Error from conventional approach is more than 50%• Proposed approach based on Wilkinson’s method:

– provides precise leakage estimation with error less than 5%– handles both uncorrelated and correlated fins correctly– useful for FinFET circuit applications such as dynamic

circuits and subthreshold logic