when to use an fpga to prototype a controller and how to start€¦ · why would i use an fpga to...
TRANSCRIPT
![Page 1: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/1.jpg)
1© 2015 The MathWorks, Inc.
When to use an FPGA to prototype a controller and how to start
Mark Corless, Principal Application Engineer, Novi MIBrad Hieb, Principal Application Engineer, Novi MI
![Page 2: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/2.jpg)
2
When to use an FPGA to prototype a controller and how to start
Why would you use a processor and an FPGA to prototype a controller?
How can the Simulink platform help you get started?
How is modeling for an FPGA different than modeling for a processor?
![Page 3: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/3.jpg)
3
High resolution voltage
modulation
High speedcontrol loops
Critical diagnostics
Position sensing
System cost reduction
Why would I use an FPGA to prototype a controller component?
FPGA = Field Programmable Gate Array
![Page 4: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/4.jpg)
4
Consider execution rate and development time when partitioning a design
100’s MHz100’s Hz
FPGA(HDL Code)
Processor(C Code)
ComponentExecution Rate
Development Time
![Page 5: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/5.jpg)
5
Let’s look at an example
![Page 6: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/6.jpg)
6
How would you partition this controller with disparate rate components?
10 kHz Rate
• Field oriented control• ADC to current• Encoder to position• Position to velocity• Voltage to PWM
1 kHz Rate
• Velocity control• Mode scheduler• Encoder calibration
50 MHz Rate
• PWM peripheral• Encoder peripheral
![Page 7: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/7.jpg)
7
Example of partitioning controller components based on execution rates
FPGAMicroprocessor
10 kHz Rate
• Field oriented control• ADC to current• Encoder to position• Position to velocity• Voltage to PWM
1 kHz Rate
• Velocity control• Mode scheduler• Encoder calibration
50 MHz Rate
• PWM peripheral• Encoder peripheral
![Page 8: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/8.jpg)
8
How do I get started?
![Page 9: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/9.jpg)
9
Get started building one piece at a time
FPGA
50 MHz Rate
• PWM peripheral
![Page 10: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/10.jpg)
10
Video: How did the Simulink platform help us get started?
![Page 11: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/11.jpg)
11
Example of partitioning controller components based on execution rates
FPGAMicroprocessor
10 kHz Rate
• Field oriented control• ADC to current• Encoder to position• Position to velocity• Voltage to PWM
1 kHz Rate
• Velocity control• Mode scheduler• Encoder calibration
50 MHz Rate
• PWM peripheral• Encoder peripheral
![Page 12: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/12.jpg)
12
10 kHz worked!
Time (sec)2 2.2 2.4 2.6 2.8 3
-20
0
20
40
60
80
100
Rotor Velocity (10kHz PWM)
velocityCommandrotorVelocity (Sim)rotorVelocity (Hw)
Time (sec)2 2.2 2.4 2.6 2.8 3
-2
-1
0
1
2
3
4Phase A Current (10kHz PWM)
phaseCurrentA (Hw)phaseCurrentA (Sim)
![Page 13: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/13.jpg)
13
Where should a 50 kHz control loop be implemented?
FPGAMicroprocessor
50 kHz Rate
• Field oriented control• ADC to current• Encoder to position• Position to velocity• Voltage to PWM
1 kHz Rate
• Velocity control• Mode scheduler• Encoder calibration
50 MHz Rate
• PWM peripheral• Encoder peripheral
???
![Page 14: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/14.jpg)
14
Timing analysis at baseline 10 kHz on CPU
![Page 15: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/15.jpg)
15
Timing estimation of initial design at 50 kHz
![Page 16: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/16.jpg)
16
Trying the initial design at 50kHz
![Page 17: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/17.jpg)
17
What else do we need to be aware of to implement the 50 kHz rate on the FPGA?
FPGAMicroprocessor
50 kHz Rate
• Field oriented control• ADC to current• Encoder to position• Position to velocity• Voltage to PWM
1 kHz Rate
• Velocity control• Mode scheduler• Encoder calibration
50 MHz Rate
• PWM peripheral• Encoder peripheral
![Page 18: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/18.jpg)
18
Simplify timing constraints by separating disparate rates with low rate delays
Integrate 50 kHz control loop with 50 MHz peripheral
components
![Page 19: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/19.jpg)
19
Simplify timing constraints by separating disparate rates with low rate delays
Using slow rate delays to at rate boundaries makes it simple to create a timing
constraint file for Xilinx tools
![Page 20: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/20.jpg)
20
Add fixed-point implementation details to math operations
Math is typically implemented in fixed-point when modeling
for FPGA implementation
![Page 21: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/21.jpg)
21
Avoid function call triggers and explicitly reset states in enabled subsystems
Explicitly reset statesusing signals
![Page 22: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/22.jpg)
22
CPU timing with 50 kHz components on FPGA
![Page 23: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/23.jpg)
23
Implementing 50 kHz components on FPGA behaves correctly
Time (sec)2 2.2 2.4 2.6 2.8 3
-20
0
20
40
60
80
100
Rotor Velocity (50kHz PWM)
velocityCommandrotorVelocity (Hw)rotorVelocity (Sim)
Time (sec)2 2.2 2.4 2.6 2.8 3
-2
-1
0
1
2
3
4Phase A Current (50kHz PWM)
phaseCurrentA (Hw)phaseCurrentA (Sim)
![Page 24: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/24.jpg)
24
Implementing 50 kHz components on FPGA behaves correctly
Time (sec)2 2.2 2.4 2.6 2.8 3
-20
0
20
40
60
80
100
Rotor Velocity (50kHz PWM)
velocityCommandrotorVelocity (Hw)rotorVelocity (Sim)
![Page 25: When to use an FPGA to prototype a controller and how to start€¦ · Why would I use an FPGA to prototype a controller component? FPGA = Field Programmable Gate Array. 4 Consider](https://reader030.vdocuments.us/reader030/viewer/2022041110/5f0f97f27e708231d444ef09/html5/thumbnails/25.jpg)
25
When to use an FPGA to prototype a controller and how to start
Why would you use a processor and an FPGA to prototype a controller?– When a processor can not meet execution timing for the component– When the final implementation will not include a processor
How can the Simulink platform help you get started?– Simulate algorithms to reduce dependency on hardware– Design and generate C/HDL algorithmic code from one environment– Automate deployment to prototyping hardware with processor and FPGA
How is modeling for an FPGA different than modeling for a processor?– Simplify timing constraints by separating disparate rates with low rate delays– Add fixed-point implementation details to math operations– Avoid function call triggers and explicitly reset states in enabled subsystems