3D-ICan Enabler Technologyand a new Landscape

Yves Leduc

Advanced System TechnologyNovember 2009

What every Architect should know about Technology,Sani R. Nassif,IBM Research Austin.Design Variability: Challenges and Solutions at microarchitecture -architecture levelDATE’08, München

MANUFACTURABILITY:

the ability to create PROFITABLE IC’s.

Forewarning, our only concern:

• Motivation• Glossary• Technology• Enabled Innovations• Status

• New Jobs

Motivations

3D-SIP

3D-STV

According to SEMATECH http://www.sematech.org/research/3D/index.htm

The advantages of 3D-TSV over the alternativesBy combining the performance and power of system-on-chip (SOC) with the functionality and time-to-market advantages of system-in-package (SiP), TSV offers the best of both for achieving very high densities for memory and logic. Its advantages over SoC and SiP include:

Greater density for the same footprint More functionality Higher performance Lower power consumption Lower cost More manufacturing flexibility Faster time to market

2D Span of Control n r2

3D Span of Control n r3

Larger the die, more appealing is 3D interconnect

r

x

y

r

z

x

y

Glossary

• F2F, where dies are soldered Face to Face

• B2F, where dies are bonded Back to Face

Glossary: F2F, B2F

Padsdies interface

Pads

dies interface

dies interface

Microbumps

Silicon Through Vias aka STV

• D2W, Die to Wafer Soldering F2FBonding B2F

• W2W, Wafer to Wafer Bonding B2F

Glossary: D2W, W2W

3D-IC’s

F2F

F2F

Multi B2F

B2F WSP Compatible

One Exampleof

3D-IC Technology

B2F, D2W

an Example from IMEC: 3D-IC [ Snapshot ]

Processedwafer A,with STV

Processedwafer B

Temporary carrierTemporary carrier bonding

Silicon of wafer A thinningDies singulation

Dies A to wafer B alignment

Die bonding Super diessingulation

Carrierremoval

Super diesAdhesivecoating

Temporaryadhesivecoating

Super-dies are singulated

an Example from IMEC: 3D-IC

Carrier

Technical Dashboard

• What is IMPORTANT to have?

The removal of the die to die ESD protections to get the density ofSTV without impacting the circuit integration.Low pin count solution to make WSP possible.Thermal awareness.

• What will be the key ENABLER?

Wafer thinning technology drives directly cost and STV densities.

• What -SEEM- to be the BEST technical options?

B2F, as bonding should be preferred to soldering for STV densities.? ‘Vias First’ STV brings highest density, but processed in wafer fab? ‘Vias Last’ STV are built in assembly plantD2W or W2W: currently unclear.

Single Chips

Side by Side Dies

Stacked Dies

F2F

B2F

Usage:

System area

System cost

Performances

Flexibility

Heat dissipation

PCB process complexity

Package process complexity

Risks

Technology maturity

WSP compatibility

Enabled Innovations

3D-IC is a technology breaking the boundaries of IC’s.It offers direct connections between modules.

The super-die created by the bonding of several dies is not an assemblyof dies but a true SOC with superior connections.

Die 1

Die 2

Die 3

One Super-Die

>1000’s connections / mm2

3D-IC is a SOC Technology

69

87

5

32

41

1312

1411

10

Compared to 2D counterparts, 3D-IC SOC’s have shorter connections to manymore neighbors. They offer many more connection planes and shorter pathsto route signals.

3D Topology brings more Compact Architecture

There is no need to specific drivers to make die to die connectionsThere is no need to place ESD protections on these internal connections

Superior Connections without Penalty

1.2V

1.2V – 3.0V

Low RLC connections

No padNo ESD protection

PadsESD protectionsI/O’s

• Massive transfer between cache memories breaks data transfer bottleneck.• Tuned processes offer lower cost and better performances.• Enhanced connection capability by enabling efficient NOC solutions.

SRAM cache 1DSPARM…

NOCSRAM cache 2Embedded PMI/O’s…

1.2V

Low leakage 1.2V – 3.0V

1 000’s connections

Example of Enhanced Performances SOC

Example of a Flexible Platform

1 000’s connections

Processors

WiFi, Bluetooth, NFC.. USB, FireWire..NOC..Power Management..…

1 000’s connections

Memory

1.2V

1.2V – 3.0V

Enabling Application: Memory!

8 * Memory N bits = Memory N bytes

8 identical IC’s

Manufacturability

Our only concern:

According to

“Today, fabs running iTSV can produce 3D-TSV devices at a total Cost of Ownership of less than $150usd per wafer.

Improved synchronization between the unit processes along with aggressive cost saving designs have been very successful at exceeding the consortium’s original cost goals.”

http://www.emc3d.org/documents/pressReleases/2009/EMC3D_consortium_continuation_July2009.pdf

[ July 2009 ] CW = (CF+CV+CY)/(TPT*Y*U)

where: CW = Cost per waferCF = Fixed costCV = Variable costCY = Cost due to yield lossTPT = ThroughputY = Composite YieldU = Utilization

Samsung debuts world’s thinnest multi-die package

Samsung Electronics has developed the world’s thinnest multi-die package, one that measures 0.6mm in height. Designed initially for 32 gigabyte (GB) densities, the new memory package is just half the thickness of a conventional memory package of eight stacked chips (or dies). The advanced packaging technology delivers a 40 percent thinner and lighter memory solution for high-density multimedia handsets and other mobile devices, according to the company.

[…]  

The newly developed ultra-thinning technology overcomes the conventional technology limits of a chip’s resistance to external pressure when under 30um in height. The productivity decline resulting from this thickness limitation had been directly attributable to a drop in production yields during mass production.

[…]

The 15um-thickness represents a significant achievement as it can allow for double the density of previous multi-chip packages. The thinner die also dramatically reduces chip weight.In addition, the new package technology can be adapted to other existing MCPs, configured as system in packages (SiPs), or package on packages (PoPs). The breakthrough technique for 15um-and-under chip thicknesses will allow for the design of very high density solutions with the smallest of form factors – an extremely attractive prospect for the highly competitive mobile market.

http://www.electroiq.com/index/display/article-display/3608609647/articles/advanced-packaging/industry-news/2009/11/samsung-debuts_world.html

[ November 2009 ]

KEY ENABLER

System [r]evolution

New know-how !

The Job of IC Designers is Changing!

3D-IC is bringing many new degrees of freedom.Packaging becomes a key technology and impacts early decisions.System partitioning is more important than ever.Early analysis is essential.Analysis must be done from PCB to Silicon.

Analyze systems at the highest level.Job is too serious to not involve early technical specialists.

Need a Strong Expertise in System Exploration, What-If analysis:-> Process Performances Understanding and Cost evaluation-> Specification modeling and simulation-> Transaction level modeling and simulation-> High Level Mixed Signal modeling and simulation-> Heterogeneous modeling and simulation-> Thermal modeling and simulation-> Advanced Packaging…

Open for discussion !