webinar: mmc- technologies - pscad...2. dq decoupled vector current control 3. half and h-bridge...

© Manitoba HVDC Research Centre | a division of Manitoba Hydro International Ltd. 1

MMC- Technologies

Presenters: Juan Carlos Garcia and Farid MosallatFebruary 26 - 2015

Webinar:


1. Modular multi-level converters2. dq decoupled vector current control3. Half and H-bridge converters4. Detailed equivalent models of MMC valves5. Simulation of a two-terminal system6. Simulation of a dc-fault and re-start process (half- and H-bridge

MMCs)7. Setup of a three-terminal system (on-line demonstration – if time

allows)8. Questions

Table of contents

© Manitoba HVDC Research Centre | a division of Manitoba Hydro International Ltd.


If you have questions during the Webinar


• Please e-mail PSCAD Support at

[email protected]


∠0 ∠

Grid-connected VSC:Operation principle

Neglecting R:

V

E

jXLII

V

E jXLII

Supplying P:

Absorbing P:

Supplying Q:

Absorbing Q:

I V

E

jXLIδ

V

EjXLII δ

sin

cos

∗ ⇒

∠0 ∠


Phase Locked Loop (PLL)


t [s] 2.520 2.540 2.560 2.580 2.600 2.620 2.640 2.660 2.680 2.700

50

60

70

80

90

100

110

[Hz]

fsrc f (PLL)

0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0

[rad]

Theta

-0.60 -0.50 -0.40 -0.30 -0.20 -0.10 0.00 0.10

[kV]

Vq

-1.00

-0.50

0.00

0.50

1.00

[kV]

Cos(Theta) Va

Extracting the phase angle of phase-A voltage

© Manitoba HVDC Research Centre | a division of Manitoba Hydro International Ltd. 6© Manitoba HVDC Research Centre | a division of Manitoba Hydro International Ltd.

Basic control modes: (P/VDC), (Q/VAC)

Control modes for grid-connected operation

VabcPLL θ

abc

dq

θ

Iabc idq

abc

dq

θ

Vabc vdq

1: P control

2: Vdc

control

Q*

-Q

PId/dt

Rate limiter

d/dt

Rate limiter

Vac*

DacQ

VAC droop

Vrms

- PI

1: Q control

2: Vac controlVAC droop controller

VAC controller

Q controller

Current limiter id*

iq*

Imax

iq1*

Decoupledcurrent

controller

id iq

vd*

vq*

dq

abc

θVabc

*

Valve controls

P*

-PPI

d/dt

Rate limiter

d/dt

Rate limiter

Vdc*

-Vdc

PI

VDC controller

P controller

id1*


Current vector control with PLL locking to phase A voltage (cosine function)

L

vd

x1ed

iq

+- -

L

vq

x2eq

id

+-+

PI

PI

+-

-+

id*

iq*

Decoupled current control strategy


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC

Modular multilevel converters


VDC

VDCVDC

VDC

VDC

VDC

VDC

VDC

VDC

VDCVDCVDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

VDC

VDC

VDC

VDC

VDCVDCVDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

VDC

VDC

VDC

VDC

VDCVDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

VDC

VDC

VDC

VDC

VDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

VDC

VDC

VDC

VDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

VDC

VDC

VDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

VDC

VDC

+VDC/2

-VDC/2

EV

VAC


: Graphs

sec 0.0000 0.0050 0.0100 0.0150 0.0200

-1.00

-0.50

0.00

0.50

1.00

E reference Eac MMC

VDC



VDC

VDCVDC

VDC

VDC

VDC

+VDC/2

-VDC/2

EV

VAC


Types of MMC


Siemens diagramHalf-Bridge MMC 2009

Note: Filters not required


VSC Valves: MMC


ABB diagram

Half-Bridge – Cascaded 2-level converter


VSC Valves: MMC

Full- or H-bridge cells


Half-bridge MMC



Half-bridge MMC


Three operating states in the half-bridge cell

State description GatesInsert +Vc (T2)

Bypass capacitor (T1)Blocked None

Forbidden (T1,T2)


Half-bridge MMC


2

2

D +

F

-

Vac_refTVdc

*0.5

Vac_ref

D +

F

+

Vac_refBVdc

*0.5

Vac_ref

Note: Half-bridge CAN NOT generate 0


Half-bridge MMC


2 2

2⁄ 00 2⁄ 2⁄

2⁄ 0

Assuming modulating index = 1

2


Capacitor balancing: sorting method – Half-bridge cell


iac < 0 iac > 0Inserted cell Discharges capacitor Charges capacitor

Bypassed cell

Prevents discharging of capacitor

Prevents charging of capacitor


Capacitor balancing: sorting method – Half-bridge cell


Actionrequested iac < 0 iac > 0Insert cell Insert cell with highest voltage Insert cell with lowest voltage

Bypass cell Bypass cell with lowest voltage Bypass cell with highest voltage

IGBT firing strategy

PWM, Level switching

Request for insertion or bypass of a cell capacitor

Measurements

Vcapacitors, Iac

Ordering of capacitors by voltage

Firing order according to table below

IGBT Firing orders

Balanced capacitor voltages


Low Level Controls


Stages

Reference voltage waves

IGBT firing strategy

PWM, NLC, etc.

Half-bridge cell Capacitor balancing algorithm

Balanced capacitor voltages

Sinusoidal(*)

AC voltages

(*) or with harmonic content as required


H-bridge MMC (full-bridge)



H-bridge


Four operating states

T1 T2

T3 T4

State description Gates

Insert +Vc (T1,T4)

Insert -Vc (T3,T2)

Bypass capacitor (T1,T2) or (T3,T4)

Blocked None

Forbidden (T1,T3) & (T2,T4)


Insert +Vc (T1,T4)Insert -Vc (T3,T2)


Blocked None



Insert +Vc (T1,T4)

Insert -Vc (T3,T2)Bypass capacitor (T1,T2) or (T3,T4)

Blocked None



Insert +Vc (T1,T4)

Insert -Vc (T3,T2)


Blocked None



Insert +Vc (T1,T4)

Insert -Vc (T3,T2)

Bypass capacitor (T1,T2) or (T3,T4)Blocked None



Insert +Vc (T1,T4)

Insert -Vc (T3,T2)


Blocked NoneForbidden (T1,T3) & (T2,T4)


Insert +Vc (T1,T4)

Insert -Vc (T3,T2)


Blocked None



H-bridge

2

2

D +

F

-

Vac_refTVdc

*0.5

Vac_ref

D +

F

+

Vac_refBVdc

*0.5

Vac_ref

Note: H-bridge CAN generate 0


Half-bridge MMC


2 2

1.25 2⁄ 0.125 1.1252⁄ 0

0 2⁄ 2⁄

2⁄ 0

1.25 2⁄ 1.125 0.125

Assuming modulating index = 1.25

1.25 2

1.125


Modelling techniques:MMC valves

• Simulation of MMC VSCs can involve hundreds of nodes. This significantly reduces simulation speed. Half-

bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Half-bridge

Vdc

Q1

Q2

C

Can be in the order of a few hundred cells

per arm


• Using Thevenin equivalent:(detailed equivalent model)

Q1

Q2

C

U. N. Gnanarathna, A. M. Gole, and R. P.Jayasinghe, "Efficient Modeling of Modular Multilevel HVDC Converters (MMC) on Electromagnetic Transient Simulation Programs," IEEE Transactions on Power Delivery, vol.26, no.1, pp.316-324, Jan. 2011



• Using Thevenin equivalent:(detailed equivalent model)

• This type of model is identified in CIGRE WB B4-57 as model Type-4

• This model is good for system wide studies and for most DC fault simulations


Ic24

Ic23

Ic22

Ic21

Ic20

Ic19

Ic18

Ic17

Ic16

Ic15

Ic14

Ic13

Ic12

Ic11

Ic10

Ic9

Ic8

Ic7

Ic6

Ic5

Ic4

Ic3

Ic2

Ic1

FP15

FP16

FP14

FP13

FP17

FP18

FP20

FP19

FP23

FP24

FP22

FP21

Vc24

Vc23

Vc22

Vc21

Vc19

Vc20

Vc18

Vc17

Vc16

Vc15

Vc14

Vc13

Vc12

Vc11

Vc10

Vc9

Vc8

Vc7

Vc6

Vc5

Vc4

Vc3

Vc2

Vc1

FP3

FP4

FP2

FP1

FP5

FP6

FP8

FP7

FP11

FP12

FP10

FP9

N1

N1

n2l

i1l

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+

-

+ 100s of nodes into 3 nodes

Ic

Vc

x10


Grid AC network in black start

mode© Manitoba HVDC Research Centre | a division of Manitoba Hydro International Ltd.

Converter 1: Grid-connected mode ⟶Controls Vdc and Q (or Vac) Converter 2: Grid-connected mode ⟶Controls P and Q (or Vac) – in black start

mode

Start-up sequence

Converter 1• Energize transformer & Pre-

charge• Bypass pre-insertion resistor• Deblock converter 1• Regulate Vdc

Converter 2After Vdc is regulated:• Deblock converter 2• Regulate Vac• Ramp-up power transfer

Converter 1 Converter 2

Vac

VdcVdc

P


Start-up sequence

t [s] 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60

-1.00

-0.50

0.00

0.50

1.00

(p.

u.)

Vac - onshore

-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00

(p.

u.)

Iac T - Onshore

0.00

0.20

0.40

0.60 0.80

1.00

1.20

(p.

u.)

Vdc at onshore terminal (P-P)

-0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80

(p.

u.)

Idc (onshore -> offshore)

t [s] 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60

-1.25

1.25

(p.

u.)

Vac - Offshore

-0.40

-0.20

0.00

0.20

0.40

(p.

u.)

Iac - Offshore

0.00 0.20 0.40 0.60 0.80 1.00 1.20

(p.

u.)

Vdc at offshore terminal (P-P)

-1.00

-0.50

0.00

0.50

1.00

(p.

u.)

Idc (offshore->onshore)

VPCC-T1

VDC-T1

IDC-T1

IAC-T1

VAC-T2

VDC-T2

IDC-T2

IAC-T2


Half-bridge DC faults performance


• Sustained DC faults (unlike LCC)

• Most systems (except one) use cables: • No need for fast re-energization• Cables experience low occurrence of faults• Fault clearing by opening AC breaker

Applies to conventional 2-Level VSC andHalf-bridge MMC




• Most systems use cables: • No need for fast re-energization• Cables experience low occurrence of faults• Fault clearing by opening AC breaker


DC faults in VSC systems with Overhead Lines (OHL)• High fault event frequency with OHL• Need fast re-energization (re-closing) (400-500 ms) to prevent

AC system movement• DC breakers are required in order to achieve fast re-

energization of DC system


DC Breaker


DC-Breakers


Low voltagePE switch

Fastdisconnect

High voltagePE switch

1. Overcurrent or DC fault under voltage front detected


DC-Breakers



Fastdisconnect



2. De-block HV PE switch


DC-Breakers



Fastdisconnect




3. Open LV PE switch


DC-Breakers



Fastdisconnect





4. Current transferred to HV PE switch


DC-Breakers



Fastdisconnect






5. Open fast disconnect


DC-Breakers



Fastdisconnect







6. Open HV PE switch


DC-Breakers



Fastdisconnect







6. Open HV PE switch

7. DC current extinguished & energy dissipated in arresters


Fault clearance in H-bridge VSC systems (by blocking)


0 2

0 • Therefore lac=0 after blocking since

dcAC VmVpkLL

3

dcc Vv dcdc VVm 23


Simulation of DC faults in a two-terminal system


System description

• T1: P control• T2: Vdc control• T1 & T2 in Vac control

34.1 [m]

15.5 [m]

C1 C2

Conductors: chukar

Tower: DC12

0 [m]

G1

12.7 [m]

.4572 [m]

Ground_Wires: 1/2_HighStrengthSteel

TL Freq. dependent model




DC Faults applied

• At close and remote terminals• Middle of the line• Low impedance faults (0.1 ohm)

DC Faults detection• Valve overcurrent (2.7 kA level)• DC voltage drop (40% of diode rectifier voltage




Converter 1

x 1.960 1.980 2.000 2.020 2.040 2.060 2.080 2.100

-1.3k-1.0k-0.8k-0.5k-0.3k0.0 0.3k0.5k0.8k

(kV

)

Edc1

-10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0

10.0

(kA

)

Idc 1->2

-300

-200

-100

0

100

200

300

(kV

)

Phase voltages T1

-10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0

10.0

(kA

)

Iac T1

Converter 2

x 1.960 1.980 2.000 2.020 2.040 2.060 2.080 2.100

-1.3k-1.0k-0.8k-0.5k-0.3k0.0 0.3k0.5k0.8k

(kV

)

Edc2

-10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5

10.0

(kA

)

Idc 2->1

-300

-200

-100

0

100

200

300

(kV

)

Phase voltages T2

-10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0

10.0

(kA

)

Iac T2

• The total time to restore 90% power was 450ms

• Including 200 ms de-ionization time

Main : Graphs

x 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.00 2.45 0.45

-0.4k-0.2k0.0 0.2k0.4k0.6k0.8k1.0k1.2k

(M

W)

0.9004k 0.8044k -0.0959k

Min -0.0108k Max 0.9006k

P1 (-) P2

Edc1 Edc2

Idc 12 Idc 21

Vac T1 Vac T2

Iac T1 Iac T2

0.0 0.0


Three-terminal system:Demonstration setup


• Starting with the two-terminal system from CIGRE B4-57• If time allows


Questions


• Please e-mail PSCAD Support at

[email protected]

webinar: mmc- technologies - pscad...2. dq decoupled vector current control 3. half and h-bridge...

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