HINDUSTHAN COLLEGE OF ARTS AND SCIENCE

COIMBATOREDEPARTMENT OF ELECTRONICS AND COMMUNICATION SYSTEMS

STUDY MATERIAL

SUBJECT : DIGITAL PRINCIPLES AND APPLICATIONSCLASS : II – B. Sc ELECTRONICS AND COMMUNICATION SYSTEMSSEMESTER : IVUNIT : I (NUMBER SYSTEM AND CODES)STAFF : S.SATHYADEEPA M.Sc., M. Phil.,ME

SYLLABUS: Decimal, binary, octal and hexadecimal numbers – conversion – floating point representation – binary addition – subtraction – multiplication – one’s and two’s complements – BCD – weighted codes and non-weighted codes - excess three – gray code –error detection codes – hamming codes – ASCII – EBCDIC – Hollerith codes – parity advantages.

NUMBER SYSTEM:

In general, decimal no.s are from 0-9, its base is 10.Binary no.s are 0,1 , its base is 2.Octal no.s are from 0-7, its base is 8.Hexadecimal no.s are from 0-F, its base is 16.

BINARY TO DECIMAL:Binary numbers are represented by the combinations of 0’s and 1’s. The base for a binary

number is 2. A binary number is called “a bit”(may be 0 or 1).Normally a binary number can be converted into decimal format by using the following method:For example: convert (111)2 into decimal.

1 1 1

1 x 20 = 1 1x21 = 2 1x22 = 4

________ (7)10

_________

Example : convert (7)10 into binary:

For fractions: convert binary (10.10)2 into decimal:

Convert decimal (2.5)10 into binary:

Note: if all binary digits are ‘1’ , then use formula asDecimal = 2n-1Ex: if no. of bits, n = 4 Then 24-1 = 16-1 = 15(ie) (15)10 = (1111)2

OCTAL TO DECIMAL:Ex: convert octal no. (25)8 into decimal:

Ex: convert decimal no. (21)10 into octal:

Fractions: Ex: convert decimal (21.23)10 into octal:

OCTAL TO BINARY:EX: convert octal (23)8 into binary:

BINARY TO OCTAL:EX: convert (1011.01101)2 into octal:

Note: Ex: convert (011.111 000 110)2 into octal:

HEXADECIMAL INTO BINARY:Ex: convert (9AF)16 into binary:

Ex: convert (1000 1100)2 into hex:

HEXA TO DECIMAL:Ex: convert (2A)16 into decimal:

Ex: convert (42)10 into hexadecimal:

BINARY ADDITION:The basic rule for binary addition is:0+0=00+1=11+0=11+1=10

Ex: perform binary addition of (11100)2 and (11010)2

Ex: add 57H and 35H

BINARY SUBTRACTION:The basic rule for binary sub is:0-0=00-1=11-0=11-1=0

Ex: subtract (1010)2 from (1101)2

Ex: subtract (200)10 – (125)10

BINARY MULTIPLICATION:

Ex: multiply 101 and 10

1 0 1X 1 0

0 0 0 1 0 1__

1 0 1 0UNSIGNED BINARY NUMBERS:

To find a number is positive or negative, avoid + or – signs and use the magnitude(absolute value).That is, absolute value of the numbers.Ex: 0000 0000 is the smallest 8 bit number.

1111 1111 is the largest 8 bit no.It does not create any problem until the carry overflows.

Ex: consider a 8 bit memory. That is, ranging from (0-255)10

Ex: add : (150)10 and (85)10

Another ex:This is for overflowing of carry, add (175)10 and (118)10

SIGN MAGNITUDE NUMBERS:

Ex: negative no.s are -1, -2, -3,………Here 1,2,3 are magnitudes and sign is negative.Consider 0 for +sign and 1 for – sign. for -1 it is -001, but if I use 0 or 1 for sign, then it is represented as 1001 for -001.For 8 bit range, if unsigned is used, then range is 0-255. But if signed is used, msb is used for sign representation . so range is reduced to -127 to 0 to +127(totally 255) Ex: for 8 bit no.s, -ve no.s are: -1 = 1000 0001 to -127=1111 1111 and +ve no.s are from +1=0000 0001 to +127=0111 1111

1’s COMPLEMENT AND 2’s COMPLEMENT:

One’s complement: if a binary no. is given, then one’s comp of that no. is just the inverted value of each bits.EX: Find one’s complement of 0101.Ans: 1010

Two’s complement: if a binary no. is given , then two’s comp of that no. is just one’s complement + 1.Ex: Find two’s complement of 0101.Ans: one’s comp of 0101 is 1010. Add 1 with 1010 to get it’s two’s complement.That is, 1010

+1 1011

ONE’S COMPLEMENT SUBTRACTION:2 CASES: 1. Subtraction of smaller no. from larger no.

2. subtraction of larger no. from smaller no.

Case 1 methodology:1. Determine the one’s complement of the smaller no.2. Add the one’s comp to the larger no.3. Remove the carry and add it to the result. This is called end around carry.

Case 2 methodology:1. Determine the one’s complement of the larger no.2. Add the one’s comp to the smaller no.3. Answer is in one’s comp form. To get the real ans. In true form take one’s comp to the result

and assign negative sign to the final answer.

TWO’S COMPLEMENT SUBTRACTION:2 CASES: 1. Subtraction of smaller no. from larger no.

2. subtraction of larger no. from smaller no.

Case 1 methodology:1. Determine the Two’s complement of the smaller no.2. Add the two’s comp to the larger no.3. Discard the carry.

Case 2 methodology:1. Determine the two’s complement of the larger no.2. Add the two’s comp to the smaller no.3. Answer is in two’s comp form. To get the real ans. In true form take two’s comp to the

result and assign negative sign to the final answer.

WEIGHTED CODES:Ex: 8421, 2421 and 5211 are all examples of weighted codes.

Note: 8421 code is normally called as BCD(binary coded decimal) code. Each bit of the code will be having a certain weightage and so it is caaled as weighted code.

Decimal digit BCD CODE8 4 2 1

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 14 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 09 1 0 0 1

EX: BCD CODE 9 – 1001Weight of lsb(1) is 1.

Weight of 0 is 2.Weight of 0 is 4.Weight of msb(1) is 8.

Ex: for (58)10 , find bcd.5 8

0101 1000Bcd of 58 is 0101 1000

Note: 8421 bcd code needs 8 bits to encode 58, but when we represent the same no. in binary, it needs only 6 bitys . so, bcd is less effi ciency. The only advantage of bcd is converting the nos into binary is easy.Another problem is generating the arithmethic circuits.

9’s AND 10’S COMPLEMENT :EX: 9’S Comp of 2 is 9-2 is7.10’s comp is 9’s comp +1 . that is , ex: 10’s of 2 is 8.

NON-WEIGHTED CODES:The code not having any weight is called non-weighted code.Ex: excess-3 and gray codes.

EXCESS-3 CODE:It’s a modified form of a bcd no. if a bcd no is given, add 3 to each digits of that no. to form the excess code.Note:For bcd subtraction, we need to implement 9’s comp or 10’s comp method. In excess3 code, we get 9’s comp of a no. by just complementing each bit. Due to this, excess3 code is called self complementing code.

Excess3 addition:Method:

1. Add 2 excess3 numbers.2. If carry is 1, add 3 to the sum of 2 digits.3. If carry is 0, subtract 3 from the sum.

Excess 3 subtraction:1. Complement the subtrahend.2. Add complemented subtrahend to the minuend.3. If carry is 1, result is +ve. Addd 3 and end around carry.4. If carry is 0, result is –ve. Subtract 3.

GRAY CODE;It is a special case of the unit-distance code. That is, in unit distance code, bit patterns for 2

consecutive no.s differ in only one position. These codes are also called cyclic codes.For gray code, any 2 adjacent code groups differ only in one bit position, gray code is also called

as reflected code.Note that the 2 lsb bits from 4 to 7 are the mirror images of 0 to 3. Similarly, the 3 lsb bits for 8

to 15 are the mirror images of 0 to 7.In general, the n lsb bits for 2n through 2 n+1 – 1 are the mirror images of those for 0 through

2n-1.

Ad vantages:Since only one bit position differs all the time, errors can be easily reducedAlso, no of bits can be reduced for bit representation. So no. of flip flops can be reduced.

GRAY TO BINARY:1. MSB of the binary number is the same as the msb of the gary code no.2. To gert next bin digit, xor done between the bit just written down and next gray code bit.3. Repeat step2 until all garay code bits have bbeen xor-ed with binary bits.

ASCII CODE:CALLED AS AMERICAN STANDARD CODE FOR INFROMATION INTERCHANGEIt is a 7 bit code. Consists of both numbers and alphabetic characters called alphanumeric codes. Here the decimal digits are represented by the bcd code preceded by 011. Other than decimal digits, there are letters and symbols which are represented by other code combinations.

EBCDIC CODE:Called Extended Binary Coded Decimal Interchange Code.It’s a 8 bit code. Here the decimal digits are represented by the bcd code preceded by 1111.

HOLLERITH CODE:Herman Hollerith developed this code to feed information into the digital computer using punched cards. The code used in the system to represent alphanumeric information is called Hollerith code.It consists of 80 columns and 12 rows. Each column represents an alphanumeric charcter with holes in the appropriate rows.A hole is sensed as 1 and absence of the hole is 0 by the circuit in the card reader.It is a 12 bit code.First 3 rows called as zone punch rowsOther 9 rows are numeric puch rows.Note:Numbers are represented in the column by a single punch.Alphabets are represented in the column by 2 punches.Ex:Letter ‘A’ has got 2 punches like 12-1 punch, that is punch in row 1 and 12 and number ‘0’ has got single punch like 0 punch.

ERROR DETECTING AND CORRECTING CODE:During transmission and reception of data through any medium, error may occur due to noise, so that 0 turns to 1 and 1 turns to 0.To correct this, we need to detect the error first by using some methods. For ex, add one or two bits along with the actual data during txn, so that data integrity can be maintained between tx and rx.The code which allows only error detection is called error detection code.The code which allows both error detection and correction is called error detecting and correcting code.

PARITY BIT:A parity bit is used for detecting errors during txn of binary information.It is an extra bit sent along with the binary data to make the no. of 1’s either odd or even.The rx checks the message, it checks the parity whether it is odd or even. If it matches then no error else error.The circuit used to generate the parity bit is called parity generator and ciruit used to check the parity bit si called parity checker.

EVEN PARITY;The added parity bit if makes the total no. of 1’s an even amount, then it is even parity else odd parity.

BLOCKK PARITY:Parity can be assigned to the binary data in rows and columsns. Block means huge data word.

HAMMING CODE:It provides detection of error and identifies error in which bit position, so called error detection and correction codes.This code uses a no. of parity bits(dependent on the no. o f bits) located at certain positions in the code group.Number of parity bits:Number of parity bits depends upon the no. of information bits.2p > x+p+1 is the formula used. Where x is no. of inf bits and p is no. of parity bits.This calculation is used for single error detection and correction.Locations of the parity bits in the code:Parity bits should be included with the inf bits correspondeing to the ascending powers of 2.Assigning values to the parity bits.:Refer notes given in the class.

ARITHMETIC CIRCUITS:

By combining logic gates in the right way, we can build circuits that add and subtract. Since these circuits are electronic, they are fast.

Binary Addition:

The four most basic cases of binary addition:

0 + 0 = 0 1 + 0 = 1 0 + 1 = 1 1 + 1 = 10

Large Binary Numbers:

Column-by-column addition applies to binary as well as decimal numbers. For example suppose to add 1 1 1 0 0+ 1 1 0 1 0 ------------- ?Start by adding the least-significant column to get 1 1 1 0 0+ 1 1 0 1 0 ------------- 0Next, add the bits in the second column and so on we get the final answer as 1 1 1 0 0+ 1 1 0 1 0---------------- 1 1 0 1 1 0----------------8-bit Arithmetic:

In first generation microcomputers addition is done on two 8-bit numbers such as A7 A6 A5 A4 A3 A2 A1 A0

+ B7 B6 B5 B4 B3 B2 B1 B0

------------------------------------------ ?

The most-significant bit (MSB) of each number is on the left, and the least-significant bit (LSB) is on the right. For the first number, A7 is the MSB and A0 is the LSB. For the second number, B7 is the MSB and B0 is the LSB. Add these 8-bit numbers; 0101 0111 and 0011 0101. If you add the bits in each column we get the answer as

0101 0111

+ 0011 0101

--------------

1000 1100

---------------

Binary Subtraction:

The four basic cases of binary subtraction:

0 – 0 = 0 1 – 0 = 1 1 – 1 = 0 10 – 1 = 1

For larger binary numbers, subtract column by column, the same as you do with decimal numbers. This means that you sometimes have to borrow from the next-higher column.

Subtract two numbers 1100 1000 and 0111 1101

1100 1000

- 0111 1101-------------

0100 1011

--------------

UNSIGNED BINARY NUMBERS: Data of the foregoing type is called unsigned binary when all of the bits in a binary are

used to represent the magnitude of the corresponding decimal number. With 8-bit unsigned arithmetic, all magnitudes must be between 0 and 255. Therefore, each number being added or subtracted must be between 0 and 255. Also, the answer must fall in the range of 0 to 255.In eight bit arithmetic, addition of two unsigned numbers whose sum is greater than 255 causes an overflow, a carry into the ninth column. If a carry into the ninth column that the 8-bit answer is invalid.SIGN-MAGNITUDE NUMBERS:

Everything has to be coded as strings of 0s and 1s, the + and – signs also have to be represented in binary form. 0 is used for the + sign and 1 for the – sign. There –001, -010 and –011 are coded as 1001, 1010 and 1011. The foregoing numbers contain a sign bit followed by magnitude bits. Numbers in this form are called sign-magnitude numbers. The MSB always represents the sign, and the remaining bits always stand for the magnitude. The range of sign-magnitude numbers are from –127 to +127. The main advantage of sign-magnitude numbers is their simplicity. Negative numbers are identical to positive numbers, except for the sign bit. 2’s COMPLEMENT REPRESENTATION: 1’s complement:

The 1’s complement of a binary number is the number that results when we complement each bit. For example 1’s complement of 1010 is 01012’s complement:

The 2’s complement is the binary number that results when we add 1 to the 1’s complement. 2’s complement = 1’s complement + 1 for example 2’s complement of 1011 is 1011 = 0100 (1s complement) 0100 + 1 = 0101 (2s complement)2’s COMPLEMENT ARITHMETIC:Addition:

When we add two binary numbers there are four possible cases:CASE 1: Both numbers are positive eg ., + 83 and +16CASE 2: Positive and smaller negative number eg., +125 and -68CASE 3: Positive and larger negative number eg., +37 and -115CASE 4: Both the numbers are negative eg., -43 and –78

Subtraction: The format for subtraction is Minuend – Subtrahend = Difference. There are four cases:

CASE 1: Both numbers are positiveCASE 2: Positive and smaller negative numberCASE 3: Positive and larger negative numberCASE 4: Both the numbers are negative

If we take the 2s complement of the subtrahend , addition of the complemented subtrahend with the minuend gives the correct answer. 4. HALF ADDER:

When we add two binary numbers, we start with the least significant column. This means that we have to add two bits with the possibility of a carry. The circuit used for this is called a half adder. The figure below shows how to build a half adder. The output of the exclusive-OR gate is called the SUM, while the output of the AND gate is the CARRY.

HALF ADDER CIRCUIT A

CARRY=AB

B

SUM=A’B +AB’

HALF-ADDER TRUTH TABLE

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

The AND gate produces a high output only when both inputs are high. The exclusive-OR gate produces a high output if either input is 1; otherwise the output is low.

First Entry:

Input A=0 and B=0. Human response: 0 plus 0 is 0 with a carry of 0.

Half-adder response: SUM=0 and CARRY=0

Second Entry:

Input A=0 and B=1. Human response: 0 plus 1 is 1 with a carry of 0. Half-adder response: SUM =1 and CARRY =0

Third Entry:

Input A=1 and B=0. Human response: 1 plus 0 is 1 with a carry of 0. Half-adder response: SUM=1 and CARRY=0.

Fourth Entry:

Input A=1 and B=1. Human response: 1 plus 1 is 0 with a carry of 1. Half-adder response: SUM=0 and CARRY=1.

FULL-ADDER: For the higher-order columns, we have to use a full-adder, a logic circuit that can add 3

bits at a time. The third bit is the carry from a lower column. This implies that we need a logic circuit with three inputs and two outputs, similar to the full adder shown

FULL-ADDER CIRCUIT: A B C

CARRY

SUM

FULL-ADDER LOGIC DIAGRAM

A B CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

A

SUM

B

C CARRY

FULL ADDER TRUTH TABLE

First Entry:

Input A=0, B=0 and C=0. Full adder Response: SUM=0 and CARRY=0

Second Entry:

Input A=0, B=0 and C=1. Full adder Response: SUM=1 and CARRY=0

Third Entry:

Input A=0, B=1 and C=0. Full adder Response: SUM=1 and CARRY=0

Fourth Entry:

Input A=0, B=1 and C=1. Full adder Response: SUM=0 and CARRY=1

Fifth Entry:

Input A=1, B=0 and C=0. Full adder Response: SUM=1 and CARRY=0

Sixth Entry:

Input A=1,B=0 and C=1. Full adder Response: SUM=0 and CARRY=1

Seventh Entry:

Input A=1, B=1 and C=0. Full adder Response: SUM=0 and CARRY=1

Eighth Entry: Input A=1,B=1 and C=1.Full adder Response: SUM=1 and CARRY=1

The full adder has inputs A and B, plus a third input C, usually called the CARRY IN because it comes from a lower-order column. There are two outputs SUM and

A B C CARRY SUM

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

CARRY. The output CARRY is called the CARRY OUT because it goes to the next higher column.

5. HALF SUBTRACTOR: SUBTRACTORS:

The subtraction of the two binary numbers may be accomplished by taking the complement(negative)of the subtrahend and adding it to the minuend. By this method, subtraction operation becomes an addition operation. By this each subtrahend bit of the number is subtracted from its corresponding significant minuend bit to form a difference bit. If the minuend bit is smaller than the subtrahend bit, a 1 is borrowed from the next significant position. A 1 has been borrowed is conveyed to the next higher pair of bits by means of a binary signal output of a given stage and going into the next higher stage.

A half subtractor is a combinational circuit that subtracts two bits and produces their difference. It also has an output to specify if a 1 has been borrowed. Let the minuend bit be X and the subtrahend be Y. To perform X-Y, we have to check the relative magnitude of X and Y. If X>=Y we have three possibilities.

1) 0 – 0 = 0 2) 1 – 0 = 1 3) 1 – 1 = 0

Their difference is called the difference bit, denoted by D. If X<Y, we have 0-1 and it is necessary to borrow a 1 from the next higher stage. The 1 borrowed from the next higher stage adds 2 to the minuend bit. With the minuend equal to 2 the difference now being

2-1 = 1. The half subtractor has two outputs the difference and the borrow, designated by D and B respectively. The borrow informs the next higher stage that a 1 has been borrowed.

TRUTH TABLE:

X Y B D

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

The output borrow B is a 0 as long as X>=Y. It is a 1 for X=0 and Y=1. The D output is the result of the arithmetic operation 2B+X-Y. The Boolean functions for the 2 outputs of the half-subtractor are derived directly from the truth table.

The Boolean expression is

D = X’Y + XY’ = XY

B = X’Y

X

B=X’Y

Y

D=XY

The ADDER-SUBTRACTOR: We can connect full adders to add or subtract binary numbers. The circuit is laid out from

the right to left, similar to the way we add binary numbers. Therefore, the least-significant column is on the right, and the most significant column is on the left. The boxes labeled FA are full adders.(Some adding circuits use a half adder instead of a full adder in the least significant column).

BINARY ADDER-SUBTRACTOR

A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B 2 A1 B1 A0 B0

S7 S6 S5 S4 S3 S2 S1 S0 CARRY

The CARRY OUT from each full adder is the CARRY IN to the next-higher full adder . The numbers being processed are A7 to A0 and B7 to B0, while the answer is S7 to S0. With 8-bit arithmetic, the final carry is ignored for reasons given easier.

ADDITION:Here is how an addition appears: A7 A6 A5 A4 A3 A2 A1 A0

+ B7 B6 B5 B4 B3 B2 B1 B0

------------------------------------------

S7 S6 S5 S4 S3 S2 S1 S0

------------------------------------------

During an addition the SUB signal is deliberately kept in the low state. Therefore, the binary number B7 to B0 passes through the controlled inverter with no change. The full adders then produce the correct output sum. They do this by adding the bits in each column, passing carries to the next higher column and so on. For instance, starting at the LSB(Least Significant Bit), the full-adder adds A0, B0 and SUB. This produces a SUM of S0 and a CARRY OUT to the next-higher full-adder. The next-higher full adder then adds A1,B1 and the CARRY IN to produce S1 and a CARRY OUT. A similar addition occurs for each of the remaining full-adders, and the correct sum appears at the output lines.

For instance, suppose that the numbers being added are +125 and –67. Then

A7 …A0 = 0111 1101 and B7 …B0 = 1011 1101 .This is the problem.

0111 1101

+ 1011 1101

--------------

?

Since SUB=0 during an addition, the CARRY IN to the least significant column is 0.

0 SUB

0111 1101

1011 1101

---------------

?

The first full adder performs this addition 0+1+1=0 with a carry of 1. The CARRY OUT of the first full adder is the CARRY IN to the second full adder.

In a similar way, the remaining full-adders add their 3 input bits until we arrive at the last full adder. When the CARRY IN to the MSB appears, the full-adder produces 1+0+1=0 with a carry of 1. The addition process ends with a final carry.

0111 1101

+ 1011 1101

--------------

1 0011 1010

----------------

During the 8-bit arithmetic, this last carry is ignored as previously discussed, therefore the answer is S7….S0 = 0011 1010 .This answer is equivalent to decimal +58, which is the algebraic sum of the numbers we started with +125 and –67.

SUBTRACTION: Here is how a subtraction appears: A7 A6 A5 A4 A3 A2 A1 A0

- B7 B6 B5 B4 B3 B2 B1 B0

------------------------------------------

S7 S6 S5 S4 S3 S2 S1 S0

------------------------------------------

During a subtraction, the SUB signal is deliberately put into the high state. Therefore, the controlled inverter produces the 1’s complement of B7 …B0. Furthermore, because SUB is the CARRY IN to the first full adder, circuit possesses the data like this A7 A6 A5 A4 A3 A2 A1 A0

- B7’ B6’ B5’ B4’ B3’ B2’ B1’ B0’

------ ------------------------------------------

S7 S6 S5 S4 S3 S2 S1 S0

-------------------------------------------------

When A7…A0 = 0 , the circuit produces the 2’s complement of B7..B0 because 1 is being added to the 1’s complement B7..B0. When A7….A0 does not equal zero, the effect is equivalent to adding A7…A0 and the 2’s complement of B7..B0.

Here is an example of +82 and +17. Then A7..A0 = 0101 0010 and B7..B0=0001 0001

The controlled inverter produces the 1’s complement of B which is 1110 1110. Since SUB = 1 during a subtraction, the circuit performs the following addition:

1 SUB

0101 0010

1110 1110

----------------

10100 0001

For 8-bit arithmetic, the final carry is ignored, as previously discussed, therefore the answer is S7..S0 = 0100 0001. This is equivalent to decimal +65, which is the algebraic difference between the numbers we started with +82 and +17.

SERIAL ADDER/SUBTRACTOR: The design of arithmetic unit depends not only on the representation of negative numbers and also on whether the information is processed in parallel or serial. Serial addition of 2 binary numbers requires only 1 full adder block irrespective of the number of bits in the operands. Comparing this with parallel adders, there is a lot of saving in hardware. But since the n-bit data is handled bit by bit. The time required to execute the arithmetic operations is very high when

compared with parallel adders. The n-bits of the operands are stored in 2n-bit shift registers and the registers are driven by common clock signal. The operands are loaded parallely into the shift registers. The nth-bit output of the registers are connected as input to the full adder circuit. The carry from the full adder is connected to input of the flip-flop and the output of the flip-flop is connected to the carry input of the full-adder. The same clock is used for shifting data in the registers is used for clocking the flip-flop.

SERIAL ADDER/SUBTRACTOR

N bit output

0,1,2,3,…….,n

CLK

Input

Signal

flip

flop

Shift Signal

0,1,2,3,……,n

Register A and B contains operand A and B respectively. The carry from the previous addition is available at output of the flip-flop along with the next bits of the operands at the input of the full adder. Hence the operand bits get added with the carry from the previous addition and shifts the sum bit back to the shift registers. The subtraction can be performed as addition in which case the operands are loaded into the shift registers along with their signs.

PARALLEL BINARY ADDER:

A 4-bit parallel binary adder is illustrated below.The purpose of this adder is to add two 4-bit binary integers. The addend inputs are named X0 through X3, and the augend bits are represented by Y0 through Y3. The adder shown does not possess the ability to handle sign bits for the binary words to be added, but only adds the magnitudes of the numbers stored. The additional circuitry needed to

handle sign bits is dependent on whether negative numbers are represented in true magnitude or in the 1’s or 2’s complement systems.

Consider the addition of the following two 4-bit binary numbers;

0 1 1 1 where X3 = 0, X2 = 1, X1 = 1 & X0 = 1

0 0 1 1 where Y3 = 0, Y2 = 0, Y1 = 1 & Y0 = 1

--------------

SUM = 1 0 1 0

----------------

The sum should therefore be S3 = 1, S2 = 0, S1 = 1 & S0 = 0.

The operation of the adder may be checked as follows. Since X0 and Y0 are the least significant digits, they cannot receive a carry from a previous stage. In the problem above, X0 and Y0 are both 1s, their sum is therefore 0, and a carry is generated and added into the full-adder for bits X1 and Y1. Bits X1 and Y1 are also both 1s, as is the carry input to this stage. Therefore, the sum output line S1 carries a 1, and the CARRY line to the next stage also carries a 1. Since X2 is a 1, Y2 is a 0, and the carry input is 1, the sum output line S2 will carry a 0, and the carry to the next stage will be a 1. Both inputs X3 and Y3 are equal to 0, and the CARRY input line to this adder stage is equal to 1. Therefore, the sum output line S3 will represent a 1, and the CARRY output line, designated as ‘overflow” in the below figure will have a 0 output.

The same configuration may be extended to any number of bits. A 7-bit adder may be extended to any number of bits. A 7-bit adder may be constructed by using 7 full-adders, and a 20-bit adder by using 20 full-adders.

The OVERFLOW line could be used to enable the 4-bit adder in the below figure to have a 5-bit output. This is not generally done, however, because the addend and augend both come from storage, and so their length is the length of the basic computer word, and a longer word cannot be readily stored by the machine. The machine with a word length of n bits (consisting of sign bit and n-1 bits to designate the magnitude) could express binary numbers –2n+1 to 2n-1 –1. A number within these limits is called representable . Since the simple 4-bit adder in the below figure has no sign bit, it can represent only binary integers from 0 to 15.

PARALLEL ADDER

INPUTS

X3 Y3 X2 Y2 X1 Y1 X0 Y0

S3 S2 S1 S0

If 1100 and 1100 are added in the adder illustrated there will be a 1 output on the OVERFLOW line because the sum of these two numbers is 11000. This number is 24 decimal and cannot be represented in this system. Such a number is referred to as non representable for this particular very small register. When two integers are added such that their sum is nonrepresentable (that is, contains too many bits), then we say the sum overflows, or an overflow occurs and a 1 on the CARRY line for the full adder connected to the most significant digits indicates this. The AND gates connected to the S output lines from the four adders are used to gate the sum into the correct register.

BINARY – CODED –DECIMAL ADDER OR 8421 ADDER: Arithmetic units which perform operations on numbers stored in BCD form must have the ability to add 4-bit representation of decimal digits. To do this, a BCD adder is used. A block diagram symbol for an adder is shown below.

The adder has as an augend digit input consisting of 4 lines, an addend digit input of 4 lines, a carry- in and a carry-out and a sum digit with four output lines. The augend digit, addend digit and sum digit are each represented in 8,4,2,1 BCD form. The purpose of the BCD adder is to add the augend and addend digits and the carry-in and produce a sum-digit and carry-out.

BCD ADDER

A8 A4 A2 A1 B8 B4 B2 B1

Carry In

K 4 – bit binary adder

Z8 Z4 Z2 Z1Carry Out

S8 S4 S2 S1

There are eight inputs to the BCD adder, four Ai or augend, inputs and four Bi

or addend digits. Each input will represent a 0 or a 1 during a given addition. If 3 (0011) is to be added to 2 (0010) then A8=0, A4=0, A2=1, A1=1 and B8=0, B4=0, B2=1, B1=0. The operands A and B are represented with 4-bit 8421 codes. The basic adder consists of 4 binary adders at the top and some provision must be made to 1) generate carries and

2) correct sums greater than 9. For instance if 310 (0011) is added to 810 (1000), the result should be 110 (0001) with a carry generated.

Example 810 = 1000

310 = 0011 ----------

1110 =1011 610 = 0110

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1110 =10001

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4- bit binary adder

Output Carry

0

For constructing the BCD adder 2, 4-bit binary adders, 2 AND gates, 1 OR gate is used. If the sum is greater than 9, the AND-OR network is enabled to add 0110(6) with A +B to get the correct sum.