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Intel® 2015

SKYLAKE RVP/SDS

System Test Validation Test PlanPC Client Group (PCCG) System Test & Validation (PSTV)

7th Mar 2014

Revision 0.3

Intel Confidential 1 Skylake RVP Platform Validation Test Plan

Copyright & Disclaimer

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Copyright © 2013, Intel Corporation. All rights reserved.

Intel Confidential 2 Skylake RVP/SDS System Test Validation Test Plan

Contents1 Introduction.................................................................................................... 7

1.1 Purpose, Objective and Intended Audience.........................................................71.2 Terminologies.......................................................................................................71.3 Reference Documents..........................................................................................91.4 Stakeholders/ Content Reviewers........................................................................9

2 Product Architecture.................................................................................112.1 Platform Architecture.........................................................................................11

2.1.1 Skylake Y Detachable Platform (All I/O Possibilities).......................................122.1.2 2.1.2 Skylake-U Clamshell/Convertible Platform.............................................122.1.3 2.1.3 Skylake H AIO Platform Architecture......................................................132.1.4 2.1.4 Skylake H 2-Chip BGA Platform Architecture..........................................142.1.5 2.1.5 Skylake Y SDS Detachable Platform........................................................152.1.6 2.1.6 Skylake PMF features.............................................................................17

3 Program Schedule....................................................................................... 19

4 Test Scope...................................................................................................... 214.1 Validation Overview...........................................................................................214.2 System Validation Scope....................................................................................21

5 Test Strategy and Schedule......................................................................235.1 Test Strategy......................................................................................................23

5.1.1 Test Coverage Approach.................................................................................235.1.2 Test Groups and Focus Areas..........................................................................24

5.2 Automation Strategy..........................................................................................255.3 User Experience Verification..............................................................................25

5.3.1 Platform KPIs...................................................................................................285.3.2 Validation Execution Configurations...............................................................30

5.4 High level milestone strategy & execution schedule..........................................32

6 Platform Validation Process....................................................................346.1 Platform CI and BKC Process..............................................................................346.2 Platform Validation Criteria and Guidance.........................................................37

6.2.1 CI Entry Criteria...............................................................................................376.2.2 BKC Entry Criteria............................................................................................376.2.3 BKC Submission Criteria..................................................................................386.2.4 Bi-weekly BKC Exit Criteria..............................................................................386.2.5 Milestone BKC Exit Criteria..............................................................................386.2.6 Sighting Process...............................................................................................406.2.7 High Speed Database (HSD) Block Diagram.....................................................406.2.8 [email protected] of Ingredient HSD...........................................426.2.9 Platform Test Overview...................................................................................436.2.10 Connectivity....................................................................................................436.2.11 Overview.........................................................................................................436.2.12 Intel WiFi/ BT Solution.....................................................................................436.2.13 Indoor Location Based Services.......................................................................446.2.14 Wireless WAN (3G / LTE).................................................................................446.2.15 Global Navigation Satellite System (GNSS)......................................................456.2.16 NFC..................................................................................................................456.2.17 WiGiG/ WiDock...............................................................................................45


6.2.18 Graphics, Multimedia, and Imaging.................................................................466.2.19 Overview.........................................................................................................466.2.20 Feature List......................................................................................................476.2.21 Storage............................................................................................................496.2.22 Overview.........................................................................................................496.2.23 Feature List......................................................................................................496.2.24 Thermal...........................................................................................................506.2.25 Overview.........................................................................................................506.2.26 Feature List......................................................................................................516.2.27 Cycling.............................................................................................................526.2.28 Overview.........................................................................................................526.2.29 Feature List......................................................................................................526.2.30 Responsiveness...............................................................................................536.2.31 Overview.........................................................................................................536.2.32 Feature List......................................................................................................53

Figures

Figure 6-1. High Speed Database (HSD) Block Diagram..................................................................41

Tables

Table 1-1. Terminologies..................................................................................................................7Table 1-2. Reference Documents.....................................................................................................9Table 4-3. Term Descriptions - HSD Block Diagram........................................................................42Table 4-4. Connectivity Features....................................................................................................45Table 4-5. Graphics, Multimedia, and WiDi Features.....................................................................46Table 4-9. Storage Features...........................................................................................................49Table 4-10. Thermal Features........................................................................................................51Table 4-15. Cycling Features..........................................................................................................52Table 4-19. Responsiveness Features............................................................................................53


Revision Taxonomy


Revision History

Document Number

Revision

Number

Reason for Changes Revision Date

0.3 Base Document Feb 6th 2014

0.4 Mar 7th 2014


1Introduction

This System Validation Test Plan document details the overall system validation strategy, methodology, scope, and process flow adopted for the validation of Intel® Skylake Client Platforms (RVP/SDS). Various test areas and validation strategies for the detailed test plan are also outlined in the document.

1.1 Purpose, Objective and Intended Audience

The document describes the approaches to System Test planning and Execution strategy for the Intel® Client Skylake RVP/SDS ULT/ULX/DT/Halo Programs. The intended audience includes Validation Architects, SW Architects, Validation Engineers and Program Stake holders like PVST/PSXT/SW QRC team

This document also describes requirements and customer commitments as known today. The current document will be updated as new product requirements or information becomes available and also if the test approach needs update or the existing document no longer meets the purpose. Descriptions of product functionality reside in other documents but may be provided in this document as an example to aid the reader.

This document only describes the test approaches and high level testing scenarios. The actual detailed test cases reside in the Contour Requirement Management tool

1.2 Terminologies

Term

Definition

ACPI ACPI (Advanced Configuration and Power Interface) is an open industry specification co-developed by Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba.

ADB Intel® Automatic Display Brightness

ALS Ambient Light Sensor

AOAC Always On Always Connected (AOAC is now called iSCT - Intel Smart Connect Technology)

BIOS Basic Input / Output System

BLC Back Light Control

BT Bluetooth

CS Connected Standby operation mode

CPPC Collaborative Processor Performance Control

CPPM Converged Platform Power Management

CPU Central Processing Unit

CUI Common User Interface

DPTF Dynamic Platform Thermal Framework


able 1-1.

Terminologies

https://vmsconprdweb01.amr.corp.intel.com/contour/perspective.req

Term

Definition

DPPE Device Power Policy Engine

DSx Deep S3/S4/S5

Dx Display Power State

EC Embedded Controller

EFI Extensible Firmware Interface (i.e., Tiano BIOS mechanism for adding features)

FFS Fast Flash Standby

GNSS Global Navigation Satellite System

GPIO General Purpose IO – IO control for device management within the system

GPS Global Positioning System

HD High Definition

HDD Hard Disk Drive

HID Human Interface Device (keyboard or mouse)

Intel® DRRS Intel® Display Refresh Rate Switching Technology

Intel® GPMT Intel® Graphics Power Modulation Technology

Intel® GRST Intel® Graphics Render Standby Technology

ID Industrial Design

IPT Intel Identity Protection Technology

ISV Independent Software Vendor

iSCT Intel Smart Connect Technology

KSC Keyboard Scan Controller

LCD Liquid Crystal Display

LFP Local Flat Panel

LED Light Emitting Diode

NFC Near field communication

M.2 Next Gen Form Factor Adaptor

OEM Original Equipment Manufacturer

OS Operating System

OTP One Time Password

PEP Power Engine Plug-In

PMIC Power Management Integrated Circuit

RFID Radio Frequency Identification

RST Rapid Storage Technology


able 1-1.

Terminologies

able 1-1.

Terminologies

Term

Definition

SBIOS System BIOS

SDK Software Development Kit

SSD Solid State Disk, eg: Flash memory configured to look like an HDD (has an IDE interface).

Sx Sleep State

TPM Trusted Platform Module (http://www.trustedcomputinggroup.org/)VBIOS Video BIOS

VPB Virtual Power Button


able 1-1.

Terminologies

able 1-1.

Terminologies

http://www.trustedcomputinggroup.org/

1.3 Reference Documents

Table 1-2. Reference Documents

Document Title Revision Revision Date Author

SKL SW SAS Ver 0.5 Kuo, Chia-hung S

SKL Graphics PRD Ver 0.5 Feb 2014

SKL SW BOM V0.54 Kuo, Chia-hung S

SKL SDS PRD V0.71 Kolinski, Jerzy

SKL Platform Use Cases Frumkin Igor & Segev Gil

SKL Platform LZ V0.9.46 Mehta Milan

SKL DT AIO LZ Doshi, Ashesh

1.4 Stakeholders/ Content Reviewers

Table 1-3. Stakeholders/ Content Reviewers

Name Role Organization Status Date

Nguyen, Trung PSTV Manager PSTV

Mukesh Kothari S Engineering Manager PSTV

Aruna Kaleeswaran Engineering Manager PSTV

Frumkin, Igor PVST PCPO

Gopalakrishnan, Divya PVST SVG

Segev, Gil PXST PCPO

Kadgi, Vijaykumar B Platform Architect

Kuo, Chia-hung S SW Architect CSS

Cheng, Anton Performance Architect CSS

Deepa Mehta PnP Lead AEA

Soe Soethiha Power Architect AEA

Ashraf Osman UX verification Architect PSTV

Mark Laser CNL System Validation Architect PSTV

Ueno, Akira SKL System Validation Architect PSTV

Kolinski, Jerzy SKL SDS Architect

Hildick, Thomas K SKL SDS System Engineer

Cefal, Andrzej SKL SDS Val. Lead

Raj, Guru Sub-system Integration

Engineering Manager

WPT

Walker, Mark R Media Architect WPT


https://sharepoint.amr.ith.intel.com/sites/UPHSP/Skylake%20Platform%20PPT/_layouts/xlviewer.aspx?id=/sites/UPHSP/Skylake%20Platform%20PPT/Document%20Library1/1/SKL%20DT-AIO%20Landing%20Zone%20v1.8.xlsx&Source=https%3A%2F%2Fsharepoint.amr.ith.intel.com%2Fsites%2FUPHSP%2FSkylake%2520Platform%2520PPT%2Fdefault.aspx&DefaultItemOpen=1&DefaultItemOpen=1

https://sharepoint.amr.ith.intel.com/sites/UPHSP/Skylake%20Platform%20PPT/_layouts/xlviewer.aspx?id=/sites/UPHSP/Skylake%20Platform%20PPT/SKL%20Platform%20LZ/1/SKL_Windows%20Platform_LZ_v0.9_46.xlsx&Source=https%3A%2F%2Fsharepoint.amr.ith.intel.com%2Fsites%2FUPHSP%2FSkylake%2520Platform%2520PPT%2Fdefault.aspx%3FPageView%3DShared%26InitialTabId%3DRibbon.WebPartPage%26VisibilityContext%3DWSSWebPartPage&DefaultItemOpen=1&DefaultItemOpen=1

https://sharepoint.amr.ith.intel.com/sites/PCPO/SKL%20Platform/_layouts/xlviewer.aspx?id=/sites/PCPO/SKL%20Platform/SKL%20Platform%20Dashboard/Use%20Cases/SKL%20Platform%20Use%20Cases%20ww01'14%20.xlsx&Source=https%3A%2F%2Fsharepoint.amr.ith.intel.com%2Fsites%2FPCPO%2FSKL%2520Platform%2FSitePages%2FHome.aspx%3FRootFolder%3D%252Fsites%252FPCPO%252FSKL%2520Platform%252FSKL%2520Platform%2520Dashboard%252FUse%2520Cases%26FolderCTID%3D0x012000F67670BAFEF962428784B85AA5BE8542%26View%3D%7BF4571D7A-71F9-4A6E-B309-DED6EE9155F2%7D&DefaultItemOpen=1&DefaultItemOpen=1

https://sharepoint.amr.ith.intel.com/sites/2015_SDS/SKL_SDS_detachable/Shared%20Documents/SKL%20SDS%20PRD%20specification/SKL%20SDS%20PRD%20rev%200.71.pdf

https://sharepoint.amr.ith.intel.com/sites/2015_SDS/SKL_SDS_detachable/_layouts/xlviewer.aspx?id=/sites/2015_SDS/SKL_SDS_detachable/Shared%20Documents/Software/Skylake-SW-BOM-v0.54.xlsx&Source=https%3A%2F%2Fsharepoint.amr.ith.intel.com%2Fsites%2F2015_SDS%2FSKL_SDS_detachable%2FSitePages%2FHome.aspx%3FRootFolder%3D%252Fsites%252F2015%255FSDS%252FSKL%255FSDS%255Fdetachable%252FShared%2520Documents%252FSoftware%26FolderCTID%3D0x0120002ECE5B8617F5F948BD415806C0C2CA4A%26View%3D%257b3AA6CFAD-7946-47D5-96EC-F10CBB4E98C4%257d&DefaultItemOpen=1&DefaultItemOpen=1

https://sharepoint.amr.ith.intel.com/sites/GCM/SWPO/SkylakePDT/SkylakePDTMWS/_layouts/WordViewer.aspx?id=/sites/GCM/SWPO/SkylakePDT/SkylakePDTMWS/Document%20Library1/1/PRD/Rev%200.5%20Skylake%20w_Android_ww50.docx&Source=https%3A%2F%2Fsharepoint.amr.ith.intel.com%2Fsites%2FGCM%2FSWPO%2FSkylakePDT%2FSkylakePDTMWS%2FDocument%2520Library1%2FForms%2FAllItems.aspx%3FRootFolder%3D%252Fsites%252FGCM%252FSWPO%252FSkylakePDT%252FSkylakePDTMWS%252FDocument%2520Library1%252F1%252FPRD%26FolderCTID%3D0x01200094E3A550A92BAE4DB3482A09829FA4BB%26View%3D%257b5AB5CABB-1A14-4BE6-988D-FEBF657E49F4%257d&DefaultItemOpen=1&DefaultItemOpen=1

Name Role Organization Status Date

Tao, Tao Q Camera Architect WPT

Hudson, Christopher M Audio Architect WPT

Ghangam, Sangeeta RST VST CSG

Hazan, Issachar CSME Validation Architect

CSG

Shepon, Oren CSME VST CSG

Zukerman, Dalit CSME Validation Lead CSG

Abramsky, Dan CSME Integration Lead CSG

Pawlowski, Maciej aDSP VST CSG

Rosenkiewicz, Sebastian aDSP Validation Lead CSG

Nayyar, Seema GFX VST VPG

Gilboa, Yoni LAN & TBT VST LAD

Gershon, Shmuel ISH VST CSG

Amit K Jain ISH Lead CSG

Katti, Gururaj SGX SV Val. Lead SVE

Murthy, Nandish SKYCAM VST SVE

Mechlovich, Harel IVCAM Val. Lead Per C

Sunny, Goh Kok Ying Audio Val SVE

Mihir Shah Platform PM Val SVE

Chintan Vora USB IO Val SVE

Chuah, Chee Thai Storage Val SVE

Igor Greinic SKYCAM Val SVE

Carter-brown, Christina S BtG Val. Lead SVE

Srinivasan, Vasudevan DPTF Platform Architect

CSS

Aran, Omer WiFi/BT Val. Lead WCS

Efrati, Eli WiFi/BT SW PM WCS

Crasta, Nithin GNSS Val. Lead IMC

Sudireddy, Subash Graphics Software Engineer

Graphics SW Validation Media

Validation


2Product Architecture

2.1 Platform Architecture

SKL reference platform is POR to support five different die-packages, ULX, ULT, SKL-H and SKL-M for Halo, and SKL-DT for DT. The SKL ULX (SKL-U) platform targets for Convertible and Detachable form factors while ULT (SKL-Y) platform targets for Clamshell and Convertible ones. The details can be found in Platform Architecture Document (PAD). The following block diagrams outlines the different form factors with all possible I/O support

The SKL Processor is available in following SKUs:

SKL Y 2+2 processor is 2.8W – 4.5W TDP chip in BGA Package

SKL U 2+2 processor is 5-25W while 2+3e is 8-25W TDP chip in BGA Package

SKL H 4+4e and 4+2 processor is 45-65W TDP chip in BGA Package

SKL DT and AIO 4+2 and 2+2 processor is 45-65W in LGA Package

Fig 2.1 ULT CRB Block Diagram


ULX (SKL-Y) Halo (SKL-M)

5 dies

7 Die/Pkgs

Dies 2+2 2+2 2+3e 4+4 e 4+2 4+2 4+2 2+2BGA (0.4bp)20x16.5x0.94 40x24x1.1 40x24x1.2

8-25w 65,55, 45 95w,65w,45w,35w

PCH

LGA(w/mILM/IHS)Package**

TDP (w)

ULT (SKL-U) Halo (SKL-H) DT (SKL-DT)

5-25w42x28x1.75BGA (0.7bp)BGA (0.65bp)

37.5x37.5

SPT-LP SPT-H (20x20.5)

35w,65w65w,55w,45w2.8-4.5w

Die 12 + 2ULT/X

SPT-LP

OPI

Die 12 + 2

ULT/X

SPT-LP

OPI

Die 22+ 3eULT

SPT-LP

OPI

64 MB

DMI

Die 3 4+ 2DT

SPT-H

DMI

Die 54 +4 eHalo

SPT-H

128MB

Die 34+2DT

DMI

SPT-H

Die 42+2DT

DMI

SPT-H

2.1.1 Skylake Y Detachable Platform (All I/O Possibilities)

2.1.2 Skylake-U Clamshell/Convertible Platform


2.1.3 Skylake H AIO Platform Architecture


2.1.4 Skylake H 2-Chip BGA Platform Architecture

The figure below outlines all of the software components that are expected to be either validated on or included with the Skylake platform. Components are color coded to highlight changes from the previous generation (Broadwell) platform, as follows.

Carry Forward. The component is either: (1) unchanged from previous generation platform, (2) a next generation or comparable part with minimal to no new features, (3) a component with very low or trivial updates required for the new platform. These components may be omitted from the remainder of the SAS, as their support is considered straightforward.

New Capabilities. The component or its generational predecessor is present on previous generation platform, but the component implements at least one new, non-trivial capability. New capabilities are outlined in the applicable SAS sections.

New for SKL. The component was either not presents on previous generation platform, or its function/scope has substantially changed from the previous generation.


2.1.5 Skylake Y SDS Detachable Platform

SKL SDS is Intel’s Ultrabook Solutions Development System for the SKL platform. This is the first detachable SDS design with a base plus a Tablet. It is designed as a ULX platform with a fan, which allows scaling up to 17w TDP with fan-less “mode” mobile PC platform. This allows up to 7W CPU where some CPU’s will be available at ~3W which would typically be a fan-less system. While designed against these new low power targets, however, the platform is still challenged to include almost all of Intel’s latest PC technology, including advances in perceptual computing through visual, audio, and sensor awareness as well as multiple wireless technologies and Intel vPro support. Moreover, the SDS is designed to accommodate the support of three operating systems (Windows, Android and Chrome) in order to demonstrate the 2015 targeted UX (User Experience) and usages. For Windows operating systems, SKL SDS is only POR to support Connected Standby environment.

SKL SDS definition is driven by UX (User experience) as indicated in Figure x. Besides of the targeted UX, other capabilities including TBT, LTE, NFC, Wifi+BT, active stylus, skycam and USB PD are also POR for SDS. The key features includes

1. 12.5 inch detachable system with standard size keyboard2. Fan based design with ability to simulate fan-less operation (flexible configuration thermal

options)3. Low Power Thunderbolt support in tablet section4. Direct Touch support with active stylus integrated into tablet ID5. Wireless Charging for Platform & Companion (placeholder in base)6. Skycam - High resolution 13MP 4K WF camera based on new CSI2, reuse of 2014 PerC UF

cam7. Detachable connector with good UX8. Power Delivery: Dual battery system with USB PD9. Audio: Support for LPAL, Direct Mics support, increased speaker size to meet Skype/Lync

certs 10. Secondary 6” e-Ink display for social broadcasting


11. Tablet features include: UF PerC camera, SkyCam, WiFi/BT, GNSS, NFC, 3G/4G/LTE, low power WiGig, USB3.0, PCIe SSD and Full size SD card


Skylake SDS Target User Experience

2.1.6 Skylake PMF features

Skylake Platform has significant improvements in terms of adding new capabilities to the Silicon and enhancements to existing legacy features to provide enhanced user experience. Below are the list of Key Platform Mega Features that are POR for SKL and one liner information for each PMF

Feature. HSD Feature.Title Feature.Owner

41891 Platform2015-Secure Enclaves

Provide safe place on the platform for an application to execute. This is base capability for various use cases such as mirror pass, secure transactions, DRM protection etc.

43520 Integrated Sensor Hub (ISH)

Sensor Hub is an Offloading Engine / Data Filter for Sensor Data Processing and leads to a gain in overall Power Efficiency

43575Converged AVS support for Platform 2015

integrated audio, voice and speech components into a hardware accelerated subsystem to achieve lower system power consumption, shorter and deterministic preprocessing latencies, and IP reusability

43736

Platform2015 - 2D Imaging Support

Enhance 2D image and performance by integrating 2D ISP plus provide low power mobile ecosystem camera interface such as CSI for high res world facing cameras. Plus support 3D gesture camera perC module for new user interaction with devices.

43821Touch Screen Controller integration for 2015

integration of touch controller in Intel platforms to match competition and reduce bom cost plus helps enable secure touch

43970 Wireless Charging TechnologyTechnology to enable wireless charging of PCs and Tablets as opposed to charging cellphones from PCs in previous year platforms

41923 Platform2015 - Hardware-managed P-states (HWP)

Extend IA P-state (MSR) interfaces providing richer OS/VMM guidance and feedback and enabling Platform (HW) control across entire P-state range

43327 Super Speed InterConnect (SSIC)

Low power mipi-MPHY standard on existing USB3 standard for compatibility with mobile ecosystem devices and eventually lower platform power in next gen products

43747 System Input Power Monitor CPU will use system power information to fully


Feature. HSD Feature.Title Feature.Owner

(PSys)optimize Turbo opportunities in Battery mode, previously due to guessing of system power information full utilization of available turbo headroom wasn't done.

43825 Platform2015 -Thunderbolt support

Changing existing thunderbolt to support 20 gbps/channel and other enhancements

43965 CommsHub

FW IP offloading functions running on ISH, enables new background comm. capabilities while platform is in connected Standby with minimal battery life impact and low BOM cost adder.

43972 Soc Duty Cycle

New technology that stop/starts the entire SoC within latency constraints saving power on semi-active workloads and providing more efficient (vs. freq.scaling) power/perf scaling

44317

USB Dual Role Mode Support (aka OTG)

Allows USB devices such as digital audio players or mobile phones to act as a host

44491

AOAA (never sleep) support for SKL

Always ON Always Available” is an implementation to provide the Always Connected user experienceA low power idle state where the platform is Always ON but display turns OFF on no user activity

40650

Platform 2015: Intel Enhanced SPI (eSPI) as LPC I/F alternative

Enables Intel to transition from 3.3v to 1.8v due to new process limitations and at the same time reduce pin count for EC interface

43734 PMIC support for 2015

Integration of various misc "jelly beans" motherboard logic into one chip to save board area, changes for 2015 for USB/TBT power delivery + FIVR removal changes

42681Platform2015 - Overclocking Enhancement & ACT support

Increase performance and productivity in Halo and DT platforms by overclocking plus ACT (adaptive clocking technology) helps mitigate RF interface issues.

42705Time Synchronization (Hammock Harbor)

Technology to help various devices such as speakers, displays, and sensors co-operate and synchronize between themselves and entire platform.


3Program Schedule

Below is the current SKL Program – HW/SW schedule (as on WW’10) [might be subjected to change based on program process] approved by SKL PXT. SKL Desktop AIO is Top priority from execution standpoint and will be the first Product SKU in SKL to go for larger OEM’s/ODM’s for Pre-Alpha/Pre-ES Milestone.

SKL Y will be first Product SKU to start with followed by SKL U and Desktop AIO.


4 Test Scope

4.1 Validation Overview

PSTV Team owns the System level Validation for the SKL Client Platforms for ULT, ULX, DT AIO, and Halo Programs. This includes System Test, System Stress and Sub-system validation. The validation vehicle is both RVP and SDS. It shall cover all the POR components - including both Internal/3rd Part components (CS & Non-CS vendor) as per the POR Matrix ensuring optimum coverage on various configurations (detailed in later sections).

The scope of PSTV team is detailed out in table 3.1

Major Deliverables from the Organization are the following:

Platform CI

Bi-weekly release of Platform BKC for SKL ULT/ULX/DT/Halo – Single BKC from PSTV team (includes the SDS BKC as well)

Bi-weekly SKL System Integration Dashboard that includes System, feature level Health assessment and QRC updates with defect chart

System Validation Updates into Platform HOP

Sighting Indicators – Critical/High defects per ingredient, Platform over platform comparison, DCRs/RCRs, etc.,

4.2 System Validation Scope

Table 3-1. System Validation Scope

Scope Out-of-ScopeAcceptance and Platform BAT that targets basic functionality and critical system level functionality (CI, BKC)

Ingredient functional level validation

(All Ingredient SW teams like VPG, CSG)

Use Case tests that target end user kind of testing

Silicon or component level validation (SVE SV and CV teams)

Inter-op and coexistence that utilizes multiple dependencies with shared capabilities

HW validation (EV, Mechanical, Thermal)

Platform power measurements for P1 workloads

Component Level power measurement (AEA)

Platform performance measurements (Benchmarks and Responsiveness ADK)

Performance KPI testing (Platform Evaluation & Competitive Assessment - PECA)

System stress tests that overloads multiple components, iterative testing (Sx, CS cycling, Concurrency).

Environmental Stress Testing (PRST) and MTBF testing (CQN)

System level certifications (includes Sys. WHCK from MSFT, Ultrabook Brand promise

Ingredient WHCK and compliance tests at device/component level (All ingredient and SDS


requirements and Skype – Lync) HW/System level)

User Experience verification - Use proper metrics to objectivity predict the perceived quality of key aspects of the user experience

Not all configurations will be tested, only those configs mentioned in table will be covered and 3rd party ingredient level validation (GED)


5Test Strategy and Schedule

5.1 Test Strategy5.1.1Test Coverage Approach

PSTV validation team will focus on the system level validation for both RVP and SDS Reference platforms. There will be leverage of previous generation of test content for BDW platform for the applicable legacy features. PSTV will focus on each major sub-system and identify legacy Vs. New features and add incremental coverage with more weightage for new features.

The table below list down the major sub-systems that PSTV team will test as part of System Validation. Connectivity and Multimedia are high risk items for SKL considering that we have new PMF (like AVS, SKYCAM, Wireless Charging) and UX focus on No Wires and Immersive Collaboration

Sub-system Major capabilities/domains

Connectivity

WiFi

WWAN

BT

WiGiG

GNSS

NFC

CHUB

LAN

Multimedia AVS (Audio, Voice, Speech)

Graphics (Media, Display, 2D/3D)

Imaging (2D Cam, 3D Cam)

WiDi

IO & User Interaction Storage – SATA, PCIe NVMe, RST

PCIe, USB 2.0, 3.0, SDXH, USB OTG

Touch Pad/Panel

Sensors - ISH

Thunder Bolt

Keyboard/Mouse

Stylus

Security and Manageability

AMT

Secure Enclave

ITP (OTP, WYSIWYS)


Sub-system Major capabilities/domainsAnC and BtG

TXT

PAVP, HDCP and UV

Secure LBS

PnP & Thermal Management CS

Sx

Deep Sx

DPTF

HDC

PMIC

Overclocking

5.1.2 Test Groups and Focus Areas

SKL System Test Content is divided into the following Test groups:

Platform Acceptance Tests: This consists of 2 test suites – One is the acceptance test that focuses on sanity checkout on basic functionality of each critical feature/ingredient of the platform, such as boot test, OS installation, Interface check out such as USB, SATA, I2C and so on. These are the bare minimum test to ensure the ingredient driver/FW software to meet the PSTV platform integration validation acceptance criteria before the platform validation starts. Once completed, we do the Platform BAT that focuses on system level attributes like Power Management Cycling (Sx, CS), Responsiveness (CS, S3 exit), Basic use cases (Audio, Video Playback) and Minimum Stability (Idle, basic stress) testing. These tests will be run 3-4 times per week based on CI build changes and are completely automated

Platform Interoperability/Coexistence Tests: Platform interoperability/coexistence tests are based on user scenarios which might include multiple functional blocks to work in tandem. Test cases involve two or more relevant interfaces/capabilities working simultaneously without any issues to validate systems HW and SW stability. Interoperability test includes capability, interoperability with common usage identified, and usage interoperability with common capability identified.

Platform Use Cases: Platform use cases test is to validate key usages to understand the proper context in which new technologies are exercised and how it relates to architecture for validation purpose. Platform usages identify and validate the impact of new platform features on usage targets, and identify measureable UX targets that may affect the end user experience. These validation cycles will be performed when the system has reached certain stability.

System Stress Tests: Under stress testing, PSTV validation team will validate the platform stability for extended hours of usage with heavy system workload. Stress testing will be done for the subsystems of the platform (such as Multimedia, Connectivity and IO’s) simultaneously. Stress tests also include Iterative/Cycling,


Concurrency & long idle duration tests (CS, Sx cycles) run on multiple systems and configurations for system stability. Stress testing will be carried out for all the external milestone releases.

Platform Key Performance Indices (KPI): Measure the platform power and performance indices including power consumption, thermal measurement, and system level responsiveness/latency measurement.

Certifications: Certification testing includes MSFT system WHCK testing. MSFT test framework is used to certify HW devices for Windows*. MSFT System level WHCK testing will be owned and executed by PSTV validation team. All other component certifications will be done by the respective component teams.

Connected Standby Testing: Connected Standby (CS) test cases have been spread and integrated into each validation domain, such as Communication, Touch, Sensor, and so on, but this group of tests will focus on the connected standby entry/exit. It puts emphasis on testing different ways of CS entry when it is in in idle state and when there is activity or system is in under workload. It also covers Connected Standby user experience for wake.

Operation Mode Testing: The SKL SDS platform is a detachable SDS system, which means that it can be used as both a clamshell and as a tablet. This distinction is important because certain features function differently depending on the mode. It also operates in ‘reverse thick tablet mode’. For the most part these are no different than tablet mode, but there needs to be some basic checks to make sure they work as expected.

User Experience Verification (KPI): Identify key focus areas for UX as per UX Pillars and critical use cases to verify the metrics/targets.

5.2 Automation Strategy

Framework:

PyAnvil/TWS Client/Host test executor Compatible with WHCK IRIS infrastructure

Languages:

Python PowerShell Windows command line

Behavior Driven Testing:

Create behavior focused scripts that map as closely as possible to the test steps defined in Contour

Reduces script complexity & points of failure Enhances code reuse Enables external contributors

Test Case automation priority: TCRB 1x1 Acceptance Suite TCRB PBAT Co-engineering/WSB Legacy Tests

HW Ready/P1 – P2 – P3, Bring Up/P1 – P2 – P3, Integration/P1 – P2 – P3, etc


Leverage code from MCG (~136 Test Case for WSB Legacy) Leverage tools from ingredient team as able

5.3 User Experience Verification

UX verification has several layers of coverage:

Exploratory Heuristics Use case –Interoperability (Competing/Fusion Usages) UX KPIs Platform PIs


5.3.1 5UX KPIs

Solution

Criteria Minimum

WiDi 1-1 Device Discovery ≤3.5 sec (1st device)

≤7.0 sec (Total 1st 5 devices)

WiDi 1-2 First Time Pairing Success Rate ≥ 95% 1st trial =100% 2nd trial

WiDi 1-3 Connect Success Rate ≥ 95% 1st trial

WiDi 1-4 Connection Reliability Rate ≥ 97%

WiDi 1-5 Connection Time ≤5.8 sec

WiDi 1-6 Latency ≤ 150ms (quality mode)≤65.0ms (interactive mode)

WiDi 1-7 Audio/Video Clarity ≥4.0 MOS

WiDi 1-8 A/V Lip Sync Audio lead≤40ms

Audio Lag ≤60ms

WiDi 1-9 A/V Smoothness ≤1.3% dropped frames No frame pauses ≥100ms

WiDi 1-10 Value Proposition Understanding ≥5

WiDi 1-11 Overall First Time Start to Use ≤10 min*.

WiDi 1-12 First Time SW Launch to Use ≤3 min*

WiDi 1-13 Automatic Reconnect ZBB?

WiDi 1-14 Managed Meeting Display Switching – vPro

≤5.8 sec

WiDi 1-15 First Time Key Task Completion Rate ≥90%

YAP 1-1 Enrollment Image-Capture Success Rate Success rate ≥99%

YAP 1-2 Enrollment Image-Capture Latency ≤4.5 sec

YAP 1-3 Initial Use Recognition Success Rate Recognition success rate ≥95%

YAP 1-4 Continued Use Recognition Success Rate

Recognition success rate ≥97%

YAP 1-5 Initial and Continued Use Recognition Latency

≤1.5 sec

YAP 1-6 Enrollment UI Subjective Rating ≥4

YAP 1-7 First Time Setup-to-Use ≤3min

YAP 1-8 Error/Help & Support Subjective Rating ≥4

YAP 1-9 OOBE Subjective Rating ≥4


Solution

Criteria Minimum

YAP 1-10 OS Login Subjective Rating ≥4

YAP 1-11 GTM UXA Key Metrics SUS ≥85 NPS ≥50

Genie Startup 95% 90% 50%

Genie Wakeup 95% 90% 50%

Genie Latency (Internet Search) 50%/ nominal 95%/worst case

Genie Latency (ChatBox) 50%/ nominal 95%/worst case

Genie Latency (Q&A) 50%/ nominal 95%/worst case

Genie Latency (Command and Control) 50%/ nominal 95%/worst case

Genie Latency (Social Media) 50%/ nominal 95%/worst case

Genie Latency (Email and Calendar) 50%/ nominal 95%/worst case

Genie Latency (2s Dialog) 50%/ nominal 95%/worst case



Genie Latency (Dictation - offline) 50%/ nominal 95%/worst case

Genie Latency (Dictation <3s - online) 50%/ nominal 95%/worst case

Genie Latency (Dictation 3-7s - online) 50%/ nominal 95%/worst case

Genie Latency (Dictation >7s - online) 50%/ nominal 95%/worst case

WiDock 1.1 Device Discovery <7 sec

WiDock 1.2 Pairing Time <1 min

WiDock 1.3 Pairing Success Rate >97%

WiDock 1.4 Docking Time Manual <5.8sec

WiDock 1.5 Docking Success Rate >97%

WiDock 1.6 Docking Reliability Rate >97%

WiDock 1.7 Undocking Time Manual TBDAuto <4.5sec

WiDock 1.8 Session Recovery (Auto ReDock) <2.6sec

WiDock 1.9 Signal Quality Indicator Subjective Rating => 4

WiDock 2.0 Auto Update/Error/Support Subjective Rating => 4

WiDock 2.1 I/O Latency <125ms

WiDock 2.2 OOBE Ease of Installation <3 minutes

WiDock 2.3 Battery Life Impact TBD

WiDock 2.4 Feedback Timeliness <125ms

WiDock 2.5 AV Quality >4.0 MOS


5.3.1 Platform KPIs

Common requirements

Overall user satisfaction

of the usages (1)

SUS (System Usability Scale) - Minimum: 85 NPS: 30Tested with external users in real life environment. Min. 30 participants. Minimum time: month.

Common requirements

Co-existence (1)

Minimum: Be able to perform all the platform co-existence use cases successfully as defined in Contour under 'Co-existence" folder. This is a superset of the BDW platform journey described in the Sheet "BDW Journey"

Common requirements

UI design scalability (1)

UX expert inspection (as part of system level heuristic evaluation). - touch areas (if applicable): the distance from the center of one element to the center of the other element should be at minimum 9mm.- font size (no font size less than 9 pt. - exceptions have to be approved)- static image quality against the given reference designs: DPI: 72- layout proportions and place of objects stay true to the original/reference UI layout design provided by graphics designer.

Common requirements

Form factor (1)

Be able to fully - perform the key use case as defined in the usage specific UXRD.- meet quality and performance related UX KPIs

Common requirements

Modes (1) Be able to fully- perform the key use case as defined in the usage specific UXRD.- meet quality and performance related UX KPIs

Common requirements

System resume

speed (1)

(NEEDS TO BE DISCUSSED WITH UB folks) Minimum: 1 second, which gives MOS, score of 4 or more on a 5-point rating scale.Outstanding: < 500 msSystem needs to be loaded with minimum amount of content: TBD in detail.

Common requirements

Boot up speed (1)

(NEEDS TO BE DISCUSSED WITH UB folks)Minimum: 8 seconds. Links to MOS score greater than 4/5Outstanding: less than 5 secondsSystem need to be loaded with minimum amount of content: TBD in detail.

Common requirements

Battery life - form factor

(1)

(NEEDS TO BE DISCUSSED WITH UB folks)Outstanding:Once a 24 hours regardless of the weight/screen size.Target: Convertible: 11.6" 1.3kg 13.3" 1.5kg 14.1" 1.9 kg, 14.1" 2.1kg Detachable w/o base: 10.1" 750g, ≥ 8.5h11.6" 900 g, ≥ 8.5 13.3" 1050g, ≥ 8h14.1" 1150g, ≥ 8h 14.1" 1350g, ≥ 8h (note: do data from the study )


Common requirements

UI design consistency

(1)

UX expert evaluation. Comply with Intel Design guidelines: fonts, icons, colors, and imaginary. Use the same labels and /or icons for the same meaning. Minimum: Check the main views and dialogs. https://private.filesanywhere.com/fs/v.aspx?v=896b65869290adae9da2&C=355

Specific cross usage

requirements

Interoperability:

integrated voice

solution (1)

1. One access point for setup and settings for Intel voice solutions2. Single wake up word for Voice assistants and Wake on Voice solution.


requirements

Consistent quality

across voice solutions (2)

Target: 90% accuracy at 2 sec latency with user feedback within 500ms. (Gives MOS of 4.0)Support the same set of languages.


requirements

Interoperability: remote

use (2)

AUS Average usability score is 4/5 or above. Tested with external users, with minimum 30 participants.


requirements

Integrated authenticatio

n solutions (1)

TBD: POST TTM


requirements

Camera co-existence (1)

TBD: POST TTM: YAP can access camera when 3D camera is used by another application.

Oobe (unpacking)

Packaging info

UX expert evaluation as part of the system level heuristic evaluation

Oobe (unpacking)

Instructions UX expert evaluation as part of the system level heuristic evaluation

Oobe (unpacking)

Time/task accomplishment

90% users can successfully set up the device for basic use without help within 5 minutes. External system user study with minimum of 30 participants

Oobe (unpacking)

Perceived quality

AUS Average usability score is 4/5 or above. Tested with external users, with minimum 30 participants.

Oobe (unpacking)

Opening UX expert evaluation as part of the system level heuristic evaluation

Oobe (unpacking)

Support UX expert evaluation as part of the system level heuristic evaluation

First time device set up

Set up experience

UX expert evaluation: - Give users realistic time estimate for setup process in terms of time and steps. - Allow skip and resume- Be able to go back and forth without losing information.


Interoperability -

efficiency

Data item is asked only once during any Intel usages set up. For items refer to the sheet 'Data Items'


UI design UX expert evaluation, Terminology, navigation, layout structure, patterns/widget, and visuals are consistent across usages and OS.



Task and time

accomplishment

90% users can successfully set up the device without help within 8 minutes.

OS Express Settings assumed Includes also YAP set up. Gestures and Voice: Introduction to the offering


Perceived quality

AUS Average usability score is 4/5 or above. External users with minimum of 30 participants.


Oobe battery life

Battery should be charged more than 50%

5.3.2 Validation Execution Configurations

Skylake execution at PSTV aligns to the Platform validation milestones, including Pre-Alpha, Alpha, Beta, and PC/PV milestones. The following table provides the Skylake validation execution schedule and milestone details:

The Skylake execution across different configurations is depicted in the following table. It shows the configurations across different POR OS flavor, Corp/Consumer, connected standby/Non-connected standby SKU. High coverage is given across the golden configuration which is Win 8.1* 5MB SKU for CS & NCS. The other configurations are low touch or No touch based on weightage given as per marketing inputs.

Segment RVP/ SDS OS ModeWin 7 64 Bit Win8.1 64 bit

Corp Consumer Corp

ULX

RVP3 (LPDDR)

CS NA Golden P1 P2

Non CS P1 NA Golden P1

SDS SIP CS NA PnP PnP

SDS CS NA Golden P1 P2

ULT RVP7 (DDR3L)

CS NA Golden P1 P2

Non CS P1 P2 P1

DT/ AIORVP9 (DDR4) NA P2 P2 Golden

P1RVP10 (DDR3L) NA NA P1 P2

Halo-H RVP11 (DDR4) NA P1 P2 Golden

P1


Golden P1

CI, BKC (Weekly), Use Case, Inter-op/Coexistence, Stress, Sys. WHCK, Responsiveness (Biweekly BKC)

P1 Inter-op/Coexistence, Sys.WHCK (Milestone BKC) and P1 tests ,Use Case, Cycling tests(Bi-weekly BKC)

P2 Delta features, P1 tests, Cycling tests (Milestone BKC)

Below is the SW BOM that will be part of BKC configurations based on supportability on different Product SKU’s and OS. The milestones are also updated on availability

Sl. No

Ingredient Type Vendor

CS/NCS support

Segment (Corp/Consumer)

Product SKU's

Win 8.1 64 CS

Win 8.1 64 NCS

Win 7 64 Bit OS

SKL Y_ULX Milestone

1 BIOS FW Intel All Both All Yes Yes Yes ES0

2 CSME FW Intel All Both All Yes Yes Yes ES0

3 EC/KSC FW Intel All Both All Yes Yes Yes ES0

4 Chipset Driver Intel All Both All Yes Yes Yes ES0

5 Graphics Driver Intel All Both All Yes Yes Yes ES0

6 WiFi Driver Intel All Both All Yes Yes Yes ES0

7 BT Driver Intel All Both All Yes Yes Yes ES0

8 CSMEI Driver Intel All Both All Yes Yes Yes ES0

9 LAN Driver Intel All Both ULT/Halo/DT only

Yes Yes Yes ES0

10 RST Driver Driver Intel All Both All Yes Yes Yes ES0

11 LPSS (Serial IO) Driver Intel CS

only Both ULT/ULX only Yes Yes No ES0

12 GMM Driver Intel Both Both All Yes Yes No ES0

13 Intel SST Audio (ADSP) Driver Intel Both Both ULT/ULX

only Yes Yes No ES0

14 Audio Codec Driver 3rd party Both Both All Yes Yes Yes ES0

15

SKYCAM (AVStream, CSI2 & Sensor driver)

Driver Intel Both Both ULT/ULX only Yes Yes No ES0

16 IVCAM Driver Intel Both Both All Yes Yes No ES0

18 Comms Hub Driver/FW Intel Both Both

ULT/ULX/Halo only

Yes Yes No Pre-Alpha


Sl. No


CS/NCS support


Product SKU's

Win 8.1 64 CS

Win 8.1 64 NCS

Win 7 64 Bit OS

SKL Y_ULX Milestone

19 ISH Driver/FW Intel Both Both ULT/ULX

only Yes Yes No Pre-Alpha

17 WiGig Driver Intel Both Both All Yes Yes Yes Alpha

20 USB OTG Driver Intel Both Both ULT/ULX only Yes Yes No Pre-

Alpha

21 Thunderbolt (AR) Driver Intel Both Both All Yes Yes No Alpha

22 SG Driver Driver 3rd party NCS Both ULT/Halo Yes Yes Yes Alpha

23 NFC Driver 3rd party Both Both All Yes Yes Yes Pre-

Alpha

24 CPPC 2.0 Driver Intel Both Both All Yes Yes Yes Pre-Alpha

25 DPTF (will include SDC) Driver Intel Both Both All Yes Yes Yes Pre-

Alpha

26

Touch Pad/Touch Screen (Precision)

Driver Inbox Both Both All Yes Yes No ES0

27 Standalone GNSS Driver Intel Both Both

ULT/ULX/Halo only

Yes Yes No Pre-Alpha

283G LTE(WWAN)/GPS

Driver Intel Both Both All Yes Yes Yes Alpha

29 AOAC Driver Intel NCS Both TBD TBD TBD TBD TBD

30 FFS FW Intel NCS Both TBD TBD TBD TBD TBD

31 AOAA Software Intel NA Both DT only TBD TBD TBD TBD

32 Wireless Charging FW Intel Both Both ULX only Yes Yes No Pre-

Alpha

33 WiDi (Intel) App Intel Both Both All No No Yes Alpha

34 SBA App Intel NCS Corporate All Yes Yes Yes Alpha

35 PEAT App Intel NCS Corporate All Yes Yes Yes Alpha

36 IEC App Intel CS Both All No No Yes Alpha

37 Skype App 3rd party All Both All Yes Yes No TBD

38 Genie App 3rd All Both All Yes Yes No TBD


Sl. No


CS/NCS support


Product SKU's

Win 8.1 64 CS

Win 8.1 64 NCS

Win 7 64 Bit OS

SKL Y_ULX Milestone

party

39 YAP App 3rd party All Both All Yes Yes No TBD

40 Seer Creek App Intel All TBD TBD TBD TBD TBD TBD

41 Mcaffee App 3rd party All TBD TBD TBD TBD TBD TBD

5.4 High level milestone strategy & execution schedule

Pre-Alpha: The objective is to enable core ingredients such as CSME, BIOS, Wireless, Graphics, Audio, LAN, and ensure that we find early issues blocking the Alpha milestone. Special focus is on targeting basic use cases for core ingredients, Sx and CS integration. The extended ingredients may or may not be part of coverage in this milestone (as per their enablement date).

Alpha: During Alpha testing, platform features are expected to be integrated in BKC stack (Intel & 3rd party) for validation and health status check/reporting. We also intend to cover the WHCK, Power measurements, Responsiveness coverage progressively to achieve early targets for platform and uncover early blocking issues. There will be more focus on extensive use case validation and very focused UX verification


Beta: During Beta all features that are POR will be covered with aim to uncover platform issues/stress or performance issues. The BKC execution, Inter-op, Sys.WHCK, Stress (includes Cycling), PnP validation & UX Verification is covered in this milestone.

PC/PV: All features and functions in POR are at planned reliability and regulatory level, ready for SRA. Target power & performance targets are met and

certifications are ready. Security and reliability result pass. All planed test cases will be executed.


6Platform Validation Process

6.1 Platform CI and BKC Process

PSTV Team shall provide the Platform Level CI, Best Known Configuration (BKC) to customers/stakeholders – which defines a stable platform stack, enablement details, work around (if any), major issues, and so on.

Platform CI: PSTV owns Platform Level Continuous integration on daily basis based on SW build changes to find issues early in the cycle and deliver a stable stack. The process is completely automated wherein ingredient teams are expected to submit their CI build to Artifact and Platform Build will happen on daily basis. PSTV will run Acceptance and Platform BAT tests to qualify CI build and report out on a daily basis. Target audience is internal customers

Weekly BKC: Weekly BKC is run every once in week on the latest available ingredients. Focus of testing is a P1 and P2 test that includes basic use cases, basic PM flows. It provides the stable available configurations for the internal customers with a list of known issues. This report doesn’t provide any guidance on health assessment. Target audience is internal customers

Bi-weekly BKC: Bi-weekly BKC is run every two weeks on the latest available stable ingredients that have undergone P1/P2 tests and focus is on incremental validation that includes Power measurements, System. Whck, Responsiveness, Inter-op and extensive use case validation. It provides the health assessment of the platform with stable available configurations with a list of known issues. Bi-weekly cadence is based on customer feedback and most of the ingredients’ update frequency. Target audience is internal customers

Priority Frequency SKL Test Plan Scope Test Group Examples

P1Daily CI Ingredient Acceptance tests, BAT tests

Weekly Weekly BKC Sub-system, System test Basic use cases

P2

Weekly Weekly BKC System test Use cases, Inter-op

Build/BKC Bi-weekly BKC Sub-system Stress, UX KPI

Build/BKC Bi-weekly BKC System Test, System Stress Cycling, Certification, PnP, Responsiveness

P3

Build/BKC Bi-weekly BKC System Test Complex use cases, coexistence

Milestone Milestone BKC System Test, System Stress Corner cases, Stress scenarios, UX KPI


Milestone BKC: This BKC is run for every software milestone (once in a milestone), which includes completely validated ingredient releases. This is executed typically 2 weeks before the official milestone date on the milestone drops submitted by SW teams and external HW stepping samples. The health assessment is done as per QRC exit criteria and recommendation is given to program forums on system health status. This includes all the corner case testing, system stress and UX verification in addition to bi-weekly BKC tests. Target audience is external customers

Based on validation execution phases and the platform stability, we adjust which test content to be run and how many test cases to be run. The test content is prioritized as per below table and cadence is defined as per priority


6.2 Platform Validation Criteria and Guidance

6.2.1 CI Entry Criteria

One of the most important CI process steps is to ensure ingredient teams submit the validated quality ingredients to the platform team before PSTV team starts the Platform level CI. The ingredient teams should do basic level of automated testing as part of CI build and should follow submission criteria. Here is the general CI entry criteria guidance for all ingredient teams to follow:

6.2.2 BKC Entry Criteria

In continuation to CI, BKC process enforces some additional entry criteria for ingredient teams to follow to ensure they submit the validated quality ingredients to the platform team before PSTV team starts the Bi-weekly validation cycle. Here is the general BKC entry criteria guidance for all ingredient teams to follow:

Ingredient teams must test submitted driver/FW with the latest BKC stack and core BKC on N-1 CI build. PSTV team will define the Core BKC that is expected by all ingredient teams to be used in their validation

Ingredient teams may decide what test content to use for their ingredient level BAT testing. PSTV validation team will also provide the platform BAT for ingredient teams to run.

Upload tested ingredient package to specified network location / BKC Life cycle tool before bi-weekly ingredient submission cut-off time, and the package includes(not limited to): Driver/FW binary files BAT test results Release notes: critical configuration info and feature updates Known issues with HSD links

If any of the criteria defined above is not met, PSTV reserves the right to reject the submitted ingredients, and the rejected ingredients will not be included in the to-be-released BKC stack.


6.2.3 BKC Submission Criteria

The Win8.1* OS imaging process will be changed to WIM format along with publishing the individual ingredient as downloadable links. These criteria are shared to all ingredient teams. The tool introduced in SKL time frame is “BKC LC” tool which was developed to track the submission, entry criteria, rejection etc. Here are some key criteria:

Posted in BKC-LC tool

No compressed files posted

PAC packaging requirements met

FW Driver acceptance checklist

Release notes

Sightings

SWLC met

Waivers

Ingredient BAT results

Device WHCK

Ingredient BAT on recent BKC

6.2.4 Bi-weekly BKC Exit Criteria

BKC exit criteria are general guidance for PSTV validation team to follow and it may vary case by case. During the platform validation, it is tolerable for certain ingredients to have some non-blocking and known issues. As long as the ingredient development team and platform validation team agree, the BKC software stack could exit with known issues. Following are the basic criteria for BKC Exit:

No new blocking issue found during the BKC test

Power and latency/responsiveness measurement values are equal or better than those of N-1 BKC.

Overall test results are same or better than N-1 BKC results.

6.2.5 Milestone BKC Exit Criteria

Milestone BKC exit criteria should meet the QRC requirements at each milestone: QRC goals must be tracked bi-weekly to ensure the overall validation process to step towards the QRC milestone goals. Below are the QRC exit criteria per each milestone


Measure Pre-Alpha* Alpha* Beta* PV*

Platform Validation Domain Attempted

(% of planned for PV )

100% of pre alpha test suite(N/A)

100% of Planned Enabled Features 100% 100%

Platform Validation Domain Passed(% of Attempted )

≥ 60% of Pre-Alpha Tests( N/A) ≥ 70 %( 50%) ≥ 85% ≥ 97%( 95%)

Platform Sx Cycling** 5 cycles (N/A) 100 cycles 500 cycles 1500 cycles

System WHCK( Tentative Check with BDW at Beta )

Assessment done and risk

filed and tracked. (N/A)

System WHCK – Overall* -50%

passing;

Intel Ingredient+ TBD -50%

passing. (All Tests Executed and any issues filed as Critical

Defects w/appropriate

Ingredients)

System WHCK – Overall* -80%

passing;


passing. (All Tests Executed and any issues filed as Critical

Defects w/appropriate

Ingredients)

System WHCK – Overall* -

100% passing.


passing. ( Certified)

Use Case Platform Interop Validation level.(Use Case Link as

tracked by Skylake PXT )

>=70% of pre alpha validation

use case( defined by PSTV and alligned with PSXT/PVST)

>=70% successful pass rate and

meets Alpha level KPI.


meets Beta level KPI


meets PV level KPI.

Number of Open Critical Severity defects( identified at Platform level by PSTV and not accounted for in

the Ing counts)

N/A

≤ 15 ≤ 10 ZERO

Number of Open High Severity defects

N/A ≤ 100 ≤ 75 ≤ 15

Platform Responsiveness

N/A

<25% deviation from Target

ValuesLog a defect for any deviation from Target

Values

Less than Target Values specified on PC Client Responsiveness QRC

Requirements Dashboard Log a Defect for any deviation

within GuardbandCreate an Exception for any

deviation outside Guardband

Platform Power and Performance

Legacy UCs (CS ,Windows Idle ,Video playback 1080p, MM12-OP, Web

Browsing

PnP Requirements

Defined and Tool for measurement

in place.

Power :<15% deviation for

(legacy UCs) and <25% deviation for (new UCs) *

Power: < 5% deviation for

(legacy UCs) and < 15% (new UCs)

of the targets.

Meet Targets (Battery Life and Wattage Actual

values for Workloads

measured by


https://sharepoint.amr.ith.intel.com/sites/PCPO/SKL%20Platform/SitePages/Home.aspx?RootFolder=/sites/PCPO/SKL%20Platform/SKL%20Platform%20Dashboard/Use%20Cases&FolderCTID=0x012000F67670BAFEF962428784B85AA5BE8542&View=%7BCAE820AA-67CF-494D-BF5A-D6D12DCAFFF2%7D






Measure Pre-Alpha* Alpha* Beta* PV*

New UCs ( These need to be confirmed -Gaming, LPA, LPAL, Video Conf, Video Cap, WiDi, Speech) NoteP

Power: < 25% deviation from the targets for legacy UC’s. *

(N/A)

Performance: <25% deviation

from the targets.

All sightings filed, with debug and

resolution resources

committed. (N/A)

Performance: < 15% deviation from targets

(N/A)

PECA match those specified at

PPOPL3)

Connected Standby Criteria Meets CS Criteria Meets CS Criteria Meets CS Criteria Meets CS Criteria

Notes: ^Each Platform milestone is achieved only after all ingredients have achieved the corresponding

ingredient milestone.

**Sx cycling in this context is defined as “S3-S0, S4-S0, S5-S0, Warm, Cold, Global Reset“

The number of cycles needs to be done on one system in one continuous test (i.e., NOT splitting up the cycles across parallel systems and combining the results)

Default BIOS setting for ME_Enabled should not be changed (i.e. ME is enabled)

For Platform team’s minimum required for number of systems is 10.The number of cycles needs to be met 80% of the time for multiple runs/systems.

NoteP- Power and Performance from B0 PO to pES – use “Safe” configuration. By ES – Final SDS BOM configuration –Meaning that we have finalized the configuration but not all devices are yet available/enabled (ex. eDP1.4 panels)By QS – Final BOM (includes every POR devices)

Exc- Notes for System WHCK No exception needed for overall not meet targets.

*Log a Defect for any deviation within Guardband.Create an Exception for any deviation outside Gaurdband

6.2.6 Sighting Process

6.2.7 High Speed Database (HSD) Block Diagram

Pre-sighting HSD is the database for tracking the pre-sightings, sightings, defects, feature requests, and so on for client platforms.

PSTV use ClientSW HSD for Pre-sighting and Sightings:

https://vthsd.intel.com/hsd/clientsw/default.aspx

Pre-sighting can be directly promoted to Client BIOS HSD, Tools HSD (using “promote” option), Graphics HSD (using “promote” option), and ADSP Sighting (using "clone" option) while for other HSD we need to manually file in other HSD. After promotion, ensure to fill the “promoted HSD” and “promoted ID” fields in the pre-sighting HSD. Ensure to fill appropriate fields in the promoted HSD as not all fields are common between Pre-sighting and Sighting HSD and manual update of certain fields are also needed. Pre –Sighting promotion must be done based on the state of sighting, that is, Open Promoted, Development. In case of


https://vthsd.intel.com/hsd/clientsw/default.aspx

3PV Components, sighting promotion can be done only when a bug is assigned to a debug lead apart from the previous condition.

All the Sighting and Debug BKM details are available @

http://pspv.intel.com/sites/pspv/Skylake/Sightings%20and%20Debug/Sighting%20and%20Debug%20process.aspx


Figure 6-1. High Speed Database (HSD) Block Diagram



The following table provides the term descriptions of the Status Value used in the HSD Block Diagram:

6.2.8 [email protected] of Ingredient HSD

The following links contain list of all ingredients HSD and Sysdebug Leads for SKL Platform

Area / Group Sysdebug HSD Sysdebug ProcessBIOS GAR\spmukher ClientSW PPTCPU Chinkov, Alexey SkyLake CPU PPT

Platform GAR\ravishku ClientSW PPTGfx Shetty, Charu H pcgsw PPTSPT Chew, Wai Kee Sunrise point HSD PPT

CSME Zukerman, Dalit CSME PPTWCS Zwerdling, Jacob CQ / CQMS.MWG.JFRST Callahan, David RST HSD PPT

SST / Display Audio Luczycki, Michal Sunrise Point HSD PPTSkyCam Katznelson, Guy Imaging HSD PPT

ISH Gallula, Adi ISH HSDLAN Horwitz, Moti LADSW HSD

WiGig GER\mweinreb CQ / CQMS.MWG.JF PPTiSCT Danneels, Gunner AOAC HSD

Chipset Kranak, Vaul DDPTF AMR\crpadalaTBT Grinkrug, MichaelLPSS Pawlocki, Leszek

GMM Krolikowski, Rafal HSD Project GMM IGK WiKi


Table 6-3. Term Descriptions - HSD Block DiagramStatus Value Description

New Defect Record is created and submittedAssigned An owner is Assigned

Implemented Defect has been fixed by the ownerVerified Defect has been verified internallyRejected Internal verification of the defect fix is unsuccessful

PendingAdditional information or verification required.(Examples: Certification data, data from test, customer accept, and so on.)

Deferred Defect fix is postponed to a later time/release

ClosedIssue has been closed.Note: If the record is submitted by external user (that is, a customer), closure of the record may not occur until the change has been re-verified by the external user.

Area / Group Sysdebug HSD Sysdebug ProcessRVP RVPSGX Cohen, HaimIPT Sun, Nan

6.2.9 Platform Test Overview

6.2.10 Connectivity

6.2.11 Overview

Connectivity is the ability to link to and communicate with other computer systems, electronic devices, software, or the Internet. Wireless communications on SKL consist of multiple technologies:

WiFi 802.11ac

Bluetooth 4.1

Location Core (Comms Hub)

Wired LAN

WWAN -3G/LTE

Discrete GNSS

Wireless Charging

NFC

WiGig

6.2.12 Intel WiFi/ BT Solution

Intel’s 2x2 Wireless LAN controller is provided as part of the Snowfield Peak module for SKL. PCIe Gen2 will be used for host interfaces. This assumes that Microsoft will accept the PCIe bus as a valid part of a connected standby system. Intel products require additional C-Link interface to support AMT connection of the WiFi to the CSME for usage by AMT. Also an additional UART port is needed for connecting the module to the CommHub. This UART port is shared between the WiFi and the BT for connection with the CHUB.

SKL supports BlueTooth (BT) 4.1 which supports BR (Bluetooth Basic Rate), EDR (Bluetooth Enhanced Data Rate) and Bluetooth low energy and adds couple of items over BT4.0:

1. Dual mode – support slave and master role concurrently in BLE.2. Secure connections – improve security of BLE connections.

The Bluetooth receiver, if connected by USB, requires nothing other than Windows in-box drivers for fundamental functionality. However, Intel provides custom drivers that add support for Bluetooth profiles that are not natively supported by the operating system. An example of such a profile is HFP with WBS and A2DP with APTX support. If connecting the Bluetooth receiver over UART, a Bluetooth controller driver must be installed. Additionally, the UART host controller driver provided as part of the


Low Power Sub System (LPSS) Intel driver package must be installed on the system. Microsoft connected standby guideline is not to use a HW RFKill button. Snowfield Peak will not support WiFi HW RF kill and SW RFKill solution will be implemented

The WiFi/Bluetooth combo wireless solution on the platform is Intel’s Snowfield Peak (SFP) solution. The supported interface for WiFi is PCIe while BT will support both USB and UART depending on platform and OS combination. In addition to the existing UART interface between Bluetooth and the host, two UART interfaces are added. One UART is to support Comms Hub offloading via the ISH and the other one to support coexistence with IMC 7262 LTE module. Both reside on a multi-function UART (MF-UART) inside SFP that is routing all external UART in the module.

The major new features introduced in Snowfield WiFi SW stack include:

LTE coexistence (to avoid LTE/WiFi/BT interference) Indoor location based services (based on Comms Hub) Secured WiFi tagging (based on CHUB and CSME) Hammock Harbor/Music Creek (see Hammock Harbor section) AMT11 with connected standby (AMT with CS is available in BDW) and with CSME power

gating support. WiDi 6.0 Intel Hotspot 2.0

6.2.13 Indoor Location Based Services

Indoor location based on Comms Hub is a new platform capability for SKL platform. Measuring distance from access points based on packet time in transit are being incorporated and optimized in SFP solution. This location data is then cross referenced with an access point’s geographic location through cloud based services and exposed to software for use in specially developed ISV applications

6.2.14 Wireless WAN (3G / LTE)

The key change for Skylake platform is that WWAN Si is now owned by Intel. The 3rd party solutions like Broadcom can be still in use, but the POR is Intel WWAN solution. WWAN (IMC XMM7262) is connected to the PCH by M.2 module via SSIC interface for Skylake platform. XMM7160, the first generation of LTE, is connected to the PCH via USB2 and this is not POR yet (depending on OEMs’ request). XMM 6260 (3G only module) will be used for the emerging market, but this is not POR either. All these modules include a GNSS. Only XMM7262 module provides an I2C sideband interface to the Comms Hub for location and sensor fusing usages. This I2C is controlled by Comms Hub FW, but not LPSS I2C host controller driver.

The coexistence of WiFi/BT and LTE for WWAN is also POR which requires 3 pins from WWAN M.2 module to connect to WiFi/BT M.2 module. The coexistence only supports with XMM7262 module.

Other platform features for SKL include ACT, RTD3 (M.2 module power on/off by OS), responsiveness (CS exit latency <500ms with WWAN), Selective Suspend, USB Low Power Mode (L0 and L1), DTPF (Dynamic TX Power and Thermal Framework) and WOd (WiFi offload).


6.2.15 Global Navigation Satellite System (GNSS)

MSFT removed the requirement of GNSS being implemented as a separate end-point that can be taken to low power state independently for Window 8.1.

The current platform POR is to support both discrete Global Navigation Satellite System (GNSS) on the motherboard for the SKUs without WWAN and GNSS embedded into M.2 module with WWAN for the SKUs with WWAN. Intel CG2000 will be used for discrete GNSS and owned by IMC/MCG. Using CG2000 for all SKUs or only APAC SKUs is TBD. For discrete GNSS, Intel CG2000 is POR solution

6.2.16 NFC

NFC is implemented in the Skylake platform as a discrete NFC part connected over SMLink0 to the PCH. This PCH connection is a private bus that is serviced by an NFC driver running within the system CSME. This private channel allows secure access to NFC through the DAL/JVM which is leveraged by Intel’s Identity Protection Technology, which enables secure payment models. The current POR NFC solution is from NXP.

6.2.17 WiGiG/ WiDock

WiGig solution for Skylake is under re-plan. This section will be updated based on the final POR.

WiGig is a multi-gigabit speed, directional wireless communications technology. Given its short range and directional transmission nature, WiGig is not positioned as a general replacement to WiFi, but is instead being used as a wireless docking technology. When in close proximity to a WiGig dock device (which also includes an Rx/Tx antenna), the system will establish a high speed interconnect over which Display Port, Ethernet/IP (over USB), and USB traffic is bridged between the host device and the sink (dock/receiver) device

The following below table lists the Connectivity features that have System Level impact and other details of Connectivity Test Plan:

S. No. Features Timeline SKU Platform Supportability

LAN1 GbE MAC PreAlpha CS & NCS All2 PXE ROM PreAlpha CS & NCS All3 Sx System Cycling PreAlpha CS & NCS All4 WOL PreAlpha CS & NCS All5 CPPM LTR PreAlpha CS All6 Jumbo Frames PreAlpha CS & NCS All7 Deep Sx Wake PreAlpha CS & NCS AllBluetooth

1 Bluetooth Support (BT 4.1) PreAlpha CS & NCS All2 BLE PreAlpha CS & NCS All3 BT WiFi Co-ex Alpha CS & NCS All4 BT WiFi LTE Co-ex Beta CS & NCS All5 BT Profiles (FTP,BPP,HFP) PreAlpha CS & NCS All6 BT AD2P (SBC) PreAlpha CS All7 USB 2.0 SS & LPM L1 PreAlpha CS & NCS All


Table 6-4. Connectivity Features

S. No. Features Timeline SKU Platform Supportability

WiFi1 Wifi Direct Service Discovery PreAlpha CS & NCS All2 WiDi 5.x PreAlpha CS & NCS All3 Miracast Support PreAlpha CS & NCS All4 Wake on WLAN PreAlpha CS & NCS All5 Airplane Mode ON/OFF PreAlpha CS & NCS All6 RF Kill PreAlpha CS & NCS All7 WiFi AOAC Support PreAlpha NCS All8 Runtime D3 for PCIe devices Alpha CS & NCS All9 PCIe LTR Support Alpha CS All10 CSME and iSCT Coex PreAlpha NCS All

11 AMT CS additions (Wowlan and NS offload) PreAlpha CS All

12 Comms Hub (Location) Alpha CS & NCS All

13Comms Hub (Offload Engine connectivity Interface to Sensor Hub)

Alpha CS & NCS All

NFC1 Active Mode of Operation Alpha CS & NCS All2 Passive Mode of Operation NA NA NA3 Reader/Writer Mode Alpha CS & NCS All4 Peer-to-Peer Mode (P2P mode) Alpha CS & NCS All5 Card Emulation Mode NA NA NA

6.2.18 Graphics, Multimedia, and Imaging

6.2.19 Overview

This Test plan covers various aspects of Graphics such as 2D, 3D, Metro games, Legacy games, Modern UI across single, multi-display configurations, display hot plugs, display swaps with active 2D, 3D workloads, and power management scenarios such as PSR. For Skylake platform, new test cases are created for the new POR features such as SVC/VP8/Open CL2.0/OGL4.2/video preview/enhanced LPSP/enhanced tessellation and so on. From IGD driver 15.33 branch WiDi driver components will be part of IGD driver package (Win8.1*) and new Test content is created for Miracast feature. For Switchable Graphics AMD, Graphics cards are covered (ULT/Halo configurations). SG is not POR for ULX and hence not covered at PSTV.

RVP configuration will have POR cameras and audio sink devices as per configuration plan. Under multimedia, test plan covers media playback over different display devices such as HDMI 1.4/DP 1.2/eDP1.4 and WiDi display. Source content includes protected (Intel insider)/non-protected (YouTube*/ videos with different codecs)/HTML5/Stereo 3D/Blue ray disks and so on. Top use case scenarios covered are VOIP/Transcoding/camera capturing and so on. Standard desktop applications such as Power DVD/WinDVD/ Media Expresso* applications are covered under multimedia. For Audio validation covering ALC286S external codec on ULT configuration, IDT ACS6220 codec will be onboard codec on ULX PV board configuration and codec ALC 282 is


covered for Non CS configurations. For Skylake, new test cases are created for audio pre/post processing features

6.2.20 Feature List

The following table lists the features and other details of Graphics, Multimedia, and WiDi Test Plan:

Sl. No.

Features Timeline Scope SKU Platform Supportability

1 3 (Symmetric) Pipe Support PO Platform CS & NCS All

2 Protected Playback (HDCP, dual HDCP) PO Platform CS & NCSAll

3 iHDMI 1.4 PO Platform CS & NCS All

4 Dual-display configuration PO Platform CS & NCS All

5 Panel fitting/Scaling PO Platform CS & NCS All

7 Rotation PreAlpha Platform CS & NCS All

11 Docking/undocking, Hot-plug/Unplug, Lid events, AC/DC Switching, Hotkeys PO Platform CS & NCS All

12 Panel Self Refresh (PSR) for eDP PO Platform CS & NCS All

13 Low Power Single Pipe (LPSP) PO Platform CS & NCS All

14 DP 1.2 PO Platform CS & NCS All

16 S3D PreAlpha Platform CS & NCS All

17 WiDi Alpha Platform CS & NCS All

18 Microsoft DirectX 9 PO Platform CS & NCS All

19 Microsoft DirectX10 PO Platform CS & NCS All

21 Microsoft DirectX11 PO Platform CS & NCS All

22 Microsoft DirectX11.1 PO Platform CS & NCS All

27 OpenGL 4.0 PO Platform CS & NCS All

28 OpenGL 4.1 Alpha Platform CS & NCS All

29 OpenGL 4.2 Alpha Platform CS & NCS All

31 OpenCL 1.2 (Windows*/Apple*) PO Platform CS & NCS All

32 OCL 2.0 (Windows*/Apple*) Beta Platform CS & NCS ULT, HALO

36 Overlay PO Platform CS & NCS All

38 IECP - TCC (Total Color Control) PO Platform CS & NCS All

39 IECP - ACE (Adaptive Contrast Enhancement) PO Platform CS & NCS All

48 Adaptive Video Scaling PO Platform CS & NCS All


Multim

Sl. No.


51 PAVP Heavy mode PreAlpha Platform CS & NCS All

53 Decode: VC1 PO Platform CS & NCS All

54 Decode: VC1 Intel GUID PO Platform CS & NCS All

55 Decode: JPEG PO Platform CS & NCS All

56 Decode: MVC PO Platform CS & NCS All

57 Decode: VC1 IT PO Platform CS & NCS All

58 Deocde: MPEG2 IT PO Platform CS & NCS All

59 Decode: AVC, VC1 & MPEG2 PO Platform CS & NCS All

60 Decode: SVC PO Platform CS & NCS All

61 Encode: (MPEG2, AVC) CQP PO Platform CS & NCS All

62 Encode: AVC CQP Multi ref PO Platform CS & NCS All

63 Encode: MPEG2 BRC PO Platform CS & NCS All

65 SVC Encode MB BRC PO Platform CS & NCS All

66 Transcode PO Platform CS & NCS All

67 PAVP Alpha Platform CS & NCS All

68 Media Vault Alpha Platform CS & NCS All

69 Audio: LPAL (Win8.1*) Alpha Platform CS & NCS All

70 Audio: Post-processing (Win8.1*) Alpha Platform CS & NCS All

71 WiDi Alpha Platform CS & NCS All

72 SG Alpha Platform NCS All


MultimMultim

6.2.21 Storage

6.2.22 Overview

The RST14.0 Product utilizes the RST 13.0 Storport based architecture on the client RST feature baseline. All current RST13.0 client functionality is maintained as is power and IO performance. RST13.0 is about supporting new storage Transports for advanced use cases covering NVMExpress and PCIe connected SSDs. With the introduction of PCIe SSDs based on the NVMExpress interface, RST13.0 will support the use of these new devices for SRT.

The new NVM technology, SXP, is paired with the NVMExpress high performance interface to provide next generation SSD performance. With Lynx Pt SDV silicon, two x1 gen2 PCIe lanes can be remapped to a single AHCI port. The PCIe SSD device can be re-mapped (@gen2 PCI speeds = 500MBps/1000MBps) under the AHCI Controller of the PCH which allows our existing RST Miniport driver to be utilized with re-mapped PCIe SSDs.

While it is intended that the NVMe transport to be utilized with SXP devices, it is also possible to utilize NVMe with NAND (that is, Fultondale). The RST implementation is tied to the use of the NVMe transport for PCIe SSDs and is not reliant on the underlying NVM Memory technology.

RST13.0 will utilize the SRT components to handle SRT Use Cases. The existing AHCI Miniport is updated to include minor changes in logic to handle minor architectural changes with the re-mapped PCIe SSDs. The addition of the NVMExpress Miniport driver as part of the RST AHCI Miniport driver binary is used to handle NVMExpress devices with remapping gates utilized.

6.2.23 Feature List

The following table lists the features and other details of Storage Test Plan:

Sl. No.


Legacy

1 RST Caching PreAlpha Platform NCS All

2 Zero Power ODD PreAlpha Platform CS & NCS All

3 RAID 0, 1, 5, 10 PreAlpha Platform NCS All

4 Supports SATA (Gen2/Gen3), eSATA PreAlpha Platform CS &

NCS All

5 Supports SSD PreAlpha Platform CS & NCS ULT

6 Fast Sync


Sl. No.


7 Lake Tiny PreAlpha Platform NCS Halo

8 RST UEFI PreAlpha Platform CS & NCS All

9 RRT – Rapid Recovery PreAlpha Platform NCS All

10 DEVSLP PreAlpha Platform CS & NCS All

11 RST Support for RTD3 PreAlpha Platform CS & NCS All

15 Link Power Management PreAlpha Platform CS & NCS All

17 Hybrid Hint PreAlpha Platform NCS ULT, HALO

18 PCIe NAND Remapping PreAlpha Platform CS & NCS All

6.2.24 Thermal

6.2.25 Overview

Thermal management consists of a way to sense temperature and a means to reduce the temperature if it is above a specified limit. For each major component of the platform, thermal management is available to the user to implement into their system design ensuring sufficient platform cooling. This document helps the user to understand thermal management behavior and how to enable each form of management for the following platform components:

Processor (IA Core and GT Core)

Platform Controller Hub

System Memory

All thermal management reduces performance in order to reduce temperature.

Skylake Client platforms:

Feature Digital Thermal Sensors (DTS) located on the IA cores, graphics core, system agent, L4 Cache (4+3e only), and PCH

Supports the use of thermal sensors placed either near the memory DIMM modules or the motherboard down chips

Supports additional thermal sensors which can be connected to the system Embedded Controller (EC) through SMBus

Any of these devices report temperatures that can be used to initiate fan control and thermal throttling when necessary.


Dynamic Platform Thermal Framework (DPTF) is a software agent that actively manages power levels of various platform components to maintain tolerable operating temperatures within the system. The system is composed of a series of “participants” and “policies” that are orchestrated by a central DPTF framework. Each participant is responsible for managing a specific component within the system. It exposes interfaces that either monitor power and temperature data from the component or adjusts power consumption of the device.

In addition to the passive cooling policy, DPTF has the critical temperature policy. This policy acts when any participant exceeds the critical temperature limit. DPTF attempts to gracefully shut down the system through operating system mechanisms. This is intended to occur before EC shutdown methods are engaged, which are more likely to result in lost data.

The list of participants is as follows:

Generic

Soc (Core, GFX, PCH)

Memory

Display

WiGig/ WiFi

WWAN

SSD

PerC

In addition to DPTF, Wilson beach will have critical thermal events monitored by the Embedded Controller EC. These critical thermal safeguards are in place for situations when the DPTF software or the operating system is not running.

To perform this, the EC monitors both the SoC temperature as well as the system skin temperatures

6.2.26 Feature List

The following table lists the features and other details of Thermal Test Plan:

Sl. No.


1 DPTF PreAlpha Platform CS & NCS All

2 Thermal Control Circuit PreAlpha Platform CS & NCS All

3 Adaptive Thermal Monitoring PreAlpha Platform CS & NCS All

4 Converged Platform power thermal Throttling (CPTT) PreAlpha Ingredient CS & NCS All

5 Platform Environment Control Interface PreAlpha Ingredient CS & NCS All

6 PCH Specific Thermal Management PreAlpha Platform CS & NCS All


Thermal

Sl. No.


7 Safety Net Validation PreAlpha Platform CS & NCS

DPTF

1 DPPM.Active policy PreAlpha Platform CS & NCS All

2 DPPM.Passive Policy 2.0 PreAlpha Platform CS & NCS All

3 DPPM.Critical Policy PreAlpha Platform CS & NCS All

4 DPPM.Cooling mode policy PreAlpha Platform CS & NCS All

5 Dynamic Battery power technology (DBPT) PreAlpha Platform CS & NCS All

6 cTDP PreAlpha Platform CS & NCS All

9 LPM PreAlpha Platform CS & NCS All

CPTT

1 Open Loop thermal Management (OLTM) PreAlpha Ingredient CS & NCS All

2 Closed Loop thermal Management (CLTM) PreAlpha Ingredient CS & NCS All

6.2.27 Cycling

6.2.28 Overview

The Skylake-Y/U/Halo platform will support most of the traditional global power states as well as Connected Standby based on ACPI rev. 5.0. Also, if this is a mobile platform, it will support AC and DC power options. The power states that will be supported are S0, S3, S4, S5, DeepSx, and warm reset. SKL-U/Y and Halo platform will support connected standby (Instant Go). In addition, both legacy power states and connected standby can be triggered in an automated/command fashion, user intervention via physical button, OS interface or system setting.

Testing an Additional Power Flows:

Apart from the general power flows, the following power scenarios on RVP are also covered:

1. S3 & S4 with Stress Test2. S0->DS3->S3->S03. S0->DS4->S4->S04. S0->DS5->S5->S05. S3 Cycling with AMT Configured6. S4 Cycling with AMT Configured7. AC->DC Switching with Video Playback


Thermal Thermal

6.2.29 Feature List

The following table lists the features and other details of Cycling Test Plan:

Sl. No.


1 S3 PreAlpha Platform NCS All

2 S4 PreAlpha Platform CS & NCS All

3 S5 PreAlpha Platform CS & NCS All

4 Deep S3 PreAlpha Platform NCS All

5 FF Deep S4 PreAlpha Platform CS & NCS All

6 FF Deep S5 PreAlpha Platform CS & NCS All

7 AC/DC PreAlpha Platform CS & NCS All

8 CS PreAlpha Platform CS ULT,ULX & Halo

9 CSME Power States PreAlpha Ingredient CS & NCS All

6.2.30 Responsiveness

6.2.31 Overview

Responsiveness is user perceived performance-. It is the specific ability of a system or functional unit to complete the assigned tasks within a given time.

Benefit of Responsiveness:

Diagnose potential problems

Diagnose inconsistent behavior.

Diagnose HW/SW Poor design.

Meeting end user expectation.

Diagnose compatibility issues of the system.

Meeting MSFT/Google/Apple certification requirements

6.2.32 Feature List

The following table lists the features and other details of Responsiveness Test Plan:


Cycling

Sl. No.


1 Hibernate Alpha Platform CS & NCS All

2 Fast startup Alpha Platform CS & NCS All

3 Standby Alpha Platform NCS All

4 First boot Alpha Platform CS & NCS All

5 Full boot Alpha Platform CS & NCS All

6 File handling Alpha Platform CS & NCS All

7 Windows* UI performance Alpha Platform CS & NCS All

8 Photo handling Alpha Platform CS & NCS All

9 Media transcode performance Alpha Platform CS & NCS All

10 Internet Explorer Startup Performance Alpha Platform CS & NCS All

11 Internet Explorer Browsing Performance Alpha Platform CS & NCS All

12 Windows* media Player performance Alpha Platform CS & NCS All

13 Streaming Media Performance Alpha Platform CS & NCS All

14 CS Alpha Platform CS All


Resp

vene