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CS-328 Computer Architecture

Week-1Digital Computer:

Imply that the computer deals with digital information, i.e., it deals with the information that is represented by binary digits

Why BINARY? Instead of Decimal or other number system?

* Consider electronic signal

In above the seven bits 1001011 represents a binary number whose decimal equivalent is 75.

Computer System divided into

Hardware – consist of all the electronics components and electromechanical devices that comprise the physical entity of the device.

Software – consists of the instructions and data that the computer manipulates to perform various data processing tasks.

By Dr. Nitin S. Goje | 91


Block Diagram of Digital Computer:

Computer Organization

concerned with the way hardware components operate

the way they are connected together to form the computer system

Computer Design

concerned with the hardware design of the computer

Computer Architecture

concerned with the structure and behavior of the computer as seen by the user

It includes the information formats, the instruction set and techniques for addressing memory.

Logic Gates:

Types of Basic Logic Blocks

Combinational Logic Block



Logic Blocks whose output logic value depends only on the input logic values

Sequential Logic Block

Logic Blocks whose output logic value depends on the input values and the state (stored information) of the blocks

Functions of Gates can be described by

Truth Table

Boolean Function

Karnaugh Map

Boolean Algebra:

Boolean Algebra

Algebra with Binary(Boolean) Variable and Logic Operations



Boolean Algebra is useful in Analysis and Synthesis of Digital Logic Circuits

Input and Output signals can be represented by Boolean Variables, and

Function of the Digital Logic Circuits can be represented by Logic Operations, i.e., Boolean Function(s)

From a Boolean function, a logic diagram can be constructed using AND, OR, and Inverter

Truth Table

The most elementary specification of the function of a Digital Logic Circuit is the Truth Table

Table that describes the Output Values for all the combinations of the Input Values, called MINTERMS

n input variables --> 2n minterms

Logic Circuit Design:



Examples:

Here are some logic gate circuit problems:

Draw a logic circuit for (A + B)C.

Draw a logic circuit for A + BC + D’.

Draw a logic circuit for AB + (AC)’.

Draw a logic circuit for (A + B)’(C + D)C’.



Basic Identities of Boolean Algebra:

Usefulness of this Table

Simplification of the Boolean function

Derivation of equivalent Boolean functions to obtain logic diagrams utilizing different logic gates

Ordinarily ANDs, ORs, and Inverters

But a certain different form of Boolean function may be convenient to obtain circuits with NANDs or NORs

Applications of DeMorgans Theorem

x’y’ = (x + y)’ x’+ y’= (xy)’

I, AND --> NOR I, OR --> NAND

Examples:

i) A+AB = AProof. A+AB = A.1 + AB [A.1 = A]= A(1+B) [Since, 1 + B = 1]= A.1 = A



ii) A(A+B) = AProof. A(A+B) = A.A + A.B= A+AB [Since, A.A = A]= A(1+B)= A.1= A

iii) A+A’B = A+BProof A+A’B = (A+A’) [Since, A+BC = (A+B)(A+C) using distributive law.]= 1 (A+B) [Since, A+A’ = 1]= A+B

iv) A.(A’+B) = ABProof A.( A’+B) = A. A’+AB= AB [AA’ = 0]

Equivalent Circuits:

Many different logic diagrams are possible for a given Function


F = ABC + ABC’ + A’C .......…… (1) = AB(C + C’) + A’C [13] ..…. (2) = AB • 1 + A’C [7] = AB + A’C [4] ...…. (3)


Week-2Karnaugh Maps for SimplificationKarnaugh Maps:

Boolean algebra helps us simplify expressions and circuits

Karnaugh Map: A graphical technique for simplifying a Boolean expression into either form:

minimal sum of products (MSP)

minimal product of sums (MPS)

Goal of the simplification.

There are a minimal number of product/sum terms

Each term has a minimal number of literals

Circuit-wise, this leads to a minimal two-level implementation



Re-arranging the Truth Table

A two-variable function has four possible minterms. We can re-arrange these minterms into a Karnaugh map

Now we can easily see which minterms contain common literals

Minterms on the left and right sides contain y’ and y respectively

Minterms in the top and bottom rows contain x’ and x respectively

A Three - Variable Karnaugh M ap

For a three-variable expression with inputs x, y, z, the arrangement of minterms is more tricky:



Another way to label the K-map (use whichever you like):

Reading the MSP from the K-map

You can find the minimal SoP expression

Each rectangle corresponds to one product term

The product is determined by finding the common literals in that rectangle

K-map Simplification of SoP Expressions

Let’s consider simplifying f(x,y,z) = xy + y’z + xz

Here is the truth table and sum of minterms for our example:



Truth Table notation for Minterms and Maxterms

Minterms and Maxterms are easy to denote using a truth table.

Example: Assume 3 variables x,y,z (order is fixed)

Making the Example K-map

In our example, we can write f(x,y,z) in two equivalent ways



In either case, the resulting K-map is shown below

Practice K-map 1

Simplify the sum of minterms m1 + m3 + m5 + m6

Solutions for Practice K-map 1

Here is the filled in K-map, with all groups shown

The magenta and green groups overlap, which makes each of them as large as possible

Minterm m6 is in a group all by its lonesome

The final MSP here is x’z + y’z + xyz’

K-maps can be tricky!

There may not necessarily be a unique MSP. The K-map below yields two valid and equivalent MSPs, because there are two possible ways to include minterm m7


Y0 1 0 0

X 0 1 1 1Z

Y0 1 1 0

X 0 1 0 1Z


Remember that overlapping groups is possible, as shown above

Four-variable K-maps – f(W,X,Y,Z)

The min terms in the third and fourth columns, and in the third and fourth rows, are switched around.

Again, this ensures that adjacent squares have common literals

Grouping minterms is similar to the three-variable case, but:

You can have rectangular groups of 1, 2, 4, 8 or 16 minterms

You can wrap around all four sides



Example: Simplify m0+m2+m5+m8+m10+m13

x’z’ + xy’z



F ive -variable K-maps – f(V,W,X,Y,Z)

Simplify f(V,W,X,Y,Z)= Σ m(0,1,4,5,6,11,12,14,16,20,22,28,30,31)



PoS Optimization

Maxterms are grouped to find minimal PoS expression

PoS Optimization from SoP

F(W,X,Y,Z)= Σm(0,1,2,5,8,9,10)

= ∏ M(3,4,6,7,11,12,13,14,15)

F(W,X,Y,Z)= (W’ + X’)(Y’ + Z’)(X’ + Z)

Or,

F(W,X,Y,Z)= X’Y’ + X’Z’ + W’Y’Z

Which one is the minimal one?

SoP Optimization from PoS

F(W,X,Y,Z)= ∏ M(0,2,3,4,5,6)

= Σm(1,7,8,9,10,11,12,13,14,15)


00000

0 000


F(W,X,Y,Z)= W + XYZ + X’Y’Z

I don’t care!

You don’t always need all 2n input combinations in an n-variable function

If you can guarantee that certain input combinations never occur

If some outputs aren’t used in the rest of the circuit

We mark don’t-care outputs in truth tables and K-maps with Xs.

x y z f (x,y,z)0 0 0 00 0 1 10 1 0 X0 1 1 01 0 0 01 0 1 11 1 0 X1 1 1 1

Within a K-map, each X can be considered as either 0 or 1. You should pick the interpretation that allows for the most simplification.



IMPLEMENTATION OF K-MAPS - Sum-of-Products Form -

Logic function represented by a Karnaugh map can be implemented in the form of I-AND-OR

A cell or a collection of the adjacent 1-cells can be realized by an AND gate, with some inversion of the input variables.

IMPLEMENTATION OF K-MAPS - Product-of-Sums Form –

Logic function represented by a Karnaugh map can be implemented in the form of I-OR-AND

If we implement a Karnaugh map using 0-cells, the complement of F, i.e., F’, can be obtained.

Thus, by complementing F’ using DeMorgan’s theorem F can be obtained

F(x,y,z) = (0,2,6)



IMPLEMENTATION OF K-MAPS - Don’t-Care Conditions –

In some logic circuits, the output responses for some input conditions are don’t care whether they are 1 or 0.

In K-maps, don’t-care conditions are represented by d’s in the corresponding cells.

Don’t-care conditions are useful in minimizing the logic functions using K-map.

- Can be considered either 1 or 0

- Thus increases the chances of merging cells into the larger cells

--> Reduce the number of variables in the product terms



Week-3Von Neumann Machine Architecture and its Functions:

Von Neumann Architecture consists of mainly 5 parts.

Input

Output device

Central Processing unit (C.P.U.)

Arithmetic Logic Unit (A.L.U).

Control Unit (C.U.)

Memory Unit (M.U)

Output Device: It is used to display the result, Eg: Monitor, printer and so on.

Input Device: It is used to enter the data, Eg. Keyboard, mouse and so on.

Central Processing Unit : (C.P.U.)

Memory Unit (M.U.): It is used to store the data in the form of binary bits.

Data from the keyboard transfers to memory.



Memory of 2 types

Primary Memory: Used to store the data temporarily.eg. Main memory ,RAM, SRAM, DRAM.

Secondary memory : Used to store the data permanently. eg. Magnetic disks, magnetic bubbles and drums.

Computer Architecture

• Refers to specification of the relationship between different hardware components of a computer system.

• It defines high and low level of abstractions.

At high level CPU is presented and low level its parts like ALU,MU,CU represented

Computer Organization

Organization is how features are implemented

Control signals, interfaces, memory technology.

e.g. Is there a hardware multiply unit or is it done by repeated addition?

Computer organization is a study of a Computer Architecture. E.g. Memory, Registers, RAM, ROM, CPU, ALU, 16 bit/ 32 bit/ 64 bit architecture, what different parts makes a computer, etc.

Programming Languages

There are 4 types of programming languages.

High Level Language

Middle Level Language

Low Level Language

Assembly Level Language.



Compiler : It is used to translate the High level language (English statements) to low level language (1‘s 0’s). Compile entire program once at time. eg. Pascal, Basic, Fortran and so on.

Interpreter : Used to translate the program high level language into low level language. It translates instruction by instruction.eg. Java

Assembler : Used to translate the Assembly level language (Mnemonics) into low level language.

Microprocessor: This is a smallest part of the processor which performs the following functions like

Storing data

Transferring

Performing Arithmetic and logical operations.

Shift Operations and so on.

Eg: 8086,80386.



Week-4Data Representations

Computer – Number System:

When we type some letters or words, the computer translates them in numbers as computers can understand only numbers.

A computer can understand positional number system where there are only a few symbols called digits and these symbols represent different values depending on the position they occupy in the number.

A value of each digit in a number can be determined using

The digit

The position of the digit in the number

The base of the number system (where base is defined as the total number of digits available in the number system).

Decimal Number System:

The number system that we use in our day-to-day life is the decimal number system.

Decimal number system has base 10 as it uses 10 digits from 0 to 9.

In decimal number system, the successive positions to the left of the decimal point represent units, tens, hundreds, thousands and so on.

(1x1000)+ (2x100)+ (3x10)+ (4xl)

(1x103)+ (2x102)+ (3x101)+ (4xl00)

1000 + 200 + 30 + 4

1234

As a computer programmer or an IT professional, you should understand the following number systems which are frequently used in computers.



S.N. Number System and Description

1 Binary Number System

Base 2. Digits used : 0, 1

2 Octal Number System

Base 8. Digits used : 0 to 7

3 Hexa Decimal Number System

Base 16. Digits used : 0 to 9, Letters used : A- F

Common Number Systems:

Quantities/Counting:



Binary Number System:By Dr. Nitin S. Goje | 91


Characteristics of binary number system are as follows:

Uses two digits, 0 and 1.

Also called base 2 number system

Each position in a binary number represents a 0 power of the base (2). Example 20

Last position in a binary number represents a x power of the base (2). Example 2x where x represents the last position - 1.

Example

Binary Number : 101012

Calculating Decimal Equivalent:

Step Binary Number

Decimal Number

Step 1 101012 ((1 x 24) + (0 x 23) + (1 x 22) + (0 x 21) + (1 x 20))10

Step 2 101012 (16 + 0 + 4 + 0 + 1)10

Step 3 101012 2110

Note : 101012 is normally written as 10101.

Octal Number System: Characteristics of octal number system are as follows:

Uses eight digits, 0,1,2,3,4,5,6,7.


Example

Octal Number : 125708




Step Octal Number Decimal Number

Step 1 125708 ((1 x 84) + (2 x 83) + (5 x 82) + (7 x 81) + (0 x 80))10

Step 2 125708 (4096 + 1024 + 320 + 56 + 0)10

Step 3 125708 549610

Note : 125708 is normally written as 12570.

Hexadecimal Number System: Characteristics of hexadecimal number system are as follows:

Uses 10 digits and 6 letters, 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F.

Letters represents numbers starting from 10. A = 10. B = 11, C = 12, D = 13, E = 14, F = 15.


Example

Hexadecimal Number : 19FDE16


Step Binary Number

Decimal Number

Step 1 19FDE16 ((1 x 164) + (9 x 163) + (F x 162) + (D x 161) + (E x 160))10

Step 2 19FDE16 ((1 x 164) + (9 x 163) + (15 x 162) + (13 x 161) + (14 x 160))10

Step 3 19FDE16 (65536+ 36864 + 3840 + 208 + 14)10

Step 4 19FDE16 10646210



Computer – Number Conversion: There are many methods or techniques which can be used to convert numbers from one

base to another. We'll demonstrate here the following:

Decimal to Other Base System

Other Base System to Decimal

Other Base System to Non-Decimal

Shortcut method - Binary to Octal

Shortcut method - Octal to Binary

Shortcut method - Binary to Hexadecimal

Shortcut method - Hexadecimal to Binary

Decimal to Other Base System Steps

Step 1 - Divide the decimal number to be converted by the value of the new base.

Step 2 - Get the remainder from Step 1 as the rightmost digit (least significant digit) of new base number.

Step 3 - Divide the quotient of the previous divide by the new base.

Step 4 - Record the remainder from Step 3 as the next digit (to the left) of the new base number.

Repeat Steps 3 and 4, getting remainders from right to left, until the quotient becomes zero in Step 3.

The last remainder thus obtained will be the most significant digit (MSD) of the new base number.

Example:

Decimal Number : 2910

Calculating Binary Equivalent:



As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so that the first remainder becomes the least significant digit (LSD) and the last remainder becomes the most significant digit (MSD).

Decimal Number : 2910 = Binary Number : 111012.

Other Base System to Decimal system Steps

Step 1 - Determine the column (positional) value of each digit (this depends on the position of the digit and the base of the number system).

Step 2 - Multiply the obtained column values (in Step 1) by the digits in the corresponding columns.

Step 3 - Sum the products calculated in Step 2. The total is the equivalent value in decimal.

Example:



Binary Number : 111012 = Decimal Number : 2910



Other Base System to Non-Decimal System Steps

Step 1 - Convert the original number to a decimal number (base 10).

Step 2 - Convert the decimal number so obtained to the new base number.

Example:

Octal Number : 258


Step 1 : Convert to Decimal

Octal Number : 258 = Decimal Number : 2110

Step 2 : Convert Decimal to Binary

Decimal Number : 2110 = Binary Number : 101012

Octal Number : 258 = Binary Number : 101012



Shortcut Method – Binary to Octal Steps

Step 1 - Divide the binary digits into groups of three (starting from the right).

Step 2 - Convert each group of three binary digits to one octal digit.

Example:


Calculating Octal Equivalent:

Binary Number : 101012 = Octal Number : 258

Shortcut Method – Octal to Binary Steps

Step 1 - Convert each octal digit to a 3 digit binary number (the octal digits may be treated as decimal for this conversion).

Step 2 - Combine all the resulting binary groups (of 3 digits each) into a single binary number.

Example:

Octal Number : 258


Octal Number : 258 = Binary Number : 101012



Shortcut Method – Binary to Hexadecimal Steps

Step 1 - Divide the binary digits into groups of four (starting from the right).

Step 2 - Convert each group of four binary digits to one hexadecimal symbol.

Example:


Calculating hexadecimal Equivalent:

Binary Number : 101012 = Hexadecimal Number : 1516

Shortcut Method – Hexadecimal to Binary Steps

Step 1 - Convert each hexadecimal digit to a 4 digit binary number (the hexadecimal digits may be treated as decimal for this conversion).

Step 2 - Combine all the resulting binary groups (of 4 digits each) into a single binary number.

Example

Hexadecimal Number : 1516




Hexadecimal Number : 1516 = Binary Number : 101012

Exercise – Convert:



Signed Binary Numbers:Possible representations:

Binary Arithmetic:1. Binary Addition:

Rules of Binary Addition

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0, and carry 1 to the next more significant bit



00010011 + 00111110 = 01010001 1 1 1 1 1 carries 0 0 0 1 0 0 1 1 = 19(base 10) + 0 0 1 1 1 1 1 0

= 62(base 10)

0 1 0 1 0 0 0 1 = 81(base 10)

Note: The rules of binary addition (without carries) are the same as the truths of the XOR gate.

2. Binary Subtraction:

00110011 - 00010110 = 00011101 0 10 1 borrows 0 0 1 1 0 10 1 1 = 51(base 10) - 0 0 0 1 0 1 1 0

= 22(base 10)

0 0 0 1 1 1 0 1 = 29(base 10)



3. Binary Multiplication:



4. Binary Division :

Binary division is the repeated process of subtraction, just as in decimal division.

For example,

00101010 ÷ 00000110 = 00000111

1 1 1 = 7(base 10)

1 1 0 ) 0 0 1 10 1 0 1 0 = 42(base 10)

- 1 1 0 = 6(base 10)

1 borrows

1 0 10 1 - 1 1 0

1 1 0

- 1 1 0

0

10000111 ÷ 00000101 = 00011011

1 1 0 1 1 = 27(base 10)

1 0 1 ) 1 0 0 10 0 1 1 1 = 135(base 10)

- 1 0 1 = 5(base 10)

1 1 10 - 1 0 1 1 1 - 0

1 1 1 - 1 0 1

1 0 1

- 1 0 1

0

Negative Numbers:



Sign-and-Magnitude Negative numbers are usually written by writing a minus sign in front.

Example:

- (12)10 , - (1100)2

In sign-and-magnitude representation, this sign is usually represented by a bit:

0 for +

1 for -

Example: an 8-bit number can have 1-bit sign and 7-bit magnitude.

1s and 2s Complement: Two other ways of representing signed numbers for binary numbers are:

1s-complement

2s-complement

They are preferred over the simple sign-and-magnitude representation.

1s Complement Given a number x which can be expressed as an n-bit binary number, its negative value

can be obtained in 1s-complement representation using:

- x = 2n - x - 1

Example: With an 8-bit number 00001100, its negative value, expressed in 1s complement, is obtained as follows:

-(00001100)2 = - (12)10

= (28 - 12 - 1)10

= (243)10

= (11110011)1s

Essential technique: invert all the bits.By Dr. Nitin S. Goje | 91


Examples: 1s complement of (00000001)1s = (11111110)1s

1s complement of (01111111)1s = (10000000)1s

Largest Positive Number: 0 1111111 +(127)10

Largest Negative Number: 1 0000000 -(127)10

Zeroes: 0 0000000

1 1111111

Range: -(127)10 to +(127)10

The most significant bit still represents the sign:

0 = +ve; 1 = -ve.

Examples (assuming 8-bit binary numbers):

(14)10 = (00001110)2 = (00001110)1s

-(14)10 = -(00001110)2 = (11110001)1s

-(80)10 = -( ? )2 = ( ? )1s

2s Complement Given a number x which can be expressed as an n-bit binary number, its negative

number can be obtained in 2s-complement representation using:

- x = 2n - x

Example: With an 8-bit number 00001100, its negative value in 2s complement is thus:

-(00001100)2 = - (12)10

= (28 - 12)10

= (244)10

= (11110100)2s

Essential technique: invert all the bits and add 1.

Examples:

2s complement of

(00000001)2s = (11111110)1s (invert)



= (11111111)2s (add 1)

2s complement of

(01111110)2s = (10000001)1s (invert)

= (10000010)2s (add 1)

Largest Positive Number: 0 1111111 +(127)10

Largest Negative Number: 1 0000000 -(128)10

Zero: 0 0000000

Range: -(128)10 to +(127)10

The most significant bit still represents the sign:

0 = +ve; 1 = -ve.

Examples (assuming 8-bit binary numbers):

(14)10 = (00001110)2 = (00001110)2s

-(14)10 = -(00001110)2 = (11110010)2s

-(80)10 = -( ? )2 = ( ? )2s

Week-5Register Transfer & Micro Operations



Register: Register is one of a small set of data holding places that are part of a

computer processor. A register may hold a computer instruction, a storage address, or any kind of data.

Registers of the 8086/80286

Intel 16-Bit Registers - General Purpose



General Purpose Registers AX (Accumulator) – favored by CPU for arithmetic operations

BX – Base – can hold the address of a procedure or variable (SI, DI, and BP can also). Can also perform arithmetic and data movement.

CX – acts as a counter for repeating or looping instructions.

DX – holds the high 16 bits of the product in multiply (also handles divide operations)

Intel 16-Bit Registers - Segment

Segment Registers



Used as base locations for program instructions, data and the stack

CS – Code Segment – holds base location for all executable instructions in a program

SS - Stack Segment – Base location of the stack

DS – Data Segment – default base location for variables

ES – Extra Segment – additional base location for memory variables.

Intel 16-Bit Registers – Index

Index Registers Contain the offset of data(variables, labels) and instructions from its base segment.

BP – Base Pointer – contains an assumed offset from the SS register. Often used by a subroutine to locate variables that were passed on the stack by a calling program.

SP – Stack Pointer – Contains the offset of the top of the stack.

Speed up processing of strings, arrays, and other data structures containing multiple elements.

SI – Source Index – Used in string movement instructions. The source string is pointed to by the SI register.

DI – Destination Index – acts as the destination for string movement instructions

Intel 16-Bit Registers - Status and Control



Status and Control Registers IP – Instruction Pointer – contains the offset of the next instruction to be executed.

Flags Register – individual bit positions within register show status of CPU or results of arithmetic operations.

Control Flags (Direction, Interrupt, Trap)

Status Flags (Carry, Overflow, Sign, Zero, Auxiliary Carry, Parity)

Flags – Status Carry (CF) – set when the result of an unsigned arithmetic operation is too large to fit

into the destination.

Overflow(OF) – set when the result of a signed arithmetic operation is too wide to fit into the destination.

Sign(SF) – set when the result of an arithmetic or logical operation generates a negative result.

Zero(ZF) – set when the result of an arithmetic or logical operation is zero.

Instructions Sets Data Moving instructions

Memory to memory

Memory to registers

Registers to registers

Registers to memory

Data Moving Instructions



MOV: Move byte or word to register or memory

IN, OUT :Input byte or word from port, output word to port

LEA :Load effective address

LDS, LES :Load pointer using data segment, extra segment

PUSH, POP :Push word onto stack, pop word off stack

XCHG :Exchange byte or word

XLAT :Translate byte using look-up table

Arithmetic Instructions ADD, SUB Add, subtract byte or word

ADC, SBB Add, subtract byte or word and carry (borrow)

INC, DEC Increment, decrement byte or word

NEG Negate byte or word (two's complement)

CMP Compare byte or word (subtract without storing)

MUL, DIV Multiply, divide byte or word (unsigned)

IMUL, IDIV Integer multiply, divide byte or word (signed)

CBW, CWD Convert byte to word, word to double word (useful before multiply/divide)

AAA, AAS, AAM, AAD ASCII adjust for addition, subtraction, multiplication, division (ASCII codes 30-39)

DAA, DAS Decimal adjust for addition, subtraction (binary coded decimal numbers)

Logical Instructions NOT Logical NOT of byte or word (one's complement)

AND Logical AND of byte or word

OR Logical OR of byte or word

XOR Logical exclusive-OR of byte or word

TEST Test byte or word (AND without storing)

Logical Shifts



Logical shift – shifting left (LShiftL) and shifting right (LShiftR)

Rotate



Shift and Rotate InstructionsBy Dr. Nitin S. Goje | 91


SHL, SHR :Logical shift left, right byte or word by 1 or CL

SAL, SAR :Arithmetic shift left, right byte or word by 1 or CL

ROL, ROR :Rotate left, right byte or word by 1 or CL

RCL, RCR: Rotate left, right through carry byte or word by 1 or CL

Transfer instructions JMP Unconditional jump

JA (JNBE) Jump if above (not below or equal)

JAE (JNB) Jump if above or equal (not below)

JB (JNAE) Jump if below (not above or equal)

JBE (JNA) Jump if below or equal (not above)

JE (JZ) Jump if equal (zero)

JG (JNLE) Jump if greater (not less or equal)

JGE (JNL) Jump if greater or equal (not less)

Subroutine and Interrupt Instructions CALL, RET Call, return from procedure

INT, INTO Software interrupt, interrupt if overflow

IRET Return from interrupt

String Instructions MOVS Move byte or word string

MOVSB, MOVSW Move byte, word string

CMPS Compare byte or word string

SCAS Scan byte or word string

LODS, STOS Load, store byte or word string

REP Repeat



REPE, REPZ Repeat while equal, zero

REPNE, REPNZ Repeat while not equal (zero)

Processor Control Instructions STC, CLC, CMC Set, clear, complement carry flag

STD, CLD Set, clear direction flag

STI, CLI Set, clear interrupt enable flag

LAHF, SAHF Load AH from flags, store AH into flags

Week-6Assembly Language Programming Programming Languages

There are 4 types of programming languages.

High Level Language

Middle Level Language

Low level Language

Assembly Level Language.

Compiler & interpreter Compiler : It is used to translate the High Level Language (English statements) to low

level language (1 ‘ 0’s).Compile entire program one at time. eg. Pascal, Basic, Fortran and so on.

Interpreter : Used to translate the program high level language into low level language. It translates instruction by instruction.eg. Java

Assembler & Microprocessor



Assembler: Used to translate the Assembly level language (Mnemonics) into low level language.

Microprocessor: This is a smallest part of the processor which performs the following functions like

Storing data

Transferring

Performing Arithmetic and logical operations.

Shift Operations and so on.

Eg: 8086,80386.

Program Data Numbers: binary, hex decimal, decimal

Examples: –10, 42d, 10001101b, 0FF3Ah, 777o

Radix: b = binary, d = decimal, h = hexadecimal, and o = octal

If no radix is given, the integer constant is decimal

A hexadecimal beginning with a letter must have a leading 0

Characters: Characters must be enclosed in double quotes. “A”

Strings: Strings must be enclosed single quotes ‘hello’.

Variables: Name of the data types and is assigned a memory locations by the program.

Byte variables: The assembler derivative that defines a byte variable takes the following forms

name DB initial value

Ex: ALPHA DB 4

Memory is associated

Word variables: The assembler defines for defining a word variable has the following forms



Name DW initial_value

Arrays: Just sequence of memory bytes of words.

Symbol Address Constants

B_ARRAY 200h 10h

B_ARRAY+1 201h 20h

B_ARRAY+2 202h 30h

W-Array DW 1000,40,29887,329

Set up array of four words with initial values 1000 40,29887,329

• Symbol Address Constants

• W-ARRAY DW 1000,40,29887,329

• Set up array of four words with initial values

Some examples of assembly language statements – Following are some examples of typical assembly language statements −

ALP Program to display HELLO WORLD



ALP Program for Addition of two numbers

ALP Program to find the factorial of a number



Week-7



Revision of Week 1 To Week 6Test – 1

Week-8Instruction Sets & Formats



Instruction Formats: A Computer will usually have variety of Instruction Code formats.

It is the function of the control unit within the CPU to interpret each instruction code

and provide the necessary control functions needed to process the instruction.

The format of an instruction is usually described in a rectangular box symbolizing the

bits of the instruction as they appear in memory words or in control register.

The bits of the instruction are divided into groups called fields.

The most common fields found in instruction formats are:

OP-code field - specifies the operation to be performed

Address field - designates memory address(es) or a processor register(s)

Mode field - specifies the way the operand or the effective address is

determined

The number of address fields in the instruction format depends on the internal

organization of CPU

The three most common CPU organizations:

Single accumulator organization:

ADD X /* AC AC + M[X] */

General register organization:

ADD R1, R2, R3 /* R1 R2 + R3 */

ADD R1, R2 /* R1 R1 + R2 */

MOV R1, R2 /* R1 R2 */



ADD R1, X /* R1 R1 + M[X] */

Stack organization:

PUSH X /* TOS M[X] */

ADD

Types of Address Instructions: Three-Address Instructions

Two-Address Instructions

One-Address Instructions

Zero-Address Instructions

Three-address instructions: Memory addresses for the two operands and one destination need to be specified.

It is also called General register organization.

Instruction: ADD R1, R2, R3

Micro-operation: R1← R2 + R3

Program to evaluate X = (A + B) * (C + D) :

ADD R1, A, B /* R1 ← M[A] + M[B] */

ADD R2, C, D /* R2 ← M[C] + M[D] */

MUL X, R1, R2 /* M[X] ← R1 * R2 */

Advantages

Results in short programs when evaluating arithmetic expressions.

Disadvantages

Instructions require too many bits to specify three addresses.



Two-address instructions: Two address registers or two memory locations are specified.

Assumes that the Destination Address is the same as that of the first operand.

Instruction: ADD R1, R2

Micro-operation: R1← R1 + R2

One-address instructions: One address can be a register name or memory address.

Single Accumulator Organization

It uses AC register for all data manipulation.

Instruction: ADD X

Micro-operation: AC← AC + M[X]

Program to evaluate X = (A + B) * (C + D) :



Zero-address instructions: Stack is used.

Arithmetic operation pops two operands from the stack and pushes the result.

Also called Stack Organization.

RISC Instructions:



Week-9



Addressing Modes: Specifies a rule for interpreting or modifying the address field of the instruction (before

the operand is actually referenced).

Variety of addressing modes

to give programming flexibility to the user

to use the bits in the address field of the instruction efficiently

Types of Addressing Modes: Implied mode

Immediate mode

Register mode

Register indirect mode

Autoincrement or Autodecrement

Direct address mode

Indirect address mode

Relative address mode

Indexed addressing mode

Base register addressing mode

Implied Mode: In this mode the operands are specified implicitly in the definition of the instruction.

All register reference instructions that use an accumulator are implied mode instruction.

Example: CMA compliment accumulator.

Immediate Mode:



Data needed by the processor is contained in the instruction

Operand= address field

e.g-ADD 5

-add 5 to the content of accumulator

-5 is the operand

Register Addressing: Operand is held in register named in address field

A k-bit field can specify any one of 2^k registers

Register Indirect Addressing:



The selected register contains the address of the operand rather than the operand itself.

Auto Increment or Auto Decrement Mode: This is similar to the register indirect mode except that the register is incremented or

decremented after or before its value is used to access memory.

Direct Address Mode: Instruction specifies the memory address which can be used directly to the physical

memory

Faster than the other memory addressing modes

Too many bits are needed to specify the address for a large physical memory space

EA = IR(addr) (IR(addr): address field of IR)



Indirect Address Mode: The address field of an instruction specifies the address of a memory location that

contains the address of the operand

When the abbreviated address is used large physical memory can be addressed with a relatively small number of bits

Slow to acquire an operand because of an additional memory access

EA = M[IR(address)]

Relative Address Mode: In this mode the content of the program counter is added to the address part of the

instruction to obtain the effective address.

Indexed Addressing Mode: In this mode the content of an index register is added to the address part of the




Base Register Addressing Mode: In this mode the content of a base register is added to the address part of the


Week-10MIPS Implementation & Pipelining:

Instruction Set Architecture: Instruction Set Architecture (ISA)

o Usually defines a “family” of microprocessors

Examples: Intel x86 (IA32), Sun Sparc, DEC Alpha, IBM/360, IBM PowerPC, M68K, DEC VAX

o Formally, it defines the interface between a user and a microprocessor

ISA includes:

o Instruction set

o Rules for using instructions

Mnemonics, functionality, addressing modes

o Instruction encoding



ISA is a form of abstractiono Low-level details of microprocessor are “invisible” to user

ISA => abstraction is a misnomer

Many processor implementation details are revealed through ISA

Example:

o Motorola 6800 / Intel 8085 (1970s)

1-address architecture: ADDA <addr>

(A) = (A) + (addr)

o Intel x86 (1980s)

2-address architecture: ADD EAX, EBX

(A) = (A) + (B)

o MIPS (1990s)

3-address architecture: ADD $2, $3, $4

($2) = ($3) + ($4)

o Advancements in fabrication technology

MIPS Architecture: Design “philosophies” for ISAs: RISC vs. CISC

Execution time =

o instructions per program * cycles per instruction * seconds per cycle

MIPS is implementation of a RISC architecture

MIPS R2000 ISA

o Designed for use with high-level programming languages

small set of instructions and addressing modes, easy for compilers

o Minimize/balance amount of work (computation and data flow) per instruction

allows for parallel execution

o Load-store machine



large register set, minimize main memory access

o fixed instruction width (32-bits), small set of uniform instruction encodings

minimize control complexity, allow for more registers

MIPS Instructions: MIPS instructions fall into 5 classes:

o Arithmetic/logical/shift/comparison

o Control instructions (branch and jump)

o Load/store

o Other (exception, register movement to/from GP registers, etc.)

MIPS Addressing Modes: MIPS addresses register operands using 5-bit field

o Example: ADD $2, $3, $4

MIPS addresses branch targets as signed instruction offset

o relative to next instruction (“PC relative”)

o in units of instructions (words)

o held in 16-bit offset in I-type

o Example: BEQ $2, $3, 12

Immediate addressing

o Operand is help as constant (literal) in instruction word

o Example: ADDI $2, $3, 64

MIPS addresses jump targets as register content or 26-bit “pseudo-direct” address

o Example: JR $31, J 128

MIPS addresses load/store locations

o base register + 16-bit signed offset (byte addressed)

Example: LW $2, 128($3)

o 16-bit direct address (base register is 0)By Dr. Nitin S. Goje | 91


Example: LW $2, 4092($0)

o indirect (offset is 0)

Example: LW $2, 0($4)

Pipeline Implementation: Idea:

o Goal of MIPS: CPI <= 1

o Some instructions take longer to execute than others

o Don’t want cycle time to depend on slowest instruction

o Want 100% hardware utilization

o Split execution of each instruction into several, balanced “stages”

o Each stage is a block of combinational logic

o Latency of each stage fits within 1 clock cycle

o Insert registers between each pipeline stage to hold intermediate results

o Execute each of these steps in parallel for a sequence of instructions

o “Assembly line”

This is called pipelining

MIPS ISA: MIPS pipeline stages

o Fetch (F)

read next instruction from memory, increment address counter

assume 1 cycle to access memory

o Decode (D)

read register operands, resolve instruction in control signals, compute branch target



o Execute (E)

execute arithmetic/resolve branches

o Memory (M)

perform load/store accesses to memory, take branches

assume 1 cycle to access memory

o Write back (W)

write arithmetic results to register file

Hazards: Hazards are data flow problems that arise as a result of pipelining

Limits the amount of parallelism, sometimes induces “penalties” that prevent one instruction per clock cycle

Structural hazards

Two operations require a single piece of hardware

Structural hazards can be overcome by adding additional hardware

Control hazards

Conditional control instructions are not resolved until late in the pipeline, requiring subsequent instruction fetches to be predicted

Flushed if prediction does not hold (make sure no state change)

Branch hazards can use dynamic prediction/speculation, branch delay slot

Data hazards

Instruction from one pipeline stage is “dependent” of data computed in another pipeline stage



Pipelined Architecture:

Pipeline Enhancements: Assume we add branch predictor

Branch predictor success rate = 85%

Penalty for bad prediction = 3 cycles

Profiler tells us that 10% of instructions executed are branches

Branch speedup

o = (cycles before enhancement) / (cycles after enhancement)

o = 3 / [.15(3) + .85(1)] = 2.3



Amdahl’s Law:

Speedup = 1 / (.90 + .10/2.3) = 1.06

6% improvement


enhanced

enhancedenhanced Speedup

FractionFractionSpeedup

1

1


Week-11Input Output and Interrupts:

Input/ Output Problems: Wide variety of peripherals

Delivering different amounts of data

At different speeds

In different formats

All slower than CPU and RAM

Need I/O modules

Input/ Output Module: Interface to CPU and Memory

Interface to one or more peripherals

Generic Model of I/O Module:



External Devices: Human readable

Screen, printer, keyboard

Machine readable

Monitoring and control

Communication

Modem

Network Interface Card (NIC)

External Device Block Diagram:

I/O Module Function: Control & Timing

CPU Communication

Device Communication

Data Buffering

Error Detection



I/O Steps: CPU checks I/O module device status

I/O module returns status

If ready, CPU requests data transfer

I/O module gets data from device

I/O module transfers data to CPU

Variations for output, DMA, etc.

I/O Module Diagram:

I/O Module Decisions: Hide or reveal device properties to CPU

Support multiple or single device

Control device functions or leave for CPU

Also O/S decisions

e.g. Unix treats everything it can as a file



Input Output Techniques: Programmed

Interrupt driven

Direct Memory Access (DMA)

Programmed I/O: CPU has direct control over I/O

Sensing status

Read/write commands

Transferring data

CPU waits for I/O module to complete operation

Wastes CPU time

CPU requests I/O operation

I/O module performs operation

I/O module sets status bits

CPU checks status bits periodically

I/O module does not inform CPU directly

I/O module does not interrupt CPU

CPU may wait or come back later

I/O Commands: CPU issues address

Identifies module (& device if >1 per module)

CPU issues command

Control - telling module what to do

e.g. spin up disk

Test - check status



e.g. power? Error?

Read/Write

Module transfers data via buffer from/to device

Addressing I/O Devices: Under programmed I/O data transfer is very like memory access (CPU viewpoint)

Each device given unique identifier

CPU commands contain identifier (address)

I/O Mapping: Memory mapped I/O

Devices and memory share an address space

I/O looks just like memory read/write

No special commands for I/O

Large selection of memory access commands available

Isolated I/O

Separate address spaces

Need I/O or memory select lines

Special commands for I/O

Limited set

Interrupt Driven I/O: What is Interrupt?

An interrupt is a signal from a device attached to a computer or from a program within the computer that causes the main program that operates the computer (the operating system) to stop and figure out what to do next.

Overcomes CPU waiting

No repeated CPU checking of device



I/O module interrupts when ready

Interrupt Driven I/O Basic Operation: CPU issues read command

I/O module gets data from peripheral whilst CPU does other work

I/O module interrupts CPU

CPU requests data

I/O module transfers data

Identifying Interrupting Module: Different line for each module

PC

Limits number of devices

Software poll

CPU asks each module in turn

Slow

Daisy Chain or Hardware poll

Interrupt Acknowledge sent down a chain

Module responsible places vector on bus

CPU uses vector to identify handler routine

Bus Master

Module must claim the bus before it can raise interrupt

e.g. PCI & SCSI

Multiple Interrupts:By Dr. Nitin S. Goje | 91


Each interrupt line has a priority

Higher priority lines can interrupt lower priority lines

If bus mastering only current master can interrupt

Direct Memory Access: Interrupt driven and programmed I/O require active CPU intervention

Transfer rate is limited

CPU is tied up

DMA is the answer

DMA Function: Additional Module (hardware) on bus

DMA controller takes over from CPU for I/O

DMA Module Diagram:

DMA Operation:



CPU tells DMA controller:-

Read/Write

Device address

Starting address of memory block for data

Amount of data to be transferred

CPU carries on with other work

DMA controller deals with transfer

DMA controller sends interrupt when finished

Week-12



Revision from Week-8 to Week-11

Test-2

Week-13 & 14



Memory Organizations and Interfacing:

Early Memory: One of the earliest types of computer memory was called magnetic core memory.

It was made by weaving fine copper wires through tiny rings of magnetic material in an array.

Following Figure shows the basic arrangement of core memory.

Figure: Diagram of a Section of Core Memory

Organization of Memory Device: Following Figure presents the basic organization of a memory device.



Interfacing Memory to a Processor: 1. Buses

In order to communicate with memory, a processor needs three types of connections: data, address, and control.

The data lines are the electrical connections used to send data to or receive data from memory.

The address lines are controlled by the processor and are used to specify which memory location the processor wishes to communicate with.

The control lines consist of the signals that manage the transfer of data. At a minimum, they specify the timing and direction of the data transfer. The processor also controls this group of lines.



2. Memory Maps

System designers describe the use

of memory with a memory map.

A memory map represents a system's memory with a long, vertical column.

It is meant to model the memory array where the rows correspond to the memory locations.

Within the full range of addresses are smaller partitions where the individual resources are present.


Figure: Basic Processor to Memory Device Interface

Figure: Sample Memory Maps


3. Address Decoding

Address decoding is a method for using an address to enable a unique memory device while leaving all other devices idle.

The method described here works for many more applications than memory though.

It is the same method that is used to identify which subnet a host computer is connected to be based on its IP address.

All address decoding schemes have one thing in common: the bits of the full address are divided into two groups, one group that is used to identify the memory device and one group that identifies the memory location within the selected memory device.

4. Chip Select Hardware

What we need is a circuit that will enable a memory device whenever the full address is within the address range of the device and disable the memory device when the full address falls outside the address range of the device.

So the process of designing a chip select is as follows:

Using the memory space of the processor and the size of the memory device, determine the number of bits of the full address that will be used for the chip select.


Figure: Sample Chip Select Circuit for a Memory Device


Using the base address where the memory device is to be located, determine the values that the address lines used for the chip select are to have.

Create a circuit with the address lines for the chip select going into the inputs of a NAND gate with the bits that are to be zero inverted.

Memory Mapped Input/ Output: The practice of interfacing an input/output (I/O) device as if it was a memory device is

called memory mapping.

Just like the bus interface for a memory device, the memory mapped interface to a bus uses a chip select to tell the device when it's being accessed and data lines to pass data between the device and the processor.

Some memory mapped I/O even use a limited number of address lines to identify internal registers.

In addition, I/O devices use the write enable and read enable signals from the processor to determine whether data is being sent to the device or read from it.

Some devices may only support writing (purely output) while others may only support reading (purely input).



Figure: Some Types of Memory Mapped I/O Configurations

Memory Terminology: Computer memory is any physical device capable of storing information temporarily or

permanently.

Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system.

Memory can be characterized by the following points like:

Speed

Size

Cost

Unit of Memory Size:

1 bit=the value of 0 or 1

8 bits = 1 byte

1024 byte =1 kilobyte

1024 kilobytes = 1 megabyte

1024 megabytes = 1 gigabyte

1024 gigabytes = 1 terabyte

1024 terabytes = 1 petabyte



Figure: Memory Hierarchy

Random Access Memory (RAM): Misnamed as all semiconductor memory is random access

Can Read/Write

Volatile in Nature

Temporary storage

Static or dynamic

Types of RAM

DRAM

SRAM



Dynamic RAM:

Bits stored as charge in capacitors

Charges leak

Need refreshing even when powered

Simpler construction

Smaller per bit

Less expensive

Need refresh circuits

Slower

Used for main memory in computing systems

Essentially analogue

Level of charge determines value

Dynamic RAM Structure:

Static RAM:

Bits stored as on/off switches



No charges to leak

No refreshing needed when powered

More complex construction

Larger per bit

More expensive

Does not need refresh circuits

Faster

Cache

Digital

Uses flip-flops

Static RAM Structure:

SRAM v DRAM:

Both volatile



Power needed to preserve data

Dynamic cell

Simpler to build, smaller

More dense

Less expensive

Needs refresh

Larger memory units

Static

Faster

Cache

Read Only Memory (ROM): Permanent storage

Nonvolatile

Microprogramming

Library subroutines (code) and constant data

Systems programs (BIOS for PC or entire application + OS for certain embedded systems)

Types of ROM:

Written during manufacture

Very expensive for small runs

Programmable (once)

PROM

Needs special equipment to program

Read “mostly”



Erasable Programmable (EPROM)

Erased by UV

Electrically Erasable (EEPROM)

Takes much longer to write than read

Flash memory

Erase whole memory electrically

Asynchronous versus Synchronous Memory Interfacing: When a processor sets the inputs of a memory device, it has to wait for the memory to

respond. This is called asynchronous operation.

Some processors, however, are designed so that the memory follows a precise timing requirement governed by a clock that is added to the bus to keep everything attached in lock-step. This type of interface is referred to as synchronous and the memory that uses this type of interface is referred to as synchronous DRAM or SDRAM.

Cache Memory: Cache memory is a very high speed semiconductor memory which can speed up CPU.

It acts as a buffer between the CPU and main memory.

It is used to hold those parts of data and program which are most frequently used by CPU.

The parts of data and programs are transferred from disk to cache memory by operating system, from where CPU can access them.

Advantages

Cache memory is faster than main memory.

It consumes less access time as compared to main memory.

It stores the program that can be executed within a short period of time.

It stores data for temporary use.

Disadvantages



Cache memory has limited capacity.

It is very expensive.

Week-15

Revision from Week-1 to Week-14


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