wcdma-01-introduction to system ic design flow
DESCRIPTION
system ic designTRANSCRIPT
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Wireless Information Transmission System Lab.
National Sun Yat-sen UniversityInstitute of Communications Engineering
Introduction to System IC Design Flow
Hung-Chih Chiang
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2Wireless Communication IC ExamplesFundamentals of SoCSystem IC Design FlowApplication Specific Platform
Outline
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3Example1: Siemens C35i Phone1. Infineon E-GOLD PMB2851E, GSM Baseband controller and DSP.2. 32.768kHz crystal3. NIY4. Bottom connector5. FLASH6. Power supply IC7. VCO8. Epcoc B4846; SAW filter, 225.0MHz9. PCB pads to Battery10. 13MHz crystal11. Tx VCO12. Hitachi PF08112B; Power amplifier13. External antenna connetor with switch.14. Diplex filter15. NIY16. Epcos B4127 SAW filter 942.5MHz17. NIY18. PCB pads to SIM card holder19. Synthesizer (?)20. Hitachi HD155124F Bright II; GSM Transceiver Circuit 21. Infineon PMB2906: Analog interface IC (E-GAIM).
Interfaces analogue signals (I/Q, voiceband, PA-control, charging control signals) to the digital domain
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4Example2: Philips DAB Receiver
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5Years 2000 2005 Communication IC Production Values in Taiwan
2000 2001 2002(e) 2003(f) 2004(f) 2005(f) 50.7 24.3% 53.7 5.9% 67.2 25.1% 101.7 51.4% 141.0 38.6% 155.6 10.4% 17.3 158.0% 32.9 90.6% 42.3 28.5% 64.3 51.9% 98.7 53.4% 118.4 20.0% ADSL/CABLE Modem 19.6 345.5% 13.4 -31.5% 19.0 41.4% 31.1 64.0% 45.1 44.9% 54.1 20.0% 5.8 728.6% 1.2 -78.8% 1.5 19.7% 4.2 184.2% 11.3 171.7% 16.9 50.0% 13.8 1871.4% 15.9 14.7% 21.9 38.1% 41.5 89.5% 67.7 63.0% 77.8 15.0% 66.8 38.9% 54.9 -17.8% 56.9 3.7% 78.9 38.5% 95.8 21.6% 108.2 12.9% Source: ITIS(2002/09)
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6System Integration Trend- Cfone
Source: ITIS(2002/10)
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7Outline
Wireless Communication IC ExamplesFundamentals of SoCSystem IC Design FlowApplication Specific Platform
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8Moores Law and Extensions
Source: Intel
- Moores Law will extend another 10-15 years.- But no exponential is forever, so delayed Moores Law (valid in the past 50 years) will be more realistic for the next 10-15 years.
Gordon Moore (ISSCC2003):
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9Histories of Key IC Components
1st Bipolar Transistor Belllab in 1956 1st integrated memory-cell NEC in 1966 1st Bipolar ECL IBM in 1957 1st 1Kb 3T MOS DRAM Intel/Honeywell in 1970 1st IC Fairchild in 1960 1st 2Kb EPROM Intel in 1971 1st TTL Fairchild in 1962 1st 1T DRAM Siemens in 1972 1st CMOS Fairchild in 1963 1st mux-addressed 16Kb DRAM Mostek in 1977 1st 4-bit NMOS uP Intel in 1974 1st 4Kb pseudo-SRAM Intel in 1979 1st 32-bit CMOS uP Belllab in 1981 1st 16Kb EEPROM Intel in 1980 1st 32-bit RISC uP Standford+Berkeley in 1984 1st 256Kb Flash Toshiba in 1985 1st 100Mhz CMOS uP Intel in 1991 1st 256b FRAM Ramtron in 1988 1st 64-bit CMOS uP-200Mhz DEC in 1992
Memory
1st multi-level 32Mb Flash Intel in 1995 1st out-of-order-execution uP Intel in 1995 1st sampled-data band-pass Filter Belllab in 1960
Logic
1st 32-bit 1Ghz uP-0.18u Intel in 2000 1st analog shift-register Philips in 1972 1st PLL IC Signetics in 1969 1st switched-capacitor Filter Berkeley in 1978 1st MOS voice-encoder Berkeley in 1976 1st DSP Belllab in 1980 1st switch-capacitor Filter Berkeley in 1977 1st floating-point 32-bit DSP Bellab in 1985 1st echo-canceller Belllab in 1983 1st Video DSP NEC in 1987 1st 1-chip Pager Philips in 1991 1st CMOS read-channel Hitachi in 1993 1st GSM Transceiver Belllab in 1995 1st low-power 16-bit DSP Matsushida in 1993
1st 1024-QAM cable-modem DSP Broadcom in 1998
Analog
DSP
1st 5Ghz OFDM-BB 80Mb/s Imec in 2000
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Technology MigrationTSMC Logic Technology Roadmap
Source: TSMC Technology Roadmap (Apr 2004)
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SoC Concept- From System on a Board to System on a Chip
Analog
ASIC CPU
Mem
ory
Analog
CPU
Mem
ory
IP
IP
IPIP
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Minimize System CostCompact System SizeReduce System Power ConsumptionIncrease System Performance
Soc Advantages
IDM
Siemens
Motorola
Toshiba
Sales Channel / Service Provider
System House (OEM/ODM)
Design House (fabless)
IP Provider
Photo Mask/Foundry Service
Packaging Service
Testing Service
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SoC ChallengesIP Resource IP library, IP provider
Chip Integration Components with different manufacturer processes (logic, memory, analog,
high V, )Chip Design Verification EDA Tools that support system verification at all or mixed design phases
Chip Testing Independently test components (logic, memory, analog, )
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A Current Practical Alternative to SoC: System-in-a-Package (SiP)
Analog
ASIC CPU
Mem
ory
SiP concept
Packaged Chip
die
substrate
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SiP benefits: Reduced developing schedule
Reduced developing cost
Possible mounting of different technologies
Increased yields enabled by smaller chip size
Benefits of SiP
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SiP Examples
Examples of practical SiP
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Wireless Communication IC ExamplesFundamentals of SoCSystem IC Design Flow*
Application Specific Platform
Outline
*Ref: Reuse Methodology Manual For SYSTEM-ON-A-CHIP DesignsTHIRD EDITION By Michael Keating & Pierre BricaudKLUWER ACADEMIC PUBLISHERS
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Typical System IC Architecture
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Traditional Sequential ASIC Design Flow
Specification
System ModelsArchitecture Design
RTL Design
Logic synthesis
Physical Design
RTL Design
Functional Verification
Logical Synthesis
Timing Verification
P & R
Physical Verification
Prototype Build & Test Prototype
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Parallel System IC Design FlowSystem Design and Verification
Placement and Route -> Tapeout
Time
Physical Specification: area, power,
clock tree design
Timing Specification:
IO timing, clock
frequency
Hardware Specification
Software Specification
Algorithm develop. &
macro decomp.
Application prototype
development
Physical Timing Hardware Software
Preliminary floorplan
Block timing specification
Block selection / design
AP prototype testing
Updated floorplansUpdated floorplans
Trial placement
Block synthesis & placement
Top-level synthesis
Block verificationTop-level
HDLTop-level
verification
Application development
Application testing
Application testing
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SpecificationsSpecification Requirements: Hardware
Functionality External interfaces to other hardware Software interface (register definitions) Timing Performance Area and power constraints
Software Functionality Timing Performance Hardware Interface Software structure, kernel
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SpecificationTwo Useful Specification Techniques: Formal specifications:
The desired characteristics of a design are defined independently of any implementation. Once a formal specification is generated, format methods such as property checking can be used to prove that a specific implementation meets the specification.
Executable specifications: An executable specification is typically an abstract model for the hardware/software been specified written in in C, C++, SystemC, HVL, Verilog, or VHDL.
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Top-Level System Design ProcessesCREATE
system specification
REFINE & TESTarchitecture model
(HW/SW co-simulation)
Block2 spec.
Block1 spec.
DEVELOPsystem model
DETERMINEHW/SW partition
DEVELOPPrototype SW
SPECIFY & DEVELOPHW architecture model
SPECIFYSW
SPECIFYHW blocks
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Outline
Wireless Communication IC ExamplesFundamentals of SoCSystem IC Design FlowApplication Specific Platform
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Application Specific PlatformIP re-use is essential for all SoC designs.
The specification of an ASIC (Application-Specific Integrated Circuit) chip often includes application adaptability due to the following factors: Significant market shift, Rapid evolved standards, Product differentiation, Hardware reuse.
Its probably not a good idea to develop an all-purpose platform for IP integration, since different applications requires different CPU/DSP powers, memories, IOs, etc.
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Application Specific PlatformA generic platform contains the following components: Bus system (AMBA, PalmBus, ) CPU/MCU, DSP SRAM, DRAM, non-volatile memory, Basic I/O functions (UART, SPI, USB, PCI, )
An application specific platform contains: Specification of application A generic platform + pre-integrated IP for the specified application.
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Platform Design Objectives Application Space
Architecture Space
SystemPlatform
PlatformSpecification
ApplicationSpace
Exploration
Platform Design Objectives: Design the platform to support multiple applications
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Platform SelectionApplication Space
Architecture Space
SystemPlatform
ApplicationSpecification
PlatformSpace
Exploration
Platform Selection: For a given application. select the best platform in terms of performance, cost, etc.
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Platform Example1: ARM PrimeXsys Platform
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Platform Example2:MIPS SOC-it
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Platform Example3:PowerPC CoreConnect Platform
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Application Specific Platform Example1:
ARM PrimeXsys Wireless Platform
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Application Specific Platform Example2:
AWM Wireless Multimedia Platform
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Xpert-GPS 3000 Platform
Application Specific Platform Example3:
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Application Specific Platform Example4:
Palm Pak SoC Platform
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System-on-a-Programmable-Chip (SoPC)
SoPC - FPGA with the following features Embedded processor core On-chip peripherals and memory Millions of gates in FPGA logic cells System level tools provided
SoPC advantages over SoC Reconfigurable Fast prototyping Save NRE charges
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SoPC Solution
Xilinx Virtex-II Pro Virtex-II Pro FPGA PowerPC 405, CoreConnect bus Micro Blaze controller (32-bit RISC) Peripheral and memory blocks EDK/ISE
Altera- Excalibur APEX 20KE FPGA ARM 922T, AMBA bus NIOS controller (16/32-bit RISC) Peripheral and memory blocks SoPC Builder/Quartus II
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Summaries
IC design trend is moving toward SoC.Parallel design flow significantly reduces system IC developing schedule wrt. Traditional design flow. Selecting a proper application-specific platform is important for current and future project development.
Introduction to System IC Design FlowOutlineExample1: Siemens C35i PhoneExample2: Philips DAB ReceiverYears 2000 2005 Communication IC Production Values in TaiwanSystem Integration Trend- CfoneOutlineMoores Law and ExtensionsHistories of Key IC ComponentsTechnology MigrationSoC ConceptSoc AdvantagesSoC ChallengesA Current Practical Alternative to SoC: System-in-a-Package (SiP)OutlineTypical System IC ArchitectureTraditional Sequential ASIC Design FlowParallel System IC Design FlowSpecificationsSpecificationTop-Level System Design ProcessesOutlineApplication Specific PlatformApplication Specific PlatformPlatform Design Objectives Platform SelectionPlatform Example1: Platform Example2:Platform Example3:Summaries