wang ruonan thesis

8/2/2019 WANG Ruonan Thesis

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Enhancement/Depletion-mode HEMT Technology for III-Nitride

Mixed-Signal and RF Applications

by

Ruonan WANG

A Thesis Submitted toThe Hong Kong University of Science and Technology

in Partial Fulfillment of the Requirements forthe Degree of Doctor of Philosophy

in the Department of the Electronic and Computer Engineering

January 2008, Hong Kong


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Authorization

I hereby declare that I am the sole author of the theses.

I authorize the Hong Kong University of Science and Technology to lend thisthesis to other institutions or individuals for the purpose of scholarly research.

I further authorized the Hong Kong University of Science and Technology toreproduce the thesis by photocopying or by other means, in total or in part, at therequest of other institutions or individuals for the purpose of scholarly research.

__________________________________________Ruonan WANG


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Enhancement/Depletion-mode HEMT Technology for III-Nitride Mixed-Signal

and RF Applications

by

Ruonan WANG

This is to certify that I have examined above PhD thesisand have found that it is complete and satisfactory in all aspects,

and that any and all revisions required bythe thesis examination committee have been made.

________________________________________

Prof. Kevin J. CHENThesis Supervisor

________________________________________Prof. Kwing Lam CHAN

Thesis Examination Committee Member (Chairman)

________________________________________Prof. Kei May LAU

Thesis Examination Committee Member

________________________________________Prof. Johnny K. O. SIN


________________________________________Prof. Jiannong WANG


________________________________________Prof. Khaled BEN LETAIEF

Head of the Department of Electronic and Computer Engineering

The Department of Electronic and Computer EngineeringJanuary 2008


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ACKNOWLEDGEMENTS

I would first like to take this opportunity to express my appreciation to my

supervisor, Prof. Kevin J. CHEN, for his intensive guidance and generous help in my

thesis work. Without his support, I could not have this opportunity to come to Hong

Kong and involve in the challenging and exciting field of GaN HEMTs. In the past

three and a half years, I learned so much from him on how to become a good

researcher. I think I can benefit from the experience with him all through my life,

especially his persistent pursuit in deeply understanding and solving problems, and

his great enthusiasm on the research and teaching work. Prof. Chen also provided me

a lot of opportunities to attend international conferences, and therefore, got a chance

to have conversations with the top corporations and research groups in the world. In

addition, I would like to thank Prof. Kei May LAU, for her supporting and providing

substrates in my research work. The other committee members of my thesis

examination are also appreciated: Prof. Kwing Lam CHAN, Prof. Jiannong WANG,

Prof. Johnny K. O. SIN, and Prof. Jianbin XU.

Most of the GaN HEMT samples used in this work were grown by Mr. Wilson C.

W. TANG, my long-term research cooperator. Many thanks go to Mr. Kwok Wai

CHAN for his kindness and patience in guiding me how to use the microwave device

measurements.

All of the GaN-based HEMTs, which make up of the foundation of my research

work, were fabricated in the nanoelectronic fabrication facility (NFF) at HKUST. Its

Mr. Shuo JIA who helped me get familiar with the clean room and the details of


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micro-fabrication techniques. He was a very good listener and friend, and we got a

lot of funs on the same interests. I also want to express my gratitude to Dr. Yong

CAI, and Dr. Jie LIU, who gave me many valuable suggestions to my work. Their

solid experiment results on GaN HEMTs constructed the foundation of my thesis

work, and their experience saved me a lot of time in wafer processing. Dr. Zhiqun

CHENG made me grasp the basic design principles of RF device and circuit

topology in a short time. Dr. Zhenchuan YANG also deserves to be mentioned here

for his helpful discussions in the group meetings and resourceful knowledge on

micro-fabrications. It has been a pleasant time to work with these kind people and

share the knowledge of GaN-based devices and circuits with them.

I would like to thank some other members in the wireless communication

laboratory, Dr. Congshun WANG, Dr. Wei HUANG, Dr. Wanjun CHENG, Dr.

Hualiang ZHANG, Dr. Maojun WANG, Mr. Kingyuen WONG, Mr. Yichao WU, Mr.

Di SONG, Mr. Li YUAN, Mr. Xiaohua WANG, Ms. Song TAN and Ms. Congwen

YI, who worked with me for a long time and shared the happy time with me.

A last, I must thank my father Duo WANG, my mother Shuyun QIAO and my

wife Hong YIN for their unconditional love, efforts and encouragements all the time.

They are the most important part of my life.


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TABLE OF CONTENTS

Title Page .......................................................................................................................... i

Authorization Page................................................................................................................... ii

Signature Page ........................................................................................................................iii

Acknowlegements................................................................................................................... iv

Table of Contents.................................................................................................................... vi

List of Figures .................................................................................................................... ix

List of Tables ........................................................................................................................ xiv

Abstract............................................................................................................................ 1

Chapter 1 Introduction ............................................................................................................. 4

1.1 Fundamentals of High Electron Mobility Transistors........................................ 4

1.2 Developments of AlGaN/GaN HEMTs ........................................................... 14

1.3 Enhancement/Depletion-mode AlGaN/GaN HEMTs and Mixed-Signal

Applications ..................................................................................................... 19

1.3.1 Synthesis of Enhancement-mode AlGaN/GaN HEMTs ....................... 19

1.3.2 Mixed-signal applications of E/D-mode AlGaN/GaN HEMTs ............ 24

1.4 Objective of This Work.................................................................................... 27

Chapter 2 Temperature Dependence and Thermal Stability of Planar-Integrated

Enhancement/Depletion-mode AlGaN/GaN HEMTs and Digital Circuits...... 29

2.1 Motivation of Planar Integration of E/D-mode AlGaN/GaN HEMTs for GaN-

based High Temperature Digital Circuits......................................................... 29


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2.2 Device Structure and Fabrication..................................................................... 31

2.3 Discrete E/D-mode AlGaN/GaN HEMTs by Planar Process........................... 36

2.3.1 Temperature Dependence...................................................................... 36

2.3.2 Thermal stability ................................................................................... 44

2.4 Planar-Integrated DCFL Digital Circuits ......................................................... 46

2.4.1 DCFL Inverters ..................................................................................... 46

2.4.2 DCFL Ring Oscillators.......................................................................... 50

2.5 Summary .......................................................................................................... 54

Chapter 3 Integration of Enhancement and Depletion-mode AlGaN/GaN MIS-HFETs by

Fluoride-based Plasma Treatment.................................................................... 56

3.1 Motivation of Fabrication of E-mode AlGaN/GaN MIS-HFETs..................... 56

3.2 Device Structure and Fabrications ................................................................... 58

3.3 Device and Circuit Characterization ................................................................ 61

3.3.1 E-mode AlGaN/GaN MIS-HFET Characteristics ................................. 61

3.3.2 DCFL Integrated Circuit Applications .................................................. 66

3.4 Conclusions...................................................................................................... 70

Chapter 4 Gain Improvement of Enhancement-mode AlGaN/GaN HEMTs Using Dual-

Gate Architectures............................................................................................ 71

4.1 Motivation for the Enhancement-mode AlGaN/GaN DG HEMTs.................. 71

4.2 E-mode Dual-Gate AlGaN/GaN HEMTs Fabrication ..................................... 72

4.3 Device DC and RF Characteristic Comparison................................................ 74

4.4 Conclusions...................................................................................................... 79


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LIST OF FIGURES

Fig. 1.1.1 Schematic structure of an AlGaAs/GaAs HEMT and the corresponding energy

band profile. ....................................................................................................... 5

Fig. 1.1.2 Energy-band diagram of the metal/n-AlGaAs/GaAs system and the

electrostatic field distribution in the AlGaAs layer at the threshold voltage and

VG,max. ................................................................................................................. 6

Fig. 1.1.3 Gate-bias-modulated conduction band diagram and 2DEG concentration of an

AlGaAs/GaAs HEMT. ....................................................................................... 7

Fig. 1.1.4 Typical DC I-V characteristics of an AlGaAs/GaAs HEMT: (a) output curve;(b) transfer curve. ........................................................... ............................................. 8

Fig. 1.1.5 Equivalent circuit model for a HEMT, and the intrinsic circuit model is

enclosed by the dashed line................................................................ ........................ 9

Fig. 1.1.6 The physical origin of the elements in the equivalent circuit model of

AlGaAs/GaAs HEMT.............................................................. ................................. 10

Fig. 1.1.7 Schematic representation of a HEMT operating in Class A................................ 13

Fig. 1.2.1 Schematic structure of an AlGaN/GaN HEMT and the corresponding energy-

band profile. ......................................................... ...................................................... 15

Fig. 1.2.2 Crystal structure of (a) Ga-faced and (b) N-faced wurtzite GaN........................ 16

Fig. 1.2.3 Band profiles of the AlGaN/GaN heterostructures with different AlGaN

thickness, which demonstrate the surface states contribution to the 2DEG

formation. ............................................................. ...................................................... 17

Fig. 1.3.1 Schematic diagram of an E-mode HEMT with the recessed gate. ..................... 20

Fig. 1.3.2 Conduction band schematic diagrams of (a) conventional D-mode AlGaN/GaN

HEMT and (b) E-mode HEMT with CF4 plasma treatment............................... 22

Fig. 1.3.3 DCFL circuit schematics of (a) E/D-mode HEMT inverter, (b) NOR gate and

(c) NAND gate logic circuits. ............................................................ ...................... 26

Fig. 2.2.1 Schematic cross-section of the AlGaN/GaN HEMT device. .............................. 31


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Fig. 2.2.2 Layout of the Hall Bridge for Hall measurements................................................ 32

Fig. 2.2.3 Schematics showing the process flow of E/D-mode HEMTs: (a) ohmic contact;

(b) active region definition by plasma treatment; (c) D-mode gate formation; (d)

E-mode gate definition and plasma treatment; (e) SiN passivation. .................. 33

Fig. 2.2.4 Layout for the AlGaN/GaN HEMTs fabrication .................................................. 34

Fig. 2.2.5 Microscopy photos of the fabricated HEMT devices: (a) overall view; and (b)

zoom-in view of the active region................................................................ ........... 35

Fig. 2.3.1 DC output characteristics of (a) D-mode HEMT and (b) E-mode HEMT by the

planar process....................................................... ...................................................... 36

Fig. 2.3.2 Transfer characteristics comparison between the planar process and thestandard ICP mesa etching process: (a) drain current and (b) transconductance

comparison. The source-drain voltage (VDS) is fixed at 10 V. ............................ 37

Fig. 2.3.3 D-mode HEMTs transfer characteristics comparison at different temperatures:

(a) drain current and (b) transconductance. .......................................................... . 38

Fig. 2.3.4 E-mode HEMTs transfer characteristics comparison at different temperatures:

(a) drain current in log scale, (b) drain current in linear scale and (c) device

transconductance. ........................................................... ........................................... 39

Fig. 2.3.5 Temperature dependence of threshold voltage (Vth) and off-state drain leakage

current (Ileak) for E/D-mode HEMTs by the planar process................................. 40

Fig. 2.3.6 Sub-threshold slope characteristic comparison between RT and 350C ........... 42

Fig. 2.3.7 Sub-threshold slope characteristics from RT to 350C........................................ 43

Fig. 2.3.8 Schematics of gate controlling capability in sub-threshold region for (a) D-

mode and (b) E-mode HEMTs. ......................................................... ...................... 43

Fig. 2.3.9 E/D-mode HEMTs DC characteristic comparison before and after high-

temperature measurements................................................................. ...................... 44

Fig. 2.3.10 The variations of the peak drain current density (Imax), off-state drain current

(Ileak) and maximum transconductance (gm) during thermal stress up to 153

hours at 350C for E/D-mode HEMTs fabricated by the planar process........... 45

Fig. 2.3.11 Small signal RF characteristics comparison before and after thermal stress for

both E-mode and D-mode HEMTs by the planar process. .................................. 46


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Fig. 2.4.1 Schematic design of E/D-mode AlGaN/GaN DCFL inverter. ............................ 47

Fig. 2.4.2 Static voltage transfer curves of an E/D-mode HEMT DCFL inverter at (a)

room temperature (RT) and (b) 350C. ....................................................... ........... 47

Fig. 2.4.3 Temperature dependence of (a) the voltage transfer curves and (b) current

consumption for the E/D-mode DCFL inverter by the planar process. ............. 49

Fig. 2.4.4 (a) Schematic design and (b) SEM photograph of a 17-stage E/D-mode

AlGaN/GaN DCFL ring oscillator by the planar process. ................................... 50

Fig. 2.4.5 Configuration of ring oscillator measurement system, including a DC source, a

current meter, a spectrum analyzer and an oscilloscope. ..................................... 51

Fig. 2.4.6 The 17-stage E/D-mode AlGaN/GaN HEMT DCFL ring oscillator frequency

spectrum at (a) room temperature (RT) and (b) 350C. ....................................... 52

Fig. 2.4.7 The dependences of the ring oscillator (a) output frequency and (b) current

consumption on different environment temperatures........................................... 53

Fig. 2.4.8 The dependences of the ring oscillator power-delay product per stage on

environment temperatures. ...................................................... ................................. 53

Fig. 3.2.1 Capacitance-voltage curves of the substrate used for the E/D-mode MIS-HFET

fabrication............................................................. ...................................................... 58

Fig. 3.2.2 Schematics showing the process flow of E/D-mode AlGaN/GaN MIS-HFETs

integration: (a) active region definition and ohmic contacts; (b) the 1st Si3N4

layer (thick) deposition and E-mode gate definition; (c) D-mode device

window opened; (d) the 2nd Si3N4 layer (thin) deposition; (e) interconnects and

pads openings; (f) metallization for gate contacts and interconnects................. 59

Fig. 3.3.1 E-mode AlGaN/GaN MIS-HFET (a) DC output and (b) transfer curves.......... 62

Fig. 3.3.2 E-mode AlGaN/GaN MIS-HFET gate leakage current performance. ............... 63

Fig. 3.3.3 Pulse measurements of E-mode AlGaN/GaN MIS-HFET. ................................. 63

Fig. 3.3.4 Small signal RF measurements of E-mode AlGaN/GaN MIS-HFETs.............. 64

Fig. 3.3.5 Power sweep measurements by a load-pull system at 2 GHz on E-mode

AlGaN/GaN MIS-HFETs........................................................ ................................. 65


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Fig. 3.3.6 DC output characteristics of an E-mode MIS-HFET with longer fluoride

plasma treatment time.............................................................. ................................. 66

Fig. 3.3.7 D-mode AlGaN/GaN MIS-HFET (a) DC output and (b) transfer curves. ........ 67

Fig. 3.3.8 E/D-mode AlGaN/GaN MIS-HFET DCFL inverter voltage transfer and current

consumption curve. ........................................................ ........................................... 68

Fig. 3.3.9 Ring oscillator frequency and time domain characteristics at RT [(a) and (b)]

and 415C [(c) and (d)]............................................................ ................................. 69

Fig. 3.3.10 Temperature dependence of ring oscillator frequency and current consumption.

........................................................... ............................................................... ............ 70

Fig. 4.1.1 Schematic structure of dual-gate AlGaN/GaN HEMTs....................................... 72

Fig. 4.2.1 Schematics showing the process flow of E-mode DG HEMTs: (a) mesa and

ohmic contacts; (b) D-mode gate electrodes; (c) E-mode gate definition and

plasma treatment; (d) E-mode gate metal deposition and lift-off....................... 73

Fig. 4.3.1 DC characteristics of E-mode DG HEMTs: (a) output curves and (b) transfer

characteristics....................................................... ...................................................... 75

Fig. 4.3.2 Transfer curves of E-mode and D-mode SG HEMTs. ......................................... 76

Fig. 4.3.3 Frequency dependence of short-circuit current gain (h21) and maximum

stable/maximum available gain (MSG/MAG) for E-mode DG and SG devices.

........................................................... ............................................................... ............ 76

Fig. 4.3.4 Equivalent small-signal circuit model for AlGaN/GaN HEMTs........................ 77

Fig. 4.3.5 Output impedance (RDS) and feedback capacitance (CGD) comparison between

E-mode SG and DG HEMTs, which are extracted from S-parameters. ............ 78

Fig. 4.3.6 Gain-frequency characteristic comparison between E-mode DG and SG

HEMTs....................................................... ................................................................ . 78

Fig. B.1 (a) Configuration of the static DC measurement with a semiconductor

parameter analyzer; (b) the shape of the device for the static DC measurement.

........................................................... ............................................................... .......... 109

Fig. B.2 (a) Configuration of the dynamic I-V measurement with a dynamic I-V

analyzer; (b) the shape of the device for the dynamic I-V measurement; (c) the

shape of the GSG probe for RF measurements. .................................................. 110


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Fig. B.3 (a) Configuration of the CV measurement with a LCR meter and a

semiconductor parameter analyzer; (b) the shape of Schottky diode for the CV

measurement. ....................................................... .................................................... 111

Fig. B.4 Configuration of the S-parameters measurement with a vector network analyzer

(VNA) and a DC bias source controlled by PC. ................................................. 114

Fig. B.5 SOLT calibration standards for on-wafer RF small-signal measurement. ...... 115

Fig. B.6 The shape of the open pad for device de-embeding. ...................................... 116

Fig. B.7 Configuration of the large-signal power measurement, including a load-pull

system, a signal generator, a DC bias source, and a power meter controlled by a

PC. .............................................................. ............................................................... 117


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LIST OF TABLES

Table 1-1 Advantages of the HEMT structure. .................................................................. 8

Table 1-2 Historical Development of GaN-based HEMTs. ............................................. 18

Table 1-3 E-mode AlGaN/GaN HEMT performance comparison................................... 23

Table 1-4 Properties of competing materials in power electronics. ................................. 24

Table 1-5 Competitive advantages of GaN devices .............................................................. . 25

Table 2-1 DCFL inverter characteristics with different environment temperatures at the

supply voltage of 3.3 V............................................................ ................................. 50


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Enhancement/Depletion-mode HEMT Technology for III-Nitride

Mixed-Signal and RF Applications

by Ruonan WANG

Department of Electronic and Computer Engineering

The Hong Kong University of Science and Technology

ABSTRACT

Owing to the unique capabilities of achieving high breakdown voltage, high

current density, high cut-off frequencies, and high operating temperatures,

AlGaN/GaN high electron mobility transistors (HEMTs) are emerging as promising

candidates for radio-frequency (RF)/microwave power amplifiers and high-

temperature electronics. Compared to the conventional depletion-mode (D-mode)

AlGaN/GaN HEMTs, enhancement-mode (E-mode) devices present two major

advantages: 1) the reduced circuit complexity by eliminating the negative voltage

supply; 2) the implementation of direct-coupled FET logic (DCFL) for digital

circuits by integrating E/D-mode AlGaN/GaN HEMTs together. In this work, we

will use a novel fluoride-based plasma treatment technique to fabricate high-

performance E-mode AlGaN/GaN HEMTs, and then apply this treatment technique


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to new device structure and integration technology for GaN-based mixed-signal

circuit applications.

This work can be divided into three parts, namely planar-integration of E/D-

mode AlGaN/GaN HEMTs, Si3N4/AlGaN/GaN metal-insulator-semiconductor

heterostructure field-effect transistors (MIS-HFETs), and E-mode dual-gate (DG)

AlGaN/GaN HEMTs. At first, to achieve high density and high uniformity GaN-

based digital circuits, a planar fabrication technology has been developed to integrate

E/D-mode AlGaN/GaN HEMTs on the same chip. A DCFL inverter and a 17-stage

ring oscillator are demonstrated using this technology, in which the whole process is

conducted on a planar surface. After 153-hour thermal stress measurements at 350C,

the fabricated devices maintain the same DC and RF characteristics, suggesting

excellent thermal reliability of this planar process. Both discrete E/D-mode HEMTs

and integrated DCFL circuits exhibit proper functions within the temperature range

from room temperature (RT) to 350C, demonstrating a promising potential for GaN-

based high-temperature digital ICs. Secondly, to enhance the gate voltage swing and

suppress the gate leakage current at high temperatures, E-mode Si3N4/AlGaN/GaN

MIS-HFETs are adopted based on CF4 plasma treatment and a two-step Si3N4

deposition technique. In the new MIS structure, the forward gate bias can be applied

up to 7 V, the highest value reported in AlGaN/GaN HEMTs up to now. In addition,

E-mode AlGaN/GaN MIS-HFETs show no current collapse under pulse operation as

a result of the Si3N4 passivation effects in the access region. The DCFL ring

oscillator, which consists of E/D-mode AlGaN/GaN MIS-HFETs, reveals a stable


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operation from RT to 415C, indicating the excellent high-temperature working

capabilities. At last, an E-mode DG AlGaN/GaN HEMT, composed of an E-mode

and a D-mode gate electrode, is designed and fabricated. Compared to the E-mode

single-gate AlGaN/GaN HEMTs, a 9-dB gain improvement has been achieved at 2.1

GHz in the DG devices. This achievement can be attributed to the higher output

impedance and smaller feedback capacitance in DG architecture.


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CHAPTER 1

INTRODUCTION

1.1 Fundamentals of High Electron Mobility Transistors

The high electron mobility transistor (HEMT), which is also named as

heterostructure field-effect transistor (HFET), modulation doped field-effect

transistor (MODFET), two-dimensional electron gas field-effect transistor

(TEGFET), or selectively doped heterostructure transistor (SDHT), was invented

about 20 years ago. The first HEMT device was reported in 1980 [1], after the

successful growth of modulation doped AlGaAs/GaAs heterostructure [2]. By

employing two semiconductor materials with different band-gaps, an electron

potential well is formed at the hetero-interface between AlGaAs and GaAs. The

electrons are confined in this potential well to form a two-dimensional electron gas

(2DEG). Due to the two-dimensional feature of the electrons in this conduction

channel, the carrier mobility can be enhanced remarkably.

The first generation of HEMT structure was constructed in lattice-matched

GaAs-based AlGaAs/GaAs system, which has been widely studied [3] and used in

radio-frequency (RF), microwave and millimeter wave applications. Additional

material systems, including pseudo-morphic HEMT (i.e. with InGaAs channel in

GaAs-based material system) and InP-based InAlAs/InGaAs have also been studied

to achieve higher operating frequencies and lower noise.


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The fundamental characteristic of the HEMT structure is the conduction band

offset between the materials which construct the barrier and channel layers, that is,

the barrier layer has a higher conduction band while the channel layer has a lower

one. A potential well is then formed which can contain a large number of electrons to

form a 2DEG channel at the hetero-interface due to this conduction band offset. The

schematic structure and the energy-band profile of an AlGaAs/GaAs HEMT are

shown in Fig. 1.1.1 [4].

Semi-insulating Substate

(GaAs)

Undoped GaAs

Undoped AlGaAs

n-doped AlGaAs

S G D

EV EC

EFE

2DEG

Fig. 1.1.1 Schematic structure of an AlGaAs/GaAs HEMT and the correspondingenergy band profile.

In this case, the electrons in the 2DEG channel are provided by the modulation

doped barrier layer. The electrons are separated from the ionized donors by the

potential barrier at the hetero-interface and confined in a two-dimensional

conduction channel, which can reduce the scattering between the carriers and the

ionized donors. This feature ensures a high electron density and mobility, which

make HEMTs promising for high frequency and high power applications.


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d d

diEC

EFqVG

E

at VG,maxat VTH

)(

0

/

max

min

0max

dddEV

E

qnE

iG

s

++=

=

=

Fig. 1.1.2 Energy-band diagram of the metal/n-AlGaAs/GaAs system and theelectrostatic field distribution in the AlGaAs layer at the threshold voltage and VG,max.

In a HEMT, by placing a Schottky barrier (metal/semiconductor) gate above the

doped AlGaAs barrier layer, the 2DEG sheet charge concentration can be controlled

by applying an appropriate bias voltage. Figure 1.1.2 shows the energy-band diagram

of the metal/AlGaAs/GaAs system and the electrostatic field distribution in the

AlGaAs barrier layer at threshold voltage and maximum gate bias [5]. Where nS0 is

the maximum 2DEG sheet carrier concentration, d is the thickness of the n-doped

AlGaAs barrier, di is the thickness of the undoped AlGaAs spacer, d is the mean

distance of the 2DEG from the AlGaAs/GaAs hetero-interface.When the gate bias

exceeds the maximum value, VG,max, a zero-field or conduction region is created near

the center of the AlGaAs layer. With increasing the forward gate bias, this region


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forms a parasitic metal semiconductor field effect transistor (MESFET) and

effectively shields the 2DEG channel of the HEMT [6].

Metal AlGaAs GaAs

VG = 0

VG > 0

VG < 0

EF

EF

EF

EF

EF

EF

EC

EC

EC

EF

EF

EF

qVG

qVG

Fig. 1.1.3 Gate-bias-modulated conduction band diagram and 2DEG concentration ofan AlGaAs/GaAs HEMT.

Figure 1.1.3 demonstrates the mechanism of the gate-controlled 2DEG channel in

an AlGaAs/GaAs HEMT [4].With a zero gate bias, there is a 2DEG accumulated at

the hetero-interface, that is, the channel is on. By increasing the gate bias, the

conduction band is modulated and more electrons are accumulated in the 2DEG

channel,which provides higher sheet carrier density and larger current density in the


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channel.When the gate bias is lowered below the threshold voltage (Vth),the channel

is depleted and there are no electrons in the channel, that is, the channel is pinched

off and no current can go through under the gate.

With a Schottky contact as the gate electrode and two ohmic contacts as the

source and drain electrodes,a heterostructure field effect transistor can be formed on

an AlGaAs/GaAs wafer. The DC output and transfer current-voltage (I-V)

characteristics of a typical AlGaAs/GaAs HEMT device are shown in Fig. 1.1.4 [4].

Linear Saturated

gmVGS

VDS

IDS

IDS

VGS

gm

VTH

Fig. 1.1.4 Typical DC I-V characteristics of an AlGaAs/GaAs HEMT: (a) outputcurve; (b) transfer curve.

Table 1-1 Advantages of the HEMT structure.

High electron mobility Small source resistance HighfTdue to high electron velocity in large electrical fields High transconductance due to small gate-to-channel separation High output resistance

(a) (b)


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Compared with conventional Si-based electronic devices, HEMTs have the

following advantages listed in Table 1-1.

After the introduction of the field-effect transistor in the early 1960s, equivalent

circuit models were analyzed by many investigators. These models were modified

after the emergence of GaAs MESFET. After the realization of the HEMTs with

submicron gate length, these models were further modified and the most popular one

is shown in Fig. 1.1.5 [7].

+

Vg

-

im = gmVgexp(-j )

g0 Cds

rd

Ld

Cdp

rs

Ls

Cgs2+Cgp

Cgs1

rg

Cg

ri

Lg

G D

S

Cgd

im

Fig. 1.1.5 Equivalent circuit model for a HEMT, and the intrinsic circuit model isenclosed by the dashed line.

The equivalent circuit for the intrinsic HEMT is shown within the dashed

rectangular boundary, which includes the gate capacitance (Cg), the charging

resistance (ri), the output conductance (g0), and the drain-to-gate transconductance

(gm). The element Ci (not shown here), which arises due to the passive coupling


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between the drain and the channel, is not included. These intrinsic parameters,

together with the extrinsic ones, can be used to analyze and predict the AC operation

behavior of the HEMT. They can be extracted from the small-signal S-parameter

measurements. The origins of these elements are shown in Fig. 1.1.6 [8].

rS CgCgs1

rd

Cgs2Cgd

rg

Cds

2DEG

S DG

Fig. 1.1.6 The physical origin of the elements in the equivalent circuit model ofAlGaAs/GaAs HEMT.

Combined with the parameter extraction techniques, the equivalent circuit can be

used to characterize the performance of the devices. In the real applications, it is also

desirable to predict the ultimate potential of the devices performance or make a

decision which device should be chosen. Then, the first-order calculation of several

performance figures of merit (FOMs) of the active devices will be very useful for

making preliminary judgments. In most cases, the FOMs of interest include the

current gain cutoff frequency (or cutoff frequency, fT), power gain cutoff frequency

(or maximum frequency of oscillation, fmax), output power density (Pout), power


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added efficiency (PAE), linear gain (GT), minimum noise figure (NFmin), etc. These

FOMs are only first-order indicators of the ultimate performance limit of the devices.

However, these data can be used as a basis of primary comparison between active

devices.

As the frequency increases, the short-circuit current gain (|h21|) of a HEMT

device will decreases. The current gain cutoff frequency of a HEMT device is the

frequency where |h21| falls to unity. In the first order approximation, from the

equivalent circuit shown in Fig. 1.1.5,fTcan be driven as:

g

mT

C

gf

2=

The fT is an approximate criterion which can be used to compare the operation

speed limitation of the devices. In general, the device with a higherfT value usually

can operate at higher frequencies than the one with a lowerfT value. In the HEMT

devices, fT can also be represented in term of the saturation drift velocity of the

electrons in the 2DEG channel:

g

satT

L

vf

2= ,

where vsat is the saturation electron drift velocity and Lg is the gate (channel) length.

Obviously, higher electron velocity and smaller gate (channel) length will result in

higher current gain cutoff frequency.

(1.1)

(1.2)


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The power gain cutoff frequency, fmax, is the highest frequency at which power

gain can be obtained from the device. That is, the power gain of the device is unity at

fmax.As current gain cutoff frequency, fmax is an indicator of the ultimate operating

frequency of the device.Highfmax value is desirable in high frequency applications.

In microwave applications, where the power gain is mostly concerned,fmax attracts

more interest from the designers than fT does. Usually, for simplification, in the

definition of the power gain cutoff frequency, the power gain is the unilateral power

gain (U), so fmax is defined as the frequency at which U reaches unity. For HEMT

devices, the unilateral gain can be represented in terms of the two-port y-parameters

of the device:

)]Re(*)Re()Re(*)[Re(4

||

21122211

21221

yyyy

yyU

+

=

The expression offmax can be extracted from the device equivalent circuit shown

in Fig. 1.1.5. In the first-order approximation,fmax can be written as [9]:

gi

dsT

RR

Rff

+=

2max ,

whereRi is the channel charging resistance, Rg is the gate parasitic resistance, Rds is

the output resistance, and fT is the current gain cutoff frequency. This equation

(1.3)

(1.4)


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provides some useful relationship betweenfT andfmax when the device works at high

frequency.

IDS

(mA/mm)

Imax

Imin

KNEE

VOLTAGE

RL-Ropt

OFF-STATE

BREAKDOWN

CLASS-A

BIAS POINT

Vk VBRVDS (V)

Fig. 1.1.7 Schematic representation of a HEMT operating in Class A.

As mentioned previously, HEMT is a promising candidate for high frequency

and high power applications due to its high carrier mobility and high current

handling capability.The small-signal FOMs, fT and fmax, provide guidelines for the

frequency performance of HEMTs, while to evaluate microwave large signal (or

power) performance of them, some other FOMs should be considered. Two

important large-signal FOMs are the output power density (Pout) and the power added

efficiency (PAE). For class A operation, the theoretical maximum output power can

be found out by:

))((2

1minmaxmax, KBRout VVIIP = , (1.5)


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whereImax is the maximum channel current,Imin is the minimum drain current due to

the gate-drain and source-drain leakage, VBR is the off-state breakdown voltage of the

device, and VK is the knee voltage. This approximate equation of the maximum

output power is graphically presented in Fig. 1.1.7 [10], where the device is assumed

to work along the ideal load line (a straight line) with a constant knee voltage and an

adequate large-signal gain.

The other important microwave large-signal FOM is the power added efficiency,

PAE. For class A operation, the PAE of the device can be written in terms of the

power gain as:

=

=

=

aDC

aout

DC

inout

GP

GP

P

PPPAE

11

2

1)/11(,

where Ga is the power gain of the device. It can be found the maximum value of

PAE for class A operation approaches 50% with infinite Ga. For class B operation,

the PAE is higher, which has a maximum value of/4 (~78.5%).

1.2 Developments of AlGaN/GaN HEMTs

In early 1990s, with the successful growth of high-quality III-nitride epitaxial

films by advanced metal-organic chemical vapor deposition (MOCVD) technique,

the AlGaN/GaN heterostructure was demonstrated for the first time in 1991 [11].

Owing to their unique characteristics, such as large bandgap, high electric field

(1.6)


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strength, and good electron transport properties, GaN-based HEMTs are emerging as

promising candidates for high voltage, high power and high frequency applications

[12]. Intensive investigations have been carried out on GaN-based HEMTs and

significant progress has been made in the last decade [13]-[28].

Semi-insulating

Substrate

Undoped GaN

Undoped AlGaN

n-doped AlGaN

Fig. 1.2.1 Schematic structure of an AlGaN/GaN HEMT and the correspondingenergy-band profile.

Similar to the GaAs-based HEMTs, GaN-based HEMTs employ two kinds of

materials with different bandgaps as the barrier and channel layer. The most popular

one is AlGaN/GaN HEMTs. Due to the conduction band offset between AlGaN and

GaN, an electron potential quantum well is formed at the hetero-interface between

AlGaN and GaN. The electrons are confined in this potential well to form a 2DEG.

The electrons transport in a two-dimensional way, which can largely improve the

electron mobility. The schematic cross-section and the energy-band profile of the

AlGaN/GaN HEMT are shown in Fig. 1.2.1.


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As reported in [29], nitride-based semiconductors have a unique property

compared to GaAs system, a very strong polarization field within the crystal. This

polarization field has profound impacts on the electronic properties of GaN-based

heterostructures.

Ga-face N-face

Substrate Substrate

0001

0001

Fig. 1.2.2 Crystal structure of (a) Ga-faced and (b) N-faced wurtzite GaN

The polarization field in the nitride-based heterostructures comes from two parts,

the spontaneous polarization and the piezoelectric polarization. Due to the non-

central symmetry, nitrides exhibit a macroscopic spontaneous polarization field

along the hexagonal c-axis in the wurtzite lattice. In addition, nitrides have a strain-

induced piezoelectric polarization, which is much higher than that in the traditional

III-V semiconductors [30]. The direction of the polarization field in nitrides depends

on the polarity of the crystal [31], that is, whether its Ga-faced [Fig. 1.2.2 (a)] or N-

faced [Fig. 1.2.2 (b)]. Almost all MOCVD-grown nitrides are Ga-faced, while the

nitrides grown in MBE system are usually N-faced. With the assistance of the


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polarization field, a polarization charge density of 1013 cm-2 can be achieved in a

strained-Al0.3Ga0.7N/relaxed-GaN system [32].

Fig. 1.2.3 Band profiles of the AlGaN/GaN heterostructures with different AlGaNthickness, which demonstrate the surface states contribution to the 2DEG formation.

In the AlGaN/GaN heterostructure, the origin of 2DEG is quite different from that

in AlGaAs/GaAs system. Due to the strong polarization field in the AlGaN/GaN

heterostructure, a sheet carrier density of ~1013 cm-2 can be obtained at the

AlGaN/GaN interface without any modulation doping [33]. As doping concentration

is zero in this case, the 2DEG does not come from the conventional modulation

doping in the AlGaN layer. Up to now, the most popular model, proposed by

Ibbetson et al. [34], suggests that the donor-like surface states could serve as the

source of the electrons in the 2DEG channel. With the electrostatic field induced by

the polarization field in the AlGaN/GaN heterostructure, the band profile and the

electron distribution are modified and a large number of electrons transfer from the

donor-like surface states to the AlGaN/GaN hetero-interface that is lower in energy,


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forming a 2DEG. The mechanism of the surface states contribution to 2DEG can be

illustrated by Fig. 1.2.3 for an undoped AlGaN barrier sample. If the donor-like

surface state is sufficiently deep and lies below Fermi level, EF, there is no 2DEG in

the channel [Fig. 1.2.3 (a)]; when the barrier thickness increases and the surface state

energy level reaches EF, the electrons are then able to transfer from the occupied

states to empty conduction band states at the interface, creating 2DEG in the channel

and leaving positive surface charges behind, as shown in Fig. 1.2.3 (b).

Table 1-2 Historical Development of GaN-based HEMTs.

Year Event Authors Ref.1969 GaN by hydride vapor phase epitaxy Maruska and Tietjen [36]1971 GaN by MOCVD Manasevit et al. [37]1992 AlGaN/GaN two-dimensional electron gas Khan et al. [38]1993 AlGaN/GaN HEMT Khan et al. [35]

1994 Microwave AlGaN/GaN HFET Khan et al. [39]1996 Microwave power AlGaN/GaN MODFET Wu et al. [40]1999 Reveal current compression in GaN MODFET Kohn et al. [41]1999 6.9 W/mm @ 10 GHz GaN HEMT on SiC Sheppard et al. [42]2000 Surface passivated AlGaN/GaN HEMTs Green et al. [43]2004 30 W/mm @ 8 GHz GaN HEMT with field plate Wu et al. [16]2005 High performance enhancement-mode HEMT Cai et al. [44]

Due to the advantages of the GaN-based heterostructures, tremendous progress

has been made in the development of AlGaN/GaN HEMT since it was firstly

demonstrated by Khan et al. in 1993 [35]. Table 1-2 lists the most representative

developments of GaN-based HEMTs.


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1.3 Enhancement/Depletion-mode AlGaN/GaN HEMTs and Mixed-Signal

Applications

1.3.1 Synthesis of Enhancement-mode AlGaN/GaN HEMTs

In the AlGaN/GaN heterostructure, high-density 2DEG induced by spontaneous

and piezoelectric polarization effects presents the conventional AlGaN/GaN HEMTs

as depletion-mode (D-mode) transistors with a threshold voltage (Vth) typically

around -4 V. Usually, the Vth of the AlGaN/GaN HEMTs depends on the design of

the epitaxial structure, namely, the Al composition, Si doping concentration, and the

thickness of the AlGaN barrier. Methods that can further modify the threshold

voltage during the device fabrication stage will provide additional flexibilities in

device fabrication and circuit applications. When the threshold voltage is adjusted to

be positive, enhancement-mode (E-mode) operation is realized. Compared to the D-

mode HEMTs, E-mode devices allow elimination of negative-polarity voltage supply,

and therefore, reduce the circuit complexity and system cost significantly.

A common fabrication technique of modifying the HEMTs threshold voltage,

the so-called gate-recess technique, is to reduce the thickness of the barrier layer

under the gate metal. In the generally used AlGaN/GaN heterostructure for HEMTs,

where Al composition is in the range of 15 - 35% and the AlGaN barrier thickness is

around 20 nm, the reduction in the AlGaN thickness by the gate recess results in a

decreasing polarization-induced 2DEG density. And with the help of the gate metal

work function, the threshold voltage can be shifted positively. With a deep enough


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gate-recess etching, the Vth can reach a positive value and E-mode HEMTs are

formed, with the schematic diagram shown in Fig. 1.3.1 [45].

S D

GaN

AlGaNSiNx

Recessed-Gate

Fig. 1.3.1 Schematic diagram of an E-mode HEMT with the recessed gate.

For a conventional III-V compound semiconductor, such as GaAs and InP, there

are sufficient highly-selective chemical wet-etching recipes [46] that can be applied

to recess etching. The wet etching has the major advantage of low damages.

However, a compatible wet-etching method for AlGaN/GaN heterostructure is still

lacking up to now. As an alternative approach, a chloride-based dry inductively

coupled plasma reactive ion etching (ICP-RIE) has been employed to fulfill this task

by several groups [45], [47]-[51]. This approach can effectively modify the Vth of

AlGaN/GaN HEMTs to positive direction. However, the ICP-RIE etching will

introduce damages and defects to the AlGaN layer, which will affect the device

performance. The post-etching rapid thermal annealing (RTA) at 700C was found to

be able to repair the damages [48], [51]. But the RTA at such high temperatures will

not be compatible with the gate metal (i.e. Ni/Au) and has to be carried out prior to

the gate metal deposition. As a result, the photolithography of the gate electrode and


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recess etching has to be conducted separately, which brings undesirable complexity

to the device fabrication. In addition, the uniformity in the recess-etching depth and,

consequently the uniformity in the threshold voltage and gate capacitance, are

another challenging issue for this method.

Recently, our group demonstrated a technique of fabricating high-performance

self-aligned E-mode AlGaN/GaN HEMTs using the fluoride-based plasma treatment

[44], [52]-[53]. No change in the AlGaN thickness is required in this technology. The

control of the threshold voltage is realized through a modulation of energy band by

fluorine ions implanted in the AlGaN/GaN heterostructure during the plasma

treatment. As the fluorine ions have a strong electronegativity and are negatively

charged, the potential in the AlGaN barrier and the 2DEG channel can be effectively

raised. As a result, the Vth can be shifted to a positive value, and E-mode HEMTs can

be fabricated. A post-gate annealing at a gate-electrode-compatible temperature of

400C proves to be effective in recovering the plasma-induced damages.

The fluorine ions, which are incorporated into the AlGaN layer by CF4 plasma

treatment, are confirmed by secondary ion mass spectrum (SIMS) measurements [52].

It can be concluded from the SIMS results that the implanted fluorine ions have a

good thermal stability in the AlGaN layer up to 700C. According to our recent

DLTS (deep-level transient spectroscopy) observations, the fluorine ions

incorporated in the AlGaN barrier introduce a deep level state near the mid-bandgap.

Therefore, the fluorine ions are believed to provide negatively charged acceptor-like

states in the AlGaN layer. These fixed negative charges will cause an upward


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bending of the conduction band in the AlGaN layer, as shown in Fig. 1.3.2.

Compared to the untreated AlGaN/GaN HEMT structure [Fig. 1.3.2 (a)], the plasma-

treated structure has its conduction band minimum above Fermi level, indicating a

completely depleted channel and E-mode operation. In addition, the immobile

negatively charged fluorine ions raise the conduction band, leading to an additional

barrier height F, as shown in Fig. 1.3.2 (b). This enhanced barrier can significantly

suppress the gate Schottky diode current of the AlGaN/GaN HEMTs in both reverse

and forward bias conditions.

Fig. 1.3.2 Conduction band schematic diagrams of (a) conventional D-modeAlGaN/GaN HEMT and (b) E-mode HEMT with CF4 plasma treatment.

There have been several other reports on the fabrication of E-mode AlGaN/GaN

HEMTs besides gate recess etching and fluoride plasma treatment techniques. Using

a thin AlGaN barrier (10 nm), Khan et al. [54] realized an E-mode HEMT with a

peak transconductance of 23 mS/mm. Hu et al. [55] demonstrated an E-mode HEMT

with selectively re-grown pn junction gates and showed a peak transconductance of

10 mS/mm. Moon et al. [47] and Kumar et al. [48] used reactive ion etching for gate


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recess to fabricate E-mode AlGaN/GaN HEMTs, with large on-resistance [47] and

nonzero (~20 mA/mm) drain current at zero gate bias [48]. Started with a D-mode

HEMT, Endoh et al. [56] was able to convert it to E-mode HEMT using Pt-based

gate electrode annealed at high temperature. Such an approach requires a D-mode

HEMT with the threshold voltage already close to zero. Y. Uemoto et al. [26] also

realized the E-mode operation by growing p-AlGaN layer under the gate to lift up the

potential in the channel. The E-mode HEMT exhibits a peak transconductance of

about 70 mS/mm. But the hole injection will affect the device turn-off characteristics

in this p-AlGaN layer technology. The E-mode device characteristics are compared

in Table 1-3 among different fabrication technologies. It seems that the E-mode

HEMTs fabricated by CF4 plasma treatment exhibit excellent DC and RF

performance, compared to other methods.

Table 1-3 E-mode AlGaN/GaN HEMT performance comparison

Ref TechnologyGate

length

Imax

(mA/mm)

Peakgm

(mS/mm)

Vth

(V)

fT& fmax

(GHz)

[54] Thin AlGaN 1 m --- 23 0.05 ---

[55] PN junction gate 10 m 40 10 --- ---

[47] Gate recess etch 0.2 m 100 85 0 24 / 45

[48] Gate recess etch 1 m 470 248 0.075 8 / 26

[56] Pt-based gate 0.12 m 450 230 0 58 /109

[26] P-layer gate 2 m 200 70 1 4.2 / 10.7

[44] Plasma treatment 1 m 313 151 0.9 10 / 34.3


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1.3.2 Mixed-signal applications of E/D-mode AlGaN/GaN HEMTs

Table 1-4 Properties of competing materials in power electronics.

Semiconductor

(commonly used compounds)

Characteristic Unit Silicon

Gallium

arsenide

(AlGaAs/

InGaAs)

Indium

phosphide

(InAlAs/

InGaAs)

Silicon

carbide

Gallium

nitride

(AlGaN/

GaN)

Bandgap eV 1.1 1.42 1.35 3.26 3.49

Electron mobility

at 300 K

cm2/Vs 1500 8500 5400 7001000-

2000

Saturated (peak)

electron velocity

x107

cm/s

1.0

(1.0)

1.3

(2.1)

1.0

(2.3)

2.0

(2.0)

1.3

(2.1)

Critical breakdown

fieldMV/cm 0.3 0.4 0.5 3.0 3.0

Thermal

conductivityW/cmK 1.5 0.5 0.7 4.5 >1.5

Relative dielectricconstant

r 11.8 12.8 12.5 10.0 9.0

In the RF and microwave power amplifier markets, a variety of PA technologies

are competing each other, such as Si lateral-diffused metal-oxide-semiconductors

and bipolar junction transistors, GaAs metal-semiconductor field-effect transistors

(MESFETs), GaAs heterojunction bipolar transistors, SiC MESFETs, and GaN

HEMTs. Compared to other competing materials, the material properties of GaN are

presented in Table 1-4 [57]. Wide bandgap, large breakdown electric field and high

electron saturated velocity make it as an excellent candidate for RF and microwave

power amplifiers. The competitive advantages of GaN-based amplifiers for a


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commercial product are described in Table 1-5 [13]. The first column states the

required performance benchmarks for any power device technology and the second

column lists the enabling features of GaN-based devices that fulfill this need. The

last column summarizes the resulting performance advantages at the system level and

to the customer. The highlighted features offer the most significant product benefits.

Table 1-5 Competitive advantages of GaN devices

Need Enabling Feature Performance Advantage

High Power DensityWide Bandgap, HighField

Compact, Ease of Matching

High Voltage Operation High Breakdown Field Eliminate/Reduce Step Down

High Linearity HEMT Topology Optimum Band Allocation

High Frequency High Electron Velocity Bandwidth, m-Wave/mm-wave

High Efficiency High OperatingVoltage

Power Saving, ReducedCooling

Low NoiseHigh Gain, HighVelocity

High Dynamic Range receivers

High TemperatureOperation

Wide BandgapRugged, Reliable, ReducedCooling

Thermal Management SiC SubstrateHigh Power Devices withReduced Cooling Needs

Technology LeverageDirect Bandgap:Enable for Lighting

Driving Force for Technology:Low Cost

Besides RF and microwave power amplifiers, AlGaN/GaN HEMTs also exhibit

the promising potential to construct digital integrated circuits (ICs), especially for the

operations at high temperature that is impossible for silicon or GaAs-based

technologies. The high-temperature digital ICs can provide the enabling technology

in intelligent control and sensing circuits for automotive engines, aviation systems,


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chemical reactors and well-logging for oil exploration systems [58]. Due to lack of p-

channel AlGaN/GaN HEMTs, a circuit configuration like CMOS can not be

implemented yet. Using n-channel HEMTs, direct-coupled FET logic (DCFL), as

shown in Fig. 1.3.3, which features integrated E/D-mode HEMTs, offers the simplest

circuit configuration [59]. For a long time, the development of GaN-based digital ICs

has been hindered by the lack of compatible integration process for both D-mode and

E-mode AlGaN/GaN HEMTs. As a tradeoff, Hussain et al. [60] used an all-D-mode-

HEMT technology and buffered FET logic (BFL) configuration to realize an inverter

and a 31-statge ring oscillator that includes 217 transistors and two negative voltage

supplies.

Fig. 1.3.3 DCFL circuit schematics of (a) E/D-mode HEMT inverter, (b) NOR gateand (c) NAND gate logic circuits.

With the development low-damage Cl2-based ICP-RIE technology, Micovic et al.

[61] applied the technology of two-step gate recess etching and used plasma-

enhanced chemical vapor deposition (PECVD) grown SiN as the gate metal


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deposition mask to fabricate E-mode HEMTs, which were integrated with the D-

mode AlGaN/GaN HEMTs together. By using this technology, they demonstrated a

31-stage DCFL ring oscillator. Recently, our group developed a technique featuring

fluoride-based plasma treatment and post-gate annealing to realize self-aligned E-

mode AlGaN/GaN HEMTs. Based on CF4 plasma treatment, a monolithic integration

of E/D-mode AlGaN/GaN HEMTs for digital ICs has been demonstrated [53], [62].

Compared to the technology of two-step gate recess etching, the fluoride-based

plasma treatment technique saves one mask for fabricating GaN-based digital ICs.

1.4 Objective of This Work

This work mainly focuses on applying fluoride-based plasma treatment technique

to realize the integration of enhancement/depletion-mode HEMTs for GaN-based

mixed-signal circuit applications. New isolation technology and new device structure

are developed to improve the circuit and device performance. In addition, the high-

temperature characteristics of AlGaN/GaN HEMTs and circuits have been

investigated in detail for GaN-based high-temperature digital IC applications.

Chapter 2 reports a planar fabrication technology for integrating

enhancement/depletion-mode AlGaN HEMTs. The technology relies heavily on CF4

plasma treatment, which is used in two separate steps to achieve two objectives: 1)

active device isolation; and 2) threshold voltage control for the enhancement-mode

HEMT formation. Compared to the standard mesa etching technique, the plasma


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treatment can achieve the same isolation results, and show no device DC and RF

performance degradation after a 153-hour thermal stress measurement. The device

and circuit high-temperature characterizations are also carried out from room

temperature to 350C.

Chapter 3 demonstrates an enhancement-mode Si3N4/AlGaN/GaN metal-

insulator-semiconductor HFETs by combing the CF4 plasma treatment technique and

a two-step Si3N4 deposition process. The threshold voltage has been shifted from -4

V (for depletion-mode substrate) to 2 V using this technique. The forward gate bias

of the E-mode MIS-HFETs is as large as 7 V, at which a maximum current density of

420 mA/mm is obtained. At the same time, the depletion-mode AlGaN/GaN MIS-

HFETs are fabricated on the same chip. A direct-coupled FET logic inverter and 17-

stage ring oscillator have been demonstrated by integrating enhancement/depletion-

mode AlGaN/GaN MIS-HFETs.

Chapter 4 contains the work of AlGaN/GaN dual-gate HEMTs, composed of an

enhancement-mode gate and a depletion-mode gate. Compared to the enhancement-

mode single-gate devices, the dual-gate AlGaN/GaN HEMTs have comparable DC

characteristics, but achieve a 9-dB gain improvement at 2.1 GHz in small signal RF

measurements. The gain improvement can be attributed to the larger output

impedance and smaller feed back capacitance in dual-gate structure.

Finally, the work is summarized in Chapter 5, and future plan for the thesis work

is also provided.


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CHAPTER 2

Temperature Dependence and Thermal Stability of Planar-Integrated

Enhancement/Depletion-mode AlGaN/GaN HEMTs and Digital Circuits

2.1 Motivation of Planar Integration of E/D-mode AlGaN/GaN HEMTs for

GaN-based High Temperature Digital Circuits

With the wide bandgap, excellent thermal and chemical stability, AlGaN/GaN

high-electron mobility transistors (HEMTs) are inherently attractive for applications

in high temperature electronics [53], [61], [63]-[66]. The direct-coupled FET logic

(DCFL) circuit, which features integrated enhancement/depletion-mode (E/D-mode)

HEMTs, offers a simple configuration for digital integrated circuits. Recently, the

DCFL digital ICs, based on E/D-mode AlGaN/GaN HEMTs, have been

demonstrated using a recess gate [61] and a fluoride-based plasma treatment

technique [53], [62], both of which used an inductively coupled plasma (ICP) mesa

etching to achieve the active device isolation. However, the three-dimensional mesas

may impose significant limitations on the minimum size realized by

photolithography and are not desirable for digital IC applications that require high-

density and high-uniformity circuit integrations. Thus, a planar process is critical to

the success of GaN-based digital IC technology, as seen from the successful

development of commercial GaAs MESFET ICs [67]-[68].

For the planar GaN-based device isolation, most of the works have been focused

on implanting high energy H+, He+, N+, Mg+ or O+ ions that introduce significant


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damages to crystal lattice and cut off the current path [69]-[73]. A multiple energy

Zn+ implantation [74], N+ implantation [75], and P+/He+ co-implantation [76] have

been implemented in the fabrication of AlGaN/GaN HEMTs. Recently, our group

developed a technique featuring fluoride-based plasma treatment and post-gate

annealing to realize E-mode AlGaN/GaN HEMTs [44], [52], [77]-[78]. The basic

idea is to introduce fluorine ions into the AlGaN barrier under the gate region.

Because of the strong electronegativity of the fluorine ions, they can provide the

fixed negative charges in the AlGaN layer, effectively depleting the two-dimensional

electron gas (2DEG) in the channel [52]. The electron-depletion capability of the

fluorine ions indicates the possibility of using fluorine plasma treatment for device

isolation. However, the isolation mechanism lies in the surface potential modulation

rather than the physical damages as in the case of ion implantation.

In this work, we employ the fluorine plasma treatment technique to achieve the

active device isolation in a planar integration of E/D-mode AlGaN/GaN HEMTs.

Without any dry etching for mesa formation and gate recess, the plasma treatment

can achieve the same isolation between active devices as the three-dimensional mesa

approach and both D-mode and E-mode HEMTs are fabricated on the same chip.

Since the GaN-based digital ICs are attractive for high-temperature applications

and thermal stability is always an important issue in any device isolation techniques,

we will report the detailed investigation of the temperature dependence and thermal

stability of the planar-integrated E/D-mode AlGaN/GaN HEMTs and digital

integrated circuits. High-temperature characterizations of E/D-mode HEMTs, DCFL


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inverter and ring oscillator are conducted from room temperature (RT) up to 350C.

At 350 C, the ring oscillator still functions properly. In addition, the thermal stress

measurements (at 350C) are carried out to evaluate the thermal reliability of the

planar process. After 153-hour thermal stress, the E/D-mode HEMTs show very

small degradation in DC and RF performances, suggesting the excellent thermal

stability in the plasma-induced inter-device isolation.

2.2 Device Structure and Fabrication

Fig. 2.2.1 Schematic cross-section of the AlGaN/GaN HEMT device.

The AlGaN/GaN HEMT structures, with the schematic cross section shown in

Fig. 2.2.1, are grown on c-plane sapphire substrates in an Aixtron AIX 2000 HT

metal-organic chemical vapor deposition (MOCVD) system. The HEMT structure

consists of a ~ 50-nm thick low temperature GaN nucleation layer, a 2.5-m thick


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unintentionally doped GaN buffer layer, and an AlGaN barrier layer with a nominal

30% Al composition. The barrier layer is composed of a 3-nm undoped spacer, a 21-

nm carrier supplier layer doped with Si at 2x1018 cm-3, and a 2-nm undoped cap layer.

Hall measurements were conducted on the sample at room temperature through a

Hall Bridge pattern fabricated on the sample, with the layout shown in Fig. 2.2.2.

The room temperature hall measurements of the structure yield an electron sheet

density of 1.3 x 1013 cm-2 and an electron mobility of 950 cm2/Vs.

Fig. 2.2.2 Layout of the Hall Bridge for Hall measurements.

The process flow is illustrated in Fig. 2.2.3. At first, the source/drain ohmic

contacts of E/D-mode HEMTs are formed simultaneously by a deposition of e-beam

evaporated Ti/Al/Ni/Au (20 nm/150 nm/50 nm/80 nm) and rapid thermal annealing

(RTA) at 850C for 30 s, as shown in Fig. 2.2.3 (a). Secondly, the active regions for

both E/D-mode devices are patterned by photolithography, which is followed by the

CF4 plasma treatment in a reactive ion etching (RIE) system [Fig. 2.2.3 (b)]. The

plasma power is 300 W, and the treatment time is 100 s. The gas flow is controlled to


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33

Fig. 2.2.3 Schematics showing the process flow of E/D-mode HEMTs: (a) ohmiccontact; (b) active region definition by plasma treatment; (c) D-mode gate formation;

(d) E-mode gate definition and plasma treatment; (e) SiN passivation.


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34

be 150 sccm, and the DC bias is set to be 0 V. This step is used to form the device

isolation. As pointed in Fig. 2.2.3 (b), the isolation regions are the locations where a

large amount of F- ions are incorporated in the AlGaN layers, and then deplete the

2DEG in the channel. Next, the D-mode HEMTs gate electrodes are patterned by

the e-beam evaporation of Ni/Au (50 nm/300 nm) and liftoff [Fig. 2.2.3 (c)].

Subsequently, the E-mode HEMTs gate electrodes and interconnections are defined.

Prior to the e-beam evaporation of Ni/Au, the gate regions are treated by CF4 plasma

at 170 W for 150 s, as shown in Fig. 2.2.3 (d). This step performs the function of

converting the treated gate region from D-mode to E-mode [44], [52]. A 200-nm-

thick SiN passivation layer is deposited by the PECVD, and the probing pads are

opened [Fig. 2.2.3 (e)]. At last, the sample is annealed at 400C for 10 min to repair

the plasma-induced damage in the AlGaN barrier and the channel of the E-mode

HEMTs. The layout for device fabrication is shown in Fig. 2.2.4, and more process

details can be found in Appendix A.

Source

Source

DrainGate

Fig. 2.2.4 Layout for the AlGaN/GaN HEMTs fabrication


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35

As a comparison, the D-mode devices are also fabricated on another piece of

sample from the same substrate by standard process, in which Cl2/He ICP etching is

used to define a mesa as the device active region. For the DCFL inverter and ring

oscillator shown in this paper, the E-mode HEMT driver is designed with a gate

length, gate-source spacing, gate-drain spacing, and gate width of 1.5, 1.5, 1.5, and

50 m, respectively; the D-mode load is designed with a gate length, gate-source

spacing, gate-drain spacing, and gate width of 4, 3, 3, and 8 m, yielding a ratio

=(WGE/LGE)/(WGD/LGD) of 16.7. The discrete E-mode and D-mode HEMTs with 1.5

x 100 m2 gate dimensions are also fabricated by planar process for DC and RF

characterizations.

Figure 2.2.5 shows the microscopy photos of the overall and zoom-in views of

the HEMT devices we fabricated.

Fig. 2.2.5 Microscopy photos of the fabricated HEMT devices: (a) overall view; and(b) zoom-in view of the active region.

(a) (b)


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2.3 Discrete E/D-mode AlGaN/GaN HEMTs by Planar Process

2.3.1 Temperature Dependence

For the E/D-mode HEMTs fabricated by the planar process, the DC output

characteristics are plotted in Fig. 2.3.1. The peak current density for D-mode and E-

mode HEMTs are about 730 and 190 mA/mm, respectively. Both E-mode and D-

mode devices can be pinched off completely when gate bias is below threshold

voltage. The current drop in D-mode HEMT under high gate bias is due to the high

current level and self heating effects during device operation. This current

degradation can be solved using SiC substrate with better thermal conductivity,

instead of sapphire. The device DC measurement details can be found in Appendix B.

Fig. 2.3.1 DC output characteristics of (a) D-mode HEMT and (b) E-mode HEMT bythe planar process

Figure 2.3.2 shows the DC transfer characteristic comparison between planar

process and standard mesa etching technology. It can be seen that the D-mode

HEMT drain leakage current for planar process is about 0.3 mA/mm, which has

0 2 4 6 8 10

0

200

400

600

800 (a)VGS = -6V ~ 1V; step = 1V

ID(mA/mm)

VDS

(V)0 2 4 6 8 10

0

50

100

150

200 (b)VGS = 0V ~ 3.5V step = 0.5V

ID(mA/mm)

VDS

(V)


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37

reached the same level as the devices fabricated by standard mesa etching. In

addition, both of them exhibit comparable drain current and transconductance (gm)

performance, as seen from Fig. 2.3.2. We also measure the leakage current between

two pads (400 x 100 m2) with the spacing of 150 m. At the DC bias of 10 V, the

leakage current by planar process is about 38 A, at the same level of the standard

mesa etching sample (~30 A). From all results above, we can conclude that,

compared with ICP mesa etching, the fluoride-based plasma treatment can achieve

the same level of device isolation, enabling a complete planar integration process.

The E-mode HEMTs exhibit smaller transconductance compared to the D-mode

devices, due to the incomplete recovery of the plasma induced damage which causes

a slight mobility reduction [44], [52].

Fig. 2.3.2 Transfer characteristics comparison between the planar process and thestandard ICP mesa etching process: (a) drain current and (b) transconductance

comparison. The source-drain voltage (VDS) is fixed at 10 V.

To evaluate the temperature dependence of the planar-integrated E/D-mode

HEMTs, on wafer high-temperature characterizations of the devices are performed

-10 -8 -6 -4 -2 0 2 410

-1

100

101

102

103 (a)

ID(mA/mm)

VGS

(V)

Planar D-HEMTPlanar E-HEMTStd. D-HEMT

VDS

= 10 V

-10 -8 -6 -4 -2 0 2 4-20

0

20

40

60

80

100

120

140 (b)

Gm(mS/mm)

VGS


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38

from RT (25C) to 350C in the air ambient. Figure 2.3.3 shows the I-V transfer

characteristics of the D-mode HEMTs by planar process within the temperature

range of 25C ~ 350C. It can be seen that both the drain current and

transconductance drop as the temperature rises. When gate is biased at 1 V, the

maximum drain current density (Imax) decreases by 48% at 350C compared to RT,

and the peakgm drops by 47% at 350C. The current and gm reductions at high

temperatures can be attributed to the mobility degradation of 2DEG [79]. The off-

state leakage current increases when temperature rises [Fig. 2.3.3 (a)], but still in an

acceptable level even at 350C. It was well known that the intrinsic carrier excitation

in semiconductor will be more serious at high temperatures due to higher thermal

activation energy, and the device will become leakier, leading to larger off-state

leakage current at high temperatures.

Fig. 2.3.3 D-mode HEMTs transfer characteristics comparison at differenttemperatures: (a) drain current and (b) transconductance.

-10 -8 -6 -4 -2 0 210

-1

100

101

102

103

104

(a)

ID(mA/mm)

VGS

(V)

RT

100oC

150oC

250oC

350oC

VDS

= 10 V

-10 -8 -6 -4 -2 0 2

0

40

80

120

160(b)RT

100oC

150oC

250oC

350oC

VDS

= 10 VGm(mS/mm)

VGS

(V)


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Fig. 2.3.4 E-mode HEMTs transfer characteristics comparison at differenttemperatures: (a) drain current in log scale, (b) drain current in linear scale and (c)

device transconductance.

The E-mode HEMTs transfer characteristics at different temperatures are given

in Fig. 2.3.4. The threshold voltage (Vth) is defined as the gate bias intercept of the

linear extrapolation of the drain current from the point of peakgm in transfer curves.

Both the threshold voltage and pinch-off source-drain leakage current (Ileak) are

plotted against the temperature for E/D-mode HEMTs in Fig. 2.3.5. When the

temperature rises from RT to 350C, Ileak increases from 0.29 to 1.16 mA/mm for D-

mode HEMTs, while it increases from 0.20 to 0.53 mA/mm for E-mode HEMTs. A

significant difference is observed in the threshold voltage shift between D-mode and

E-mode HEMTs at high temperatures. The threshold voltage of D-mode HEMTs

-2 -1 0 1 2 3

0

20

40

60

80

100

120

140

Vth(350

oC)

Vth(RT)

(b)

ID(m

A/mm)

VGS

(V)

RT

350oC

VDS

= 10 V

-6 -4 -2 0 2 410

-1

100

101

102

(a)

ID(m

A/mm)

VGS

(V)

RT

100oC

150oC

250oC

350oC

VDS = 10 V

-6 -4 -2 0 2 4

0

20

40

60

80

100

120 (c)RT

100oC

150oC

250oC

350oC

VDS

= 10 V

Gm(m

S/mm)

VGS

(V)


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40

changes little at high temperatures, as seen from Fig. 2.3.3 and Fig. 2.3.5. But the E-

mode HEMTs Vth shifts to the negative direction when the temperature increases. As

shown in Fig. 2.3.4 (b), the E-mode HEMTs Vth varies from 1.14 V at RT to 0.77 V

at 350C, exhibiting a temperature coefficient of -1.14 mV/K. But within the whole

temperature range (RT ~ 350 C), the E-mode device keeps its threshold voltage as a

positive value all the time.

0 50 100 150 200 250 300 350 400-0.5

0.0

0.5

1.0

1.5

2.0

-5

-4

-3

-2

-1

0

1

2

,

,

Ileak

(mA/mm)

Temperature (oC)

E-mode HEMT

D-mode HEMT

Vth

(V)

Fig. 2.3.5 Temperature dependence of threshold voltage (Vth) and off-state drainleakage current (Ileak) for E/D-mode HEMTs by the planar process.

The different trends in the Vth-temperature dependence between the E-mode and

D-mode HEMTs could be due to the presence of fluorine ions in the AlGaN layer of

the E-mode HEMTs. As we mentioned before, the fixed fluorine ions have played a

key role in shifting Vth during the formation of E-mode HEMTs. According to our

recent DLTS (deep-level transient spectroscopy) measurement [80] and

photoconductivity measurement, the fluorine ions incorporated in the AlGaN layer


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41

introduce acceptor-like deep-level states that are near the mid-bandgap. As the

temperature increases, some of the electrons confined in the fluorine ions can be

thermally excited, leading to a reduction in the number of the negatively-charged

fluorine ions in the AlGaN layer. Therefore, the E-mode HEMTs Vth tends to shift to

the negative direction as the temperature rises. Even with this negative shift in Vth,

the E-mode HEMTs maintained a positive threshold voltage throughout the entire

high temperature testing, e.g., Vth is 0.77 V even at 350C [Fig. 2.3.4 (b)]. It should

be noted that the fluorine treatment technique is robust enough to allow us to adjust

and optimize the threshold voltage at the specified temperature by changing the

fluorine plasma treatment dose.

Figure 2.3.4 (a) and (c) reveal that the E-mode drain current decreases 26% at the

same bias andgm drops 47% at 350C compared to RT. The current reduction of E-

mode HEMTs is much smaller than D-mode HEMTs (48%) due to the different shift

occurred in the E-mode HEMTs Vth. At high temperatures, the E-mode HEMTs

exhibit a more negative Vth compared to RT, which will help to increase the current

density; in D-mode operation, Vth changes little at high temperatures, leading to a

larger current drop than E-mode HEMTs. Nevertheless, both E-mode and D-mode

AlGaN/GaN HEMTs show stable operation at 350C, indicating good thermal

stability of the planar process based on CF4 plasma treatment.

The high-temperature characteristics of sub-threshold slope are also investigated

for both E-mode and D-mode HEMTs, as shown in Fig. 2.3.6. From the transfer


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42

curve in log scale, the HEMT sub-threshold slope (S) can be defined by the following

equation [81],

( )[ ]DGS

Id

dVS

log= .

From Fig. 2.3.6, we can see the drain current slopes below threshold voltage become

smaller at 350C than RT for both E-mode and D-mode HEMTs, indicating a larger

Svalue. The sub-threshold slopes at different temperatures have been summarized in

Fig. 2.3.7. The Svaries from 248 mV/dec at RT to 664 mV/dec at 350C for D-mode

HEMT, while it increases from 464 to 757 mV/dec for E-mode device. As we

discussed before, the electron mobility decreases with temperature increased. When

gate bias is close to device threshold voltage, the electrons begin to accumulate under

the gate and form 2DEG. But the accumulation rate will be affected due to the

mobility degradation at high temperatures, leading to a larger sub-threshold slope.

-10 -8 -6 -4 -2 0 2 410

-1

100

101

102

103

D-mode RTD-mode 350oC

ID(mA/mm)

VGS

(V)

E-mode RT

E-mode 350oC

Fig. 2.3.6 Sub-threshold slope characteristic comparison between RT and 350C

(2.1)


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43

0 100 200 300 400

200

400

600

800

S(mV/

dec)

Temperature (oC)

E-mode SD-mode S

Fig. 2.3.7 Sub-threshold slope characteristics from RT to 350C.

Fig. 2.3.8 Schematics of gate controlling capability in sub-threshold region for (a) D-mode and (b) E-mode HEMTs.

Figure 2.3.7 also shows us that the sub-threshold slope in E-mode HEMT is

larger than D-mode HEMT within the temperature range of 25C ~ 350C. But the

difference between E-mode and D-mode HEMT keeps decreasing as temperature

increases. The sub-threshold slope reveals the gate controlling capability to the

channel, which can be illustrated in Fig. 2.3.8. For D-mode HEMT, when gate bias is

close to threshold voltage, the electrons accumulate in the channel. At that time, the

static electric field starts from gate metal, goes through the AlGaN layer, and ends at


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2DEG in the channel, as shown in Fig. 2.3.8 (a). For E-mode HEMT, a large number

of fluorine ions are located in the AlGaN layer, as we mentioned before. The electric

field will be stopped at these negative ions in AlGaN layer, so that part of electric

field will be shielded in E-mode HEMT [Fig. 2.3.8 (b)]. Therefore, compared to D-

mode HEMTs, the gate controlling capability will be depressed by fluorine ions in E-

mode devices, resulting in a larger sub-threshold slope. At high temperatures, part of

fluorine ions will lose electrons due to higher electron thermal energy, and threshold

voltage becomes more negative. So the fluorine ion shielding effects can be released

to some extent in E-mode HEMTs, and the behavior of E-mode HEMTs will be

closer to D-mode devices. Then the difference in S between E-mode and D-mode

HEMTs is decreased at high temperatures, as given in Fig. 2.3.7.

2.3.2 Thermal stability

Fig. 2.3.9 E/D-mode HEMTs DC characteristic comparison before and after high-temperature measurements.

-10 -8 -6 -4 -2 0 2 410

-1

100

101

102

103

104

(a)VDS

= 10 V

ID(m

A/mm)

VGS

(V)

, E/D-HEMT ID

before HT

, E/D-HEMT ID

after HT

-10 -8 -6 -4 -2 0 2 4

0

20

40

6080

100

120

140

160

180

(b)

, E/D-HEMT Gm before HT, E/D-HEMT Gm after HT

VDS

= 10 V

Gm(m

S/mm)

VGS

(V)


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45

When high-temperature measurements are finished, we re-measure the E/D-mode

HEMTs I-V characteristics. As shown in Fig. 2.3.9, the device performance shows

little difference before and after high-temperature measurements.

0 20 40 60 80 100 120 140 160

10-1

100

101

102

103

50

100

150

200

250

, D/E-HEMT ILeakID

(mA/mm)

Time (hours)

, D/E-HEMT Imax

, D/E-HEMT Peak gm

Maxim

umg

m

(mS/mm)

Fig. 2.3.10 The variations of the peak drain current density (Imax), off-state draincurrent (Ileak) and maximum transconductance (gm) during thermal stress up to 153

hours at 350C for E/D-mode HEMTs fabricated by the planar process.

The device thermal stress measurements are also carried out to evaluate the

thermal stability of the planar process further. The sample is thermally stressed at

350C for hours. DC and RF measurements are performed at various stress time.

Figure 2.3.10 shows the variations of the maximum current density Imax, off-state

leakage currentIleak, and the peak transconductance gm with different stress time up

to 153 hours. It can be seen that, for both E-mode and D-mode HEMTs by planar

process, no obvious performance degradations occur during the 153-hour thermal

stress testing. That indicates that the thermal stability for the planar process is pretty

good at 350C at least.


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46

-5 -4 -3 -2 -1 0 1 2 3

0

10

20

30

40

50

60

Ft&Fmax

(GHz)

VGS

(V)

, D-HEMT Ft & Fmax Before HT, D-HMET Ft & Fmax After HT, E-HEMT Ft & Fmax Before HT, E-HEMT Ft & Fmax After HT

Fig. 2.3.11 Small signal RF characteristics comparison before and after thermal

stress for both E-mode and D-mode HEMTs by the planar process.

On wafer small signal RF characterizations are also performed before and after

153-hour thermal stress from 0.1 to 39.1 GHz on E/D-mode HEMTs fabricated by

planar process. The RF measurement details can be found in Appendix B. As shown

in Fig. 2.3.11, the E/D-mode HEMT RF characteristics remain the same after a long

time thermal stress. The maximum current gain cutoff frequency (fT) and maximum

power gain cutoff frequency (fmax) are about 11.5 and 35.3 GHz respectively for D-

mode HEMT; the maximumfTandfmax are 8.3 and 28.9 GHz for E-mode ones.

2.4 Planar-Integrated DCFL Digital Circuits

2.4.1 DCFL Inverters

The circuit schematic of an E/D-mode DCFL inverter is given in Fig. 2.4.1,

where the D-mode HEMT is used as an active load and the E-mode HEMT is used as

a driver to drive this active load.


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47

Fig. 2.4.1 Schematic design of E/D-mode AlGaN/GaN DCFL inverter.

Fig. 2.4.2 Static voltage transfer curves of an E/D-mode HEMT DCFL inverter at (a)room temperature (RT) and (b) 350C.

Figure 2.4.2 shows the inverter static voltage transfer characteristics (the solid

square curves) and the inverter current consumption (the solid circle curves) at RT

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

10-3

10-2

10-1

100

101

Vout(V)

Vin (V)

(a)

IDD

(mA)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50.0

0.5

1.0

1.5

2.0

2.5

3.03.5

10-2

10-1

100

101

(b)

Vout(V)

Vin (V)

IDD

(mA)

wang ruonan thesis

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