wafer level process formation of a polymer isolated chip … · wafer level process formation of a...
TRANSCRIPT
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Harry Gee ON Semiconductor
WAFER LEVEL PROCESS FORMATION OF A POLYMER ISOLATED CHIP SCALE PACKAGE
Presented to the Santa Clara Valley Chapter,IEEE CPMT SocietyTuesday, November 22, 2016
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Small Silicon CSP device
Assembly Issue
Polymer Isolation Process Module
Experimental Results
Conclusion
Q & A
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• 2 Lead Chip Scale Package 0201/01005 sized devices
• 100% of the CSP area is the silicon
• Using a 01005 sized CSP device occupies less board area
compared to the same sized die built in a plastic molded
package
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01005 0201
• More than Two Thousand 01005
parts able to fit on top of a dime
• Dime thicker than six 01005 parts
Dime Diameter: 17.91 mm
Dime Thickness: 1.35 mm
01005 sized CSP
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Solder Bridge on the CSP end
(CSP tilted at the end)
Solder Bridge on CSP side
(CSP tilted to one side)
Silicon Low Profile Bump
Copper Copper
Solder Paste
Short/Leakage contributing factors
• Short Bump Height (Low Profile)
• Solder Paste Proximity to CSP Edge
• Solder Stencil to Pad Alignment
• CSP placement accuracy and tilt
Excess Solder (Short between bare
silicon die sidewall and the PCB
pad)
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Silicon
Solder
CSP
Solder
0201 CSP Tilt
(Sidewall Bridging) Close up image
Of sidewall Solder Bridging
Short causes assembly rework and added cost
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Silicon
Polymer Isolation
Passivation Solder Bump
Top Metal
Silicon
Passivation
Solder Bump
Top Metal
Conventional Bare Silicon CSP 5-Side Polymer Isolated CSP
• About 70% of a 0201/01005 CSP area is available for silicon circuits
• Area lost due from the saw street region
• Silicon removed from the saw street & replaced with a polymer
• No lost in silicon real estate area with the addition of the polymer isolation
• Polymer Isolation on silicon sidewall prevents the assembly short issue
• Polymer on the backside prevents short to the silicon backside
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1) Mount Wafer to Carrier
Substrate
2) Silicon Wafer Backgrind Carrier
Silicon
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3) Scribe line Silicon
Trench Mask
Carrier
Silicon
Photoresist
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4) Silicon Trench Etch
Suitable for products that
have Test Structures and
Dummy Fill in the Scribe
Line region.
Carrier
Silicon
5) Resist Clean
Carrier
Silicon
Photoresist
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6)Polymer Coat & Cure
Carrier
Silicon
Polymer Isolation
Final Probe done after carrier removal
Screens out dies damaged from defects at Silicon Etch Module
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Photoresist
Silicon
Top Metal Carrier
Infrared (IR) Topside Illumination
IR Detector
Stepper
Microscope
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Alignment Feature
IR Camera
(Stepper)
• Develop Inspection (IR Scope)
Check Pattern Alignment
Product & Misalignment Structure
• CD Measure
Silicon Silicon
After Silicon Plasma Etch
Carrier
Silicon Etch Space to
Front side active Silicon Devices
(7.5 um)
Alignment is important
Device
• Wafer Probe done after
Silicon Plasma Etch Module
• Reject dies that may be
Damaged from the silicon
etch
Top Metal Photoresist
Photoresist
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0201 Sized Polymer Isolated CSP
(0.200 mm Thick)
Polymer
01005 Sized Polymer Isolated CSP
(0.170 mm Thick)
Silicon Silicon
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Polyimide
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Experimental Results
Mechanical Strength
Reliability
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Load
CSP
Span
Displacement
Load Load
At Breakage
Setup Setup
Cross Section
Force (Load) vs
Displacement
Curve
(Example)
Support Support
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0.0
1.0
2.0
CSP Polymer Isolated-CSP
Bre
akin
g Fo
rce
(K
gf)
27% IncreaseCSP Thickness:
Bare Silicon: 270 um
Polymer Isolated: 200 um
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0
100
200
300
400
500
600
700
800
CSP Polymer Isolated-CSP
σm
ax
at
Bre
akag
e(
Mp
a)
2.4x Increase
𝜎𝑚𝑎𝑥 =3 × 𝐹𝑏𝑟𝑒𝑎𝑘 × 𝐿𝑠𝑝𝑎𝑛
2 × 𝑊 × 𝑇2
Silicon Fracture Stress Increase
• Poly Isolation
• Plasma Etch Silicon Street
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Polymer
Silicon Edge
Silicon Traditional
Mechanical
Dicing Saw
Polymer Isolated
CSP With Plasma
Silicon Etch
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Board Level Test Condition Read Point
Rej/ sample
size
Board Assembly Yield
Mount on Board & Test
Test After
Mount
0/1180
Highly Accelerated Stress Test (HAST)
Temp= +130°C, RH=85%,18.8 psig, biased
96 hr 0/270
Temperature Cycle
T = -65°C to 150°C 1000 cycles
0/270
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Top View
Side View End View
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Black & White X-Ray of CSP after HAST Reliability
CSP
FR4 Board
Copper
Trace Copper
Trace
Solder
(Stencil)
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Silicon
Polymer Isolation
Black White X-RayCSP Device
Copper on PWB
FR4 Board
CopperTrace
Black & White/Color X-Ray of CSP after HAST Reliability
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No Leakage to substrate due to Polymer Isolation on sidewalls
Even if solder extends to the scribe and along the sidewall
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A 5-side polymer 0201/01005 CSP requires the bulk silicon to be thinned down to
maintain the low profile final package thickness.
• Thinner silicon decreases the mechanical strength
• Improve silicon strength with silicon plasma etch instead of mechanical diamond saw
Polymer Isolated 0201/01005 sized CSP key points:
• Polymer Sidewall Isolation eliminates assembly solder shorts to the silicon
• Wafer Level Polymer Process Module integrated into standard CSP Flow
• Carrier provides mechanical support during polymer formation module after the wafer
is thinned to <100um
• Backside Silicon Street Etch suitable for scribe lines that contain test structures and
dummy fill
• 27% better mechanical strength than typical bare silicon CSP (Silicon Plasma Etch
and polymer isolation)
• Industrial Temp Cycle Performance (> 1000 cycles 150C to -65C)
• Polymer Isolation still intact after HAST (96 hr)
• Qualified for Production