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Recent Advances in Electronics and Communication Technologies 4,5 March,2011

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Synthesis of CMOS op-amp

S. S. Chauhan1, S.C. Yadav2, Dr. R.Chandel3 Graphic Era University (E&CE Deptt.)1, 2, NIT Hamirpur (E&CE Deptt)3

[email protected], [email protected],[email protected]

Abstract This talk presents a new method for optimizing and automating component sizing in CMOS analog circuits. It is shown that a wide variety of circuit performance measures have a special form, i.e., they are polynomial functions of the design variable. The approach is based on the observation that the first order behavior of a MOS transistor in the saturation region is such that the cost and the constraint functions for this optimization problem can be modeled as polynomial in the design variables. The problem is then solved efficiently as a convex optimization problem. Second order effects are then handled by formulating the problem as one of solving a sequence of convex programs. Numerical experiments show that the solutions to the sequence of convex programs coverage to the same design point for widely varying initial guesses. Accuracy of performance prediction in the sizing program (implemented in MATLAB) is maintained by using a newly proposed MOS transistor model and verified against detailed SPICE simulation. Index Terms - Device models, optimization, transistor-sizing.

1. INTRODUCTION

The current trend in microelectronics is to integrate a complete system that previously occupied one or more boards on one or a few chips. Although most of the functionality in an integrated system is implemented in digital circuitry, analog circuits are needed to interface between the core digital system and the real world. Analog interface circuits have, thus, become vital and indispensable parts of most digital circuits. They provide the necessary signal conditioning and modification so that they can be processed digitally. Interface circuits span a wide variety of functions and applications such as data acquisition systems, A/D and D/A converters, particle and radiation detection circuits, automotive electronics, biomedical instrumentation and control circuits, robot sensing, industrial process monitoring, implantable biomedical instruments, preamplifiers, compressors, power drivers, etc. Therefore, to realize an integrated system on a single chip, the digital and analog circuits are combined together. Existing approaches of automatic circuit sizing are broadly classified into three main categories, namely knowledge-based optimization, simulation-based optimization, and analytical equation-based optimization. Since analog design requires detailed circuit knowledge, a major approach of implementing an analog synthesis tool has been the knowledge-based approach. However, the application of this approach has been limited due to requirement of having to codify extensive circuit knowledge and design heuristics. Simulation-based optimization approach does not require much circuit knowledge. Hence, the main advantage of this approach is that a wide range of circuits can be synthesized.

However, the basic limitation comes from the requirement of costly circuit simulation in each iteration of the optimization algorithm. To reduce the CPU time of optimization-based techniques, the third approach is analytical equations-based optimization, where, the circuit performances are evaluated using analytical equations.

2. THE BASIC APPROACH The proposed op-amp sizing technique is based on three

basic ideas:-- 1. Extrapolating the saturation region characteristic of a

transistor into its linear region of operation. The use of the extrapolated transistor characteristic results in a design formulation that is simple and robust.

2. To separate the first-order and higher order behavior of the MOS transistor. With the first-order model, it is shown that the constraint functions and the objective function for the design optimization problem are posynomials in the design variables, namely transistor sizes and biases. In other words, with the first-order model, the op-amp synthesis problem is formulated as a geometric programming problem. With a logarithmic transformation, a geometric programming problem becomes a convex optimization problem.

3. The higher order effects are handled by iteratively updating the first-order model parameters using the higher order transistor models, and by solving a sequence of convex programs. The parameter update is based on iteratively refining the dc operating point.

2.1. Transistor Characteristics Usually transistors in an analog circuit are biased in the saturation region where the drain conductance is low, which helps to get high ac performance. Therefore, for analog design

Fig.1 MOS transistor characteristics


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analysis, one can use only the saturation region characteristic. Methodical use of the saturation region characteristic is shown in Fig. 1.

The continuous curves are the actual ID-VDS characteristic curves of a transistor with different VGS. The dotted line divides the whole region of operation into two parts, linear (left) and saturation (right) regions. The dotted line cuts a characteristic curve at a point where VDS is equal to the drain saturation voltage VDSAT. By extrapolating the saturation region characteristic curves into the linear region, as shown by the dashed lines in Fig. 1, a set of artificial characteristic curves are obtained.

These characteristic curves are simple and smooth over the entire region of operation. For analog design analysis, rather than using the actual characteristic curves, these artificial characteristic curves can be used. To ensure that at the final design point the transistors are actually in saturation, it is necessary to satisfy the constraint VDS≥VDSAT for all transistors.

2.2. Shichman-Hodges MOS Model In Shichman-Hodges MOS model a transistor is in saturation region when,

and in this region of operation the drain current is,

The body effect threshold voltage is,

Where, γ is body factor and ΦF is equilibrium electrostatic potential. The channel length modulation λ is equal to λc/L where, λc is proportionality constant. If the S–H model is used for the extrapolated device characteristic curves, over the entire region of operation transconductance gm, drain conductance gd, and effective gate-to-source voltage VGT (=VGS –VT) are, respectively,

Note that, assuming constant, (1+λ VDS) the device model parameters gm, gd and VGT are product of power (PoP) functions of W/L, L and ID. A PoP function is the product of a positive coefficient and various variables that are raised to some power

3. BASIC GEOMETRIC PROGRAMMING

3.1. Monomial and posynomial functions Let x1, x2,……..,xn denote n real positive variables and x = (x1, x2,……..,xn) a vector with components xi. A real valued function f of x, with the form

(1) where c > 0 and ai Є R, is called a monomial function, or

more informally, a monomial (of the variables x1,…….., xn). Constant c is referred as the coefficient of the monomial, the constants (a1,…,an) are referred as the exponents of the

monomial. Any positive constant is a monomial, as is any variable. Monomials are closed under multiplication and division i.e. if f and g are both monomials then so are f*g and f/g. (This includes scaling by any positive constant.) A monomial raised to any power is also a monomial:-

The term `monomial', which is used here (in the context of

geometric programming) is similar to, but differs from the standard definition of `monomial' used in algebra. In algebra, a monomial has the form (1), but the exponents ai must be nonnegative integers, and the coefficient c is one.

A sum of one or more monomials, i.e., a function of the form

where ck > 0, is called a posynomial function or, a

posynomial (with K terms, in the variables x1,…….., xn). The term `posynomial' is meant to suggest a combination of

`positive' and `polynomial'. Any monomial is also a posynomial. Posynomials are closed under addition, multiplication, and positive scaling. Posynomials can be divided by monomials (with the result also a posynomial) i.e. if f is a posynomial and g is a monomial, then f/g is a posynomial. If γ is a nonnegative integer and f is a posynomial, then fγ is a posynomial (since it is the product of γ posynomials). 3.2 Standard form Geometric Program

A geometric program (GP) is an optimization problem of

the form minimize f0(x) subject to fi(x)≤ 1; i = 1,….,m; gi(x) = 1; i = 1,…,p; where fi are posynomial functions, gi is monomials, and xi

is the optimization variables. (There is an implicit constraint that the variables are positive, i.e., xi > 0.) We refer to the problem (3) as a geometric program in standard form. In a standard form GP, the objective must be posynomial (and it must be minimized) the equality constraints can only have the form of a monomial equal to one, and the inequality constraints can only have the form of a posynomial less than or equal to one. We can switch the sign of any of the exponents in any monomial term in the objective or constraint functions, and still have a GP. But if we change the sign of any of the coefficients, or change any of the additions to subtractions, the resulting problem is not a GP.

3.3. Solution Method for GP The main motivation for GP modeling is the great efficiency with which optimization problems of this special form can be solved. The main trick to solving a GP efficiently is to convert it to a nonlinear but convex optimization problem, i.e., a problem with convex objective and inequality constraint functions, and linear equality constraints. The conversion of a GP to a convex problem is based on a logarithmic change of variables, and a logarithmic transformation of the objective


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and constraint functions. In place of the original variables xi, we use their logarithms, yi = log xi (so xi = ey

i ). Instead of minimizing the objective f0, we minimize its logarithm log f0 . We replace the inequality constraints fi≤1 with log fi≤0, and the equality constraints gi = 1 with log gi = 0. This results in the problem minimize log f0 (ey) subject to log fi (ey) 0; i = 1; : : : ; m; (4) log gi (ey)= 0; i = 1; : : : ; p; with variables y = (y1; : : : ; yn). Here we use the notation ey, where y is a vector, to mean component wise exponentiation: (ey)i = e. This transformed version is convex, and so can be solved very efficiently by interior point methods. Interior-point methods are quite reliable. Problems with hundreds of variables and thousands of constraints can be solved on a current desktop computer, in at most a few tens of seconds. By exploiting problem structure (such as sparsity), far larger problems can be solved with many thousands of variables and constraints.

4. DESIGN FORMULATION FOR SIMPLE CMOS OP-

AMP SIZING

4.1. Characterization of Simple CMOS Op-Amps Various steps of op-amp sizing are described here by using

a simple running example, shown in Fig. 2. Consider the design optimization problem as minimize a weighted sum of gate area and power while

In this design problem, Land W/Lof the transistors and the bias current Ib are the design variables. In the op-amp, M1, M2 and M3, M4 are matched pairs.

4.2. DC Analysis

In this step, the circuit is analyzed to determine analytical equations that give its dc operating point. These equations are solved to get the dc operating point, which is then used for predicting its performance.

In a CMOS analog circuit, various node voltages can be defined by the gate-to-source voltages of various transistors. Further, the gate-to-source voltages of the transistors can be determined by its size and its dc current. Finally, the dc current through all the transistors can be essentially determined by only a few transistors, referred as current source transistors.

An exception to this approach is the output node, whose voltage usually cannot be determined from the VGSi’s of various transistors. However, in actual applications, op-amps are used in a closed loop configuration, where the output node voltage is stable at a predetermined value (usually zero).

In the Two Stage OP-AMP shown above, the bias stage current is Ib and the current through the input stage and the second stage are, respectively,

(1) (2)

The gate-to-source voltages of all the transistors are determined by

(3) (4)

Through a casual dc analysis, various node voltages are expressed in terms of VGSi ’s and bias voltages

(5) (6)

(7) The back bias of the transistors in the op-amp in terms of

various node voltages is as follows: ,5 (8)

(9) Finally, drain-to-source voltages of the transistors are

expressed in terms of the node voltages as follows:--

(10)

(11)

(12)

(13) These nonlinear equations are solved through a fixed-point scheme. The overall method of finding node voltages is shown in Fig. 3. In the first step, channel length modulation factor, (1+λ VDSi) and threshold voltage, VT, of various transistors are updated based on the VDSi’s and VSBi’s values in the previous iteration. In the first iteration, (1+λ VDSi)’s assumed to be one and all the VTi’s are taken to be VT0 .

Fig.2 Simple op-amp, example


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Next, the drain current of all current source transistors in the circuit are found. These currents are then used to find the current through the remaining transistors in the circuit. In the next step, VGSi’s are determined from IDi’s, VTi’s, (1+λ VDSi)’s, and Wi/Li ’s of the transistors. In the subsequent step, from the VGSi’s, various node voltages are determined. In the final step, VDSi’s and VSBi’s are evaluated using their equations. The values of the VDSi’s and VSBi’s, which is obtained at the end of each iteration, are then used in the next iteration to get a more accurate estimate of the dc operating point. The terminating condition is that all node voltages in two consecutive iterations are very close. This formulation results in a highly contractive fixed-point scheme that converges very fast. This is because, across the design space, the value of (1+λ VDSi)’s close to one and the back bias dependency function of the threshold voltage is strictly monotonic with small slope.

4.3. Design Space Constraints The design space constraints include the technology limits of the transistor sizes and the constraints on design variables, which help to bias the transistors in saturation. The inequalities that keep the transistors away from the linear region are given by:--

εSUB /VGTi≤1 (14) εSUB =margin to which all transistor away from subthreshold region The inequalities that keep the transistors away from the linear region are given by:-- VD ≥ VG-VTSAT for n type (15) VD ≤ VG-VTSAT for p type (16) Where VTSAT=VGS-VDSAT Consider the example circuit, the gate and drain voltages of transistor M3 and M4 are same. Therefore, these two transistors are always in saturation. However, to keep M1 (and M2) in saturation, we require V1 ≥ Vin1-VTSAT1 . In quiescent condition Vin1=0. Further, from(8), V1=Vdd-VGS3 . Therefore design inequality is VGT3/(Vdd-VT3+VTSAT1)≤1 (17) The transistor M5 is kept in saturation region V3 ≥ V4+VTSAT5 using expression of by V3 and V4 in (6) and (7) we get the inequality (VGT5+VGT1)/(Vdd+Vin1-VT1-VT5+VTSAT5)≤1 (18) Assuming constants VTi’s and VTSATi’s ,(14),(17),and (18) are posynomial functions of VGTi’s ,which are constrained to be less than or equal to one. Finally, to keep the transistor size with in the specified limit, the following inequalities should be satisfied: Wmin/Wi≤1 (19) Wi/Wmax≤1 (20) Lmin/Li≤1 (21) Li/Lmax≤1 (22) 4.4 Performance Constraints and Objective Function The low frequency gain of the opamp is gm1/(gd1+gd3). Therefore, to meet the gain specification Aspec.gd1/gm1+Aspec.gd3/gm1≤1 (23) The unity gain frequency of the opamp is gm1 /C L . So to get the specified UGF UGFspec.CL/gm1≤1 (24) Slew rate of the op-amp is I D5/ C L. So the constraint to get the specified slew rate is SRspec.CL/ID5≤1 (25) The negative common mode range is given by:-- CMR-=-Vdd+VGS0+VGS1-VTSAT5 (26) (VGT0+VGT1)/(Vdd-VT0-VT1+VTSAT5-|CMRSPEC|)≤1 (27) For simple input differential pair, the positive common mode range is:-- CMR+=Vdd-VGS3+VTSAT1 (28) Therefore, to meet its specification, the constraint is:-- VGT3/(Vdd-VT3+VTSAT1-CMR+SPEC)≤1 (29) 4.5 Objective Function

In the optimization formulation, a weighted sum of the total gate area of the transistors and the power dissipation is taken as the objective function to be minimized. The total power dissipation is:--

Fig.3 Iterative approach of finding DC operating point


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PD=2*(Vdd–Vss)*(Ib+ID5) (30) and the total effective gate area is EFFAREA=(Wi/Li)Li2 for i=0,1,2,3,4 (31)

All the performance constraint functions are posynomials in the device parameters VGTi’s, IDi’s, gmi’s, and gdi’s. These device parameters are PoP function of design variables. Therefore, the performance constraint functions are posynomials in the design variables. Further, the power dissipation and the total effective gate area are posynomials of the design variables. As with the design space constraints, the performance constraints are expressed in terms of device parameters, which are in turn functions of the actual design variables.

5. FORMULATION OF OP-AMP DESIGN AS A

SEQUENCE OF CONVEX PROGRAMMING PROBLEMS

Assuming constant VT, (1+λVDS) and VTSAT, the op-amp synthesis problem is formulated as a convex programming problem. Now, to account for the effect of variations in VT, (1+λ VDS) and VTSAT the overall method is shown in Fig. 4. The various steps of the method are as follows:--

1. Accept the designer specifications and the circuit to be sized. The user may provide an initial design point, which is optional. By default, the initial design point is taken as the minimum feature size for all the transistors. Using two iterations of the dc analysis technique described in Fig.3 an approximate dc operating point at the initial design point is found.

2. In this step, the constants and powers of the PoP representation of the various IDi’s are determined. The values of VDSi’s, which are used to determine the constant, come from the previous iteration. Similarly, the constants and powers of the PoP representation of the various gdi ’s, gmi’s, and VGTi ’s are also determined. Using the values of VSBi’s,

which come from the previous iteration, the threshold voltage of the transistors is also evaluated here.

3. From the constants and powers of gdi ’s, gmi’s, VGTi ’s,

IDi’s, and the values of VTi ’s, the objective function and the constraint functions in the transformed design space are derived. Bot

h the objective function and the constraint functions are convex functions. 4. The convex programming problem is then solved to find

the global optimal solution of the current iteration. 5. In this step, the dc operating point is updated for the new

solution design point. The method of finding the dc operating point is the same as shown in Fig.3. The basic difference is that only one pass of the flow graph shown in Fig. 3 is executed. In the single pass, to get the updated values of VGTi ’s, IDi’s and VTi ’s, the values of VDSi’s and VSBi’s are taken from the operating point at the solution point in the previous iteration.

6. In this step, the convergence of the sequence of solution

design points and node voltages are checked. If the design points and the node voltages of the last two iterations are very close, then the op-amp netlist with sized transistors is provided. Otherwise, we go back to step 2.

6. CONCLUSION

The CMOS op-amp sizing technique described has been implemented in MATLAB and SPICE for two stage CMOS op-amp. In the implementation, convex programming problem is solved by using the sequential quadratic programming method which is available in optimization toolbox. Experimental results are given below. Table 1 consists of MATlab and spice simulation results using optimal design point variables against various given specifications.

Perf. unit Spec. Matlab Simulation

Spice Simulation

A(0) 70 60.3 64.6 UGF(MHz) 10 8.135 9.11 CMR(V) -2.5,2.5 -1.33, 4.66 -1.56, 4.33 SR(v/µSec) 10 4.5 6.2 PD(mW) - 1 2.25 Fval - -11.3225 -

TABLE.1 MATlab and Spice simulated performance result

Fig.4 Op-amp sizing method through sequential convex programming


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Table 2 consists of optimal design point, found using optimization toolbox in MATLAB for convex programming. In this table various W of MOS Transistors and bias current have been given (with constant L=0.6 µ)

Variables Values W0,W1,W2,W3,W4,W5 0.99 µ Ib 0.5 µA

An efficient technique for sizing CMOS op-amps is used .The main concept in this approach is that the CMOS op-amp sizing problem can be formulated as a sequence of (convex)geometric programs. Such a formulation has two major advantages as enumerated below:--

1) Since the convex programming problem is very well understood, it is very straight forward to solve it in a robust and computationally efficient manner.

2) The sequence of solutions generated is a sequence of global optimal of convex programming sub problems. It suggests that the point to which this sequence converges is the globally optimal solution of the original problem. This is supported by experimental results, where it is shown that the method converges to the same final design point for widely varying initial design points.

This is achieved by modeling VGT, gm, and gd as a PoP function of the transistor sizes and the bias current at a “relaxed” estimate of the dc operating point. Because of this iterative formulation, as the iterant proceed and approach convergence, the coefficient and powers of the first-order PoP model are made accurate via the use of second order model functions.

Restricting the devices to operate in the saturation region is done because in standard CMOS op-amp design, the mosfets that are used as loads or amplification devices are biased in the saturation region for, among other reasons, the low gd that is achievable in this region. There are specific exceptions to this rule, e.g., when a parallel connection of an NMOS and PMOS device is used to build a resistor, or the common mode feedback transistor in a fully differential two-stage op-amp. SCP (Sequential Convex Programming) approach can be applied to MOS circuits without concerning about the region of operation of the individual devices, or even for bipolar circuits if the iterative model-optimize approach is applied appropriately.

For this it is required that the derived device parameters, e.g., gm and gd , be modeled as PoP functions of the independent design variables and that these PoP models become accurate approximations of the original device models as the iterant converge.

There are certain performance metrics like settling time, which cannot be modeled as a suitable analytic function. While it is possible to meet a given settling time specification by suitably constraining slew rate, unity gain frequency, and phase margin (which are modeled as posynomials).

Effort required to derive analytic expressions of performance metrics (for a new op-amp) is a hindrance to the widespread use of techniques such as described here but this

hurdle should be crossed in order to bring the major advantages of convex optimization into a truly automated circuit-sizing tool.

REFERENCES [1] P.Mandal and V.Visvanathan, “A new approach for

CMOS op-amp synthesis,” in Proc. 12th Int. Conf. VLSI Design, 1999, pp. 189–194.F.

[2] P.Mandal and V.Visvanathan,” CMOS Op-Amp Sizing Using a Geometric Programming Formulation,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, Vol. 20, No. 1, January 2001.

[3] S. P. Boyd, Seung Jean Kim, Lieven Vandenberghe and Arash Hassibi “A Tutorial on Geometric Programming”

[4] C. Taumazou and C. A. Markis, “Analog IC design automation: Part I—Automated circuit generation: New concept and methods,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 218–238, Feb. 1995.

[5] A. Grace, “Optimization Toolbox User’s Guide,” The Math Works Inc., Nov. 1992.

[6] M. M. Hershenson, S. P. Boyd, and T. H. Lee, “GPCAD: A tool for CMOS op-amp synthesis,” in Proc. Int. Conf. Computer-Aided Design, 1998, pp. 296–303.

[7] G.W. Roberts & A. S. Sedra,” SPICE second edition,” Oxford University Press, 1959.

[8] B. Razavi,” Design of Analog CMOS Integrated Circuits “, TMH, 2002.

TABLE.2 Optimal design point for simple op-amp

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