vs8100 som reference manual - apcvesti2c inter-integrated circuit ic integrated circuit jtag joint...

VEST-VS8100-USG-001, REV A

APC Proprietary Information March 29, 2016

VS8100 SOM Reference Manual

VEST-VS8100-USG-001

Copyright © 2016 Advanced Products Corporation Pte Ltd. All rights reserved. No part of this document may be photocopied, reproduced, or translated to another language without the prior written permission of Advanced Products Corporation Pte Ltd.



TABLE OF CONTENTS 1 Overview ....................................................................................................................................... 7

1.1 Introduction ....................................................................................................................................... 7 1.2 Feature Summary .............................................................................................................................. 7 1.3 Block Diagram .................................................................................................................................... 8 1.4 List of Acronyms ................................................................................................................................ 9 1.5 Reference Documents ..................................................................................................................... 10

2 Main Hardware Components ........................................................................................................11

2.1 NXP i.MX 6Dual/6Quad ................................................................................................................... 11 2.1.1 Overview .................................................................................................................................. 11 2.1.2 i.MX6 System Block Diagram ................................................................................................... 11 2.1.3 Features ................................................................................................................................... 12

2.2 10/100/1000 MB Ethernet Transceiver ........................................................................................... 14 2.2.1 Overview .................................................................................................................................. 14 2.2.2 AR8031 Block Diagram ............................................................................................................ 14 2.2.3 AR8031 Features ...................................................................................................................... 14

2.3 Memory ........................................................................................................................................... 15 2.3.1 DDR3 SDRAM ........................................................................................................................... 15 2.3.2 eMMC Flash Memory .............................................................................................................. 15

2.4 PMIC ................................................................................................................................................ 15

3 External Interface .........................................................................................................................16

4 Signal Description Per Block/Instance ............................................................................................31

4.1 Asynchronous Sample Rate Converter (ASRC) ................................................................................ 31 4.2 Digital Audio Mux (AUDMUX) ......................................................................................................... 31 4.3 Clock Controller Module (CCM) ....................................................................................................... 32 4.4 Display Content Integrity Checker (DCIC) ........................................................................................ 33 4.5 Enhanced Configurable SPI (ECSPI) ................................................................................................. 34 4.6 Enhanced Periodic Interrupt Timer (Epit) ....................................................................................... 36 4.7 Enhanced Serial Audio Interface (ESAI) ........................................................................................... 37 4.8 Flexible Controller Area Network (FLEXCAN) .................................................................................. 38 4.9 General Purpose Input/Output (GPIO) ............................................................................................ 39 4.10 General Purpose Timer (GPT) .......................................................................................................... 44 4.11 HDMI ................................................................................................................................................ 45 4.12 I2C .................................................................................................................................................... 46 4.13 Image Processing Unit (IPU) ............................................................................................................ 47 4.14 Keypad Port (KPP) ............................................................................................................................ 49 4.15 LVDS Display Bridge (LDB) ............................................................................................................... 51 4.16 MIPI- Camera Serial Interface Host Controller (MIPI_CSI) .............................................................. 51 4.17 MIPI Display Serial Interface Host Controller (MIPI_DSI) ................................................................ 52 4.18 PCI Express (PCIe) ............................................................................................................................ 52 4.19 Pulse Width Modulation (PWM) ..................................................................................................... 53 4.20 Serial Advanced Technology Attachment PHY (SATA PHY) ............................................................. 53



4.21 System JTAG Controller (SJC)........................................................................................................... 54 4.22 SONY/PHILIPS Digital Interface (SPDIF) ........................................................................................... 55 4.23 Universal Asynchronous Receiver/Transmitter (UART) .................................................................. 55 4.24 Universal Serial Bus Controller (USB) .............................................................................................. 58 4.25 Ultra Secured Digital Host Controller (uSDHC) ................................................................................ 59 4.26 Watchdog Timer (WDOG)................................................................................................................ 61 4.27 Crystal Oscillator (XTALOSC) ............................................................................................................ 61 4.28 10/100/1000-Mbps Ethernet (ENET)............................................................................................... 62

5 ELECTRICAL SPECIFICATION ...........................................................................................................64

5.1 Absolute Maximum Characteristics................................................................................................. 64 5.2 Operational Characteristics ............................................................................................................. 64

5.2.1 Power Supplies ......................................................................................................................... 64 5.2.2 Power Consumption ................................................................................................................. 64

6 ENVIRONMENTAL SPECIFICATION .................................................................................................66

6.1 Temperature Specification .............................................................................................................. 66 6.2 Humidity .......................................................................................................................................... 66

7 MECHANICAL SPECIFICATION ........................................................................................................67

7.1 Module Dimension .......................................................................................................................... 67 7.2 Height on Top .................................................................................................................................. 67 7.3 Height on Bottom ............................................................................................................................ 67 7.4 Mechanical Dimension .................................................................................................................... 68

8 BOARD OPTIONS ...........................................................................................................................69

9 Revision History ............................................................................................................................70

10 Legal Notices .............................................................................................................................71



LIST OF TABLES Table 1-1: List Of Acronyms ............................................................................................................................. 10 Table 3-1: 204-pin SO-DIMM Pin Assignment ................................................................................................. 30 Table 4-1: External Signals Of ASRC ................................................................................................................. 31 Table 4-2: External Signals Of AUDMUX .......................................................................................................... 32 Table 4-3: External Signals Of CCM ................................................................................................................. 33 Table 4-4: External Signals Of DCIC ................................................................................................................. 34 Table 4-5: External Signals Of ECSPI 1 ............................................................................................................. 35 Table 4-6: External Signals Of ECSPI 2 ............................................................................................................. 35 Table 4-7: External Signals Of ECSPI 4 ............................................................................................................. 36 Table 4-8: External Signals Of ECSPI 5 ............................................................................................................. 36 Table 4-9: External Signals Of EPIT .................................................................................................................. 36 Table 4-10: External Signals Of ESAI ................................................................................................................ 38 Table 4-11: External Signals Of FLEXCAN ........................................................................................................ 39 Table 4-12: External Signals Of GPIO1 ............................................................................................................. 40 Table 4-13: External Signals Of GPIO2 ............................................................................................................. 41 Table 4-14: External Signals Of GPIO3 ............................................................................................................. 42 Table 4-15: External Signals Of GPIO4 ............................................................................................................. 42 Table 4-16: External Signals Of GPIO5 ............................................................................................................. 43 Table 4-17: External Signals Of GPIO6 ............................................................................................................. 44 Table 4-18: External Signals Of GPIO7 ............................................................................................................. 44 Table 4-19: External Signals Of GPT ................................................................................................................ 45 Table 4-20: External Signals Of HDMI .............................................................................................................. 46 Table 4-21: External Signals Of I2C 1 ............................................................................................................... 46 Table 4-22: External Signals Of I2C 2 ............................................................................................................... 47 Table 4-23: External Signals Of I2C 3 ............................................................................................................... 47 Table 4-24: External Signals Of IPU1 ............................................................................................................... 48 Table 4-25: External Signals Of IPU2 ............................................................................................................... 49 Table 4-26: External Signals Of KPP ................................................................................................................. 50 Table 4-27: External Signals Of LDB ................................................................................................................. 51 Table 4-28: External Signals Of MIPI_CSI......................................................................................................... 52 Table 4-29: External Signals Of MIPI_DSI ........................................................................................................ 52 Table 4-30: External Signals Of PCIe ................................................................................................................ 53 Table 4-31: External Signals Of PWM .............................................................................................................. 53 Table 4-32: External Signals Of SATA PHY ....................................................................................................... 54 Table 4-33: External Signals Of SJC .................................................................................................................. 55 Table 4-34: External Signals Of SPDIF .............................................................................................................. 55 Table 4-35: External Signals Of UART1 ............................................................................................................ 56 Table 4-36: External Signals Of UART2 ............................................................................................................ 57 Table 4-37: External Signals Of UART3 ............................................................................................................ 57 Table 4-38: External Signals Of UART4 ............................................................................................................ 57 Table 4-39: External Signals Of UART5 ............................................................................................................ 58 Table 4-40: External Signals Of USB ................................................................................................................ 59 Table 4-41: External Signals Of uSDHC2 .......................................................................................................... 60 Table 4-42: External Signals Of uSDHC3 .......................................................................................................... 61



Table 4-43: External Signals Of WDOG ............................................................................................................ 61 Table 4-44: External Signals Of XTALOSC ........................................................................................................ 62 Table 4-45: External Signals Of ENET ............................................................................................................... 62 Table 4-46: LED Status ..................................................................................................................................... 63 Table 5-1: Absolute Maximum Characteristics ................................................................................................ 64 Table 5-2: Power Supply Requirement ............................................................................................................ 64 Table 5-3: Power Consumption ....................................................................................................................... 64 Table 8-1: VS8100 SOM Ordering Part Numbers ............................................................................................ 69



LIST OF FIGURES/DIAGRAMS Figure 1-1: VS8100 SOM Board Block Diagram ................................................................................................. 8 Figure 2-1: i.MX6 System Block Diagram ......................................................................................................... 11 Figure 2-2: AR8031 Functional Block Diagram ................................................................................................ 14 Figure 7-1: Top View ........................................................................................................................................ 68 Figure 7-2: Bottom View .................................................................................................................................. 68



1 OVERVIEW

1.1 INTRODUCTION This hardware reference manual is written for the VEST VS8100 family of SOM (System-On-Module) based on the NXP’s i.MX6 ARM® Cortex™-A9 architecture processors. The SOM provides an ideal building block that easily integrates with a wide range of target markets requiring rich multimedia functionality, powerful graphics and video capabilities, as well as high-processing, compact, cost effective and with low power consumption.

The VS8100 SOM is tested to work in the following operating system environment:

Android

Embedded Linux

1.2 FEATURE SUMMARY • NXP i.MX6 processors (Dual/Quad ARM Cortex-A9 Core, 1.0 GHz/Core)

• 1 GB DDR3 SDRAM (Expandable to 4GB)

• 4 GB eMMC Flash for storage memory/boot (Expandable to 64GB)

• On-board 10/100/1000 Mbps Ethernet PHY

• 3.3V Input power supply

• 68mm x 61mmform factor

• 204 pin SO-DIMM Interface

• PCIe V2.0

• SATA II, 3.0Gbps

• USB 2.0 OTG (up to 480Mbps), with integrated HS USB PHY

• USB 2.0 Host(480Mbps)

• LVDS Serial Ports

• HDMI 1.4 Port

• AC97/I2S/SSI, up to 1.4Mbps

• MMC/SD/SDIO

• I2C

• eCSPI

• UART

• CAN

• PWM



• CSI

• GPIO

• JTAG

• Gigabit Ethernet through On-SOM Gigabit Ethernet PHY

1.3 BLOCK DIAGRAM

Figure 1-1: VS8100 SOM Board Block Diagram



1.4 LIST OF ACRONYMS

Acronyms Abbreviations

ARM Advanced RISC Machine

CAN Controller Area Network

CPU Central Processing Unit

CSI Camera Serial Interface

DDR3 Double Data Rate 3

DSI Display Serial Interface

eCSPI Enhanced Configurable Serial Peripheral Interface

eMMC Enhanced Multi Media Card

ESAI Enhanced Serial Audio Interface

GB Giga Byte

Gbps Gigabits per second

GPIO General Purpose Input Output

HDMI High-Definition Multi-media Interface

I2C Inter-Integrated Circuit

IC Integrated Circuit

JTAG Joint Test Action Group

LCD Liquid Crystal Display

LVDS Low Voltage Differential Signal

MB Mega Byte

Mbps Megabits per second

MHz Mega Hertz

MIPI Mobile Industry CPU Interface

MLB Media Local Bus

MMC Multi-Media Card

PWM Pulse Width Modulation

RGMII Reduced Gigabit Media Independent Interface

ROM Read-Only Memory

SATA Serial Advanced Technology Attachment

SD Secure Digital

SDIO Abbreviation

SDRAM Synchronous Dynamic Random Access Memory

SGMII Serial Reduced Gigabit Media Independent Interface

SJC System JTAG Controller

SOM System On Module

SPDIF Sony/Philips Digital Interconnect Format

SPI Serial Peripheral Interface

SSI Synchronous Serial Interface

TMDS Transition Minimized Differential Signalling

UART Universal Asynchronous Receiver/Transmitter



Acronyms Abbreviations

USB Universal Serial Port

USBOTG Universal Serial Port on the Go

VEST Venture Embedded Solutions Technology

APC Advanced Products Corporation Private Limited

ISO International Organization for Standardization

Table 1-1: List Of Acronyms

1.5 REFERENCE DOCUMENTS

i.MX 6Solo/6DuaLite Automotive and Infotainment Applications Processors Technical Data (Document Number: IMX6SDLAEC)

i.MX 6Solo/6DuaLite Applications Processor Reference Manual (Document Number: IMX6SDLRM)

Common Hardware Design for i.MX 6Dual/6Quad and i.MX 6Solo/6DualLite (Document Number: AN4397)



2 MAIN HARDWARE COMPONENTS

This section summarizes the main hardware building blocks of the VS8100 SOM.

2.1 NXP I.MX 6DUAL/6QUAD

2.1.1 Overview The NXP i.MX6 processors are integrated multimedia applications processors optimized for low power consumption. The simplified system block diagram of the i.MX6 is shown below.

2.1.2 i.MX6 System Block Diagram

Figure 2-1: i.MX6 System Block Diagram

Note: Please refer the latest i.MX6 datasheet from NXP website for detail



2.1.3 Features The NXP i.MX6 Application Processors are based on the ARM Cortex-A9 MPCoreTM platform, which has the following features:

ARM Cortex-A9 MPCore 4xCPU Processor (with TrustZone)

The core configuration is symmetric, where each core includes:

- 32 KByte L1 Instruction Cache

- 32 KByte L1 Data Cache

- Private Timer and Watchdog

- Cortex-A9 NEON MPE (Media Processing Engine) Co-processor

The ARM Cortex-A9MPCore complex includes:

- General Interrupt Controller (GIC) with 128 interrupt support

- Global Timer

- Snoop Control Unit (SCU)

- 1 MB unified L2 cache shared by two/four cores

- Two Master AXI (64-bit) bus interfaces output of L2 cache

NEON MPE coprocessor

- SIMD Media Processing Architecture

- NEON register file with 32x64-bit general-purpose registers

- NEON Integer execute pipeline (ALU, Shift, MAC)

- NEON dual, single-precision floating point execute pipeline (FADD, FMUL)

- NEON load/store and permute pipeline External

On-Chip Memory:

- Boot ROM, including HAB (96 KB)

- Internal multimedia / shared, fast access RAM (OCRAM, 256 KB)

- Secure/non-secure RAM (16 KB)

External memory interfaces:

- 16-bit, 32-bit, and 64-bit DDR3-1066, LV-DDR3-1066, and 1/2 LPDDR2-1066 channels, supporting DDR interleaving mode, for 2x32 LPDDR2-1066

- 8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size

- BA-NAND, PBA-NAND, LBA-NAND OneNAND and others BCH ECC up to 40 bit



- 16-bit NOR Flash. All WEIMv2 pins are muxed on other interfaces.

- 16-bit PSRAM, Cellular RAM

Hard disk drives – SATA II, 3.0Gbps

Display

- LVDS serial ports

- HDMI 1.4 port

Camera sensors:

- Parallel camera port (up to 20 bit and up to 240 MHz peak)

MMC/SD/SDIO cards

USB

- One high speed(HS) USB 2.0 OTG (up to 480Mbos), with integrated HS USB PHY

- Three USB 2.0 (480Mbps) hosts

Expansion PCI Express port(PCIe) V2.0

Three I2S/SSI/AC97, up to 1.4Mbps each

Enhanced Serial Audio Interface(ESAI), up to 1.4Mbps per channel

Five UARTs, up to 4.0Mbps each

Five eCSPI, (Enhanced CSPI)

Three I2C, supporting 400kbps

Gigabit Ethernet Controller, 10/100/1000 Mbps

Four Pulse Width Modulators(PWM)

System JTAG Controller(SJC)

GPIO with interrupt capabilities

Two Controller Area Network (FlexCAN),1Mbps each

Two Watchdog timers(WDOG)

Note: Please refer the latest i.MX6 datasheet from NXP website for detail



2.2 10/100/1000 MB ETHERNET TRANSCEIVER

2.2.1 Overview The VS8100 SOM features the Atheros AR8031 Gigabit Ethernet PHY. The AR8031 is Atheros’s 4th generation, single port, 10/100/1000 Mbps, Tri-speed Ethernet PHY. It supports both RGMII and SGMII interface to the MAC.

2.2.2 AR8031 Block Diagram

Figure 2-2: AR8031 Functional Block Diagram

2.2.3 AR8031 Features The AR8031 supports both 1588v2 and synchronous Ethernet to offer a complete time synchronization solution to meet the next generation network requirements. The key new features supported by the device are:

10/100/1000 BASE-T IEEE 802.3 compliant

Supports 1000 BASE-T PCS and auto-negotiation with next page support

Supports RGMII and / or SGMII interfaces to MAC devices

Supports Fiber and Copper combo mode when MAC interface works in RGMII mode

Supports additional IEEE 1000 BASE-X and 100 BASE-FX with Integrated SerDes

RGMII timing modes support internal delay and external delay on Rx path



Supports IEEE802.3az (Energy Efficient Ethernet)

Supports Wake-on LAN (WoL) to detect magic packet and notify the sleeping system to wake up

Automatic channel swap (ACS)

Automatic MDI/MDIX crossover

2.3 MEMORY

2.3.1 DDR3 SDRAM The VS8100 SOM uses four DDR3 SDRAM ICs to support a total 1GB (expandable to 4GB) on board SDRAM memory. A pair of DDR3 IC is physically located on either side of the SOM. These SDRAM operated at 1.5V voltage level. The SDRAM calibration resistor used on SOM is 240ohm 1 % resistor.

Please see Section 8 for various memory options.

2.3.2 eMMC Flash Memory The VS8100 SOM is available with up to 64GB of eMMC flash memory. The eMMC flash is used for Flash Disk purposes, O.S. run- time-image and the Boot-loader.

eMMC is directly connected to i.MX6 SDHC 4 and operating under 3.3V voltage level. The eMMC flash memory is physically located on the top of the SOM.

Please see Section 8 for various eMMC Flash options.

2.4 PMIC The VS8100 SOM features NXP PMPF0100 as a Power Management Integrated circuit. PMIC designed specifically for use with NXP’s i.MX series of application processors. The PMPF0100 regulates all power rails required on SOM from a single 3.3 V power supply. The PMIC is fully programmable via the I2C interface and associated register map. Additional communication is provided by direct logic interfacing including interrupt, watchdog and reset.



3 EXTERNAL INTERFACE

The VS8100 SOM employs a 204-pin SO-DIMM form factor interface. The recommended mating connector for baseboard interfacing is Lotes AAA-DDR-109-K01 or equivalent.

Pin No.

Pin Name iMX6 pad name Signal Signal Type Voltage Level

Description

1 JTAG_MOD JTAG_MOD JTAG_MOD Input(PU100K) 3.3V SJC mode selection

2 BT_Pin3 EIM_DA6 SRC_BOOT_CFG06 Input 3.3V Boot configuration signal to select boot from eMMC

3 JTAG_nTRST JTAG_TRSTB JTAG_TRSTB Input(PU47K) 3.3V Test reset

4 BT_Pin1 EIM_DA4 SRC_BOOT_CFG04 Input 3.3V Boot configuration signal to select boot from serial ROM

5 JTAG_TDO JTAG_TDO JTAG_TDO Output 3.3V Test data output

6 SD2_DATA7 NANDF_D7 NAND_DATA07 SD2_DATA7 GPIO_IO07

3.3V Muxing

7 JTAG_TDI JTAG_TDI JTAG_TDI Input(PU47K) 3.3V Test data input


3.3V Muxing

9 JTAG_TMS JTAG_TMS JTAG_TMS Input(PU47K) 3.3V Test mode select


3.3V Muxing

11 JTAG_TCK JTAG_TCK JTAG_TCK Input(PU47K) 3.3V Test clock

12 SD2_DATA4 NANDF_D4 NANDF_DATA04 SD2_DATA4 GPIO2_IO04

3.3V Muxing

13 SATA_TXP SATA_TXP SATA_PHY_TX_P Differential 2.5V SATA transmit output differential positive

14 SD2_DATA3 SD2_DAT3 SD2_DATA3 ECSPI5_SS3 KEY_COL6 AUD4_TXC GPIO1_IO12

1.8V Muxing

15 SATA_TXN SATA_TXM SATA_PHY_TX_N Differential 2.5V SATA transmit output differential negative

16 SD2_DATA2 SD2_DAT2 SD2_DATA2 ECSPI5_SS1 EIM_CS3_B AUD4_TXD KEY_ROW6 GPIO1_IO13

1.8V Muxing



Pin No.


Description

17 SATA_RXN SATA_RXM SATA_PHY_RX_N Differential 2.5V SATA receive input differential negative

18 SD2_DATA1 SD2_DAT1 SD2_DATA1 ECSPI05_SS0 EIM_CS2_B AUD4_TXFS KEY_COL7 GPIO_IO14

1.8V

19 SATA_RXP SATA_RXP SATA_PHY_RX_P Differential 2.5V SATA receive input differential positive

20 SD2_DATA0 SD2_DAT0 SD2_DATA0 ECSPI5_MISO AUD4_RXD KEY_ROW7 GPIO_IO15 DCIC2_OUT

1.8V Muxing

21 USB_HOST_DN USB_H1_DN USB_H1_DN Differential USB Host data negative

22 SD2_CLK SD2_CLK SD2_CLK ECSPI5_SCLK KEY_COL5 AUD4_RXFS GPIO1_IO10

1.8V Muxing

23 USB_HOST_DP USB_H1_DP USB_H1_DP Differential USB host data positive

24 SD2_CMD SD2_CMD SD2_CMD ECSPI5_MOSI KEY_ROW5 AUD4_RXC GPIO1_IO11

1.8V Muxing

25 USB_OTG_ID ENET_RX_ER USB_OTG_ID ENET_RX_ER ESAI_RX_HF_CLK SPDIF_IN ENET_1588_EVENT2_ OUT GPIO1_IO24

3.3V Muxing

26 SD2_WP NANDF_D3 NANDF_DATA03 SD1_DATA7 GPIO2_IO03

3.3V Muxing

27 USB_OTG_DP USB_OTG_DP USB_OTG_DP Differential USB OTG data positive

28 SD2_CD_B NANDF_D2 NANDF_DATA02 SD1_DATA6 GPIO2_IO02

3.3V Muxing

29 USB_OTG_DN USB_OTG_DN USB_OTG_DN Differential USB OTG data negative

30 HDMI_D2P HDMI_D2P HDMI_TX_DATA2_P Differential 2.5V HDMI differential data2 positive

31 USB_OTG_PWR_EN EIM_D22 EIM_DATA22 ECSPI4_MISO IPU1_DI0_PIN01 IPU2_CSI1_DATA10 USB_OTG_PWR GPIO3_IO22 SPDIF_OUT

3.3V Muxing



Pin No.


Description

32 HDMI_D2M HDMI_D2M HDMI_TX_DATA2_N Differential 2.5V HDMI differential data2 negative

33 USB_H1_PWR_ EN ENET_TXD1 MLB_CLK ENET_TX_DATA1 ESAI_TX2_RX3 ENET_1588_EVENT0_ IN GPUO1_IO29

3.3V Muxing


35 USB_OTG_VBUS USB_OTG_VBUS USB_OTG_VBUS Power 4.5 to 5.25V

USB VBUS


37 USB_H1_VBUS USB_H1_VBUS USB_H1_VBUS Power 4.5 to 5.25V

USB VBUS


39 SD3_DATA3 SD3_DAT3 SD3_DATA3 UART3_CTS_B GPIO7_IO07

3.3V Muxing


41 SD3_DATA2 SD3_DAT2 SD3_DATA2 GPIO7_IO06

3.3V Muxing

42 HDMI_CLKP HDMI_CLKP HDMI_TX_CLK_P Differential 2.5V HDMI differential clock positive

43 SD3_DATA1 SD3_DAT1 SD3_DATA1 UART1_RTS_B FLEXCAN2_RX GPIO7_IO05

3.3V Muxing

44 HDMI_CLKM HDMI_CLKM HDMI_TX_CLK_N Differential 2.5V HDMI differential clock negative

45 SD3_DATA0 SD3_DAT0 SD3_DATA0 UART1_CTS_B FLEXCAN2_TX GPIO7_IO04

3.3V Muxing

46 HDMI_HPD HDMI_HPD HDMI_TX_HPD 2.5V HDMI hot plug detect

47 SD3_CLK SD3_CLK SD3_CLK UART2_RTS_B FLEXCAN1_RX GPIO7_IO03

3.3V Muxing

48 DISP_RST_B NANDF_CS0 NAND_CE0_B GPIO6_IO11

3.3V Muxing

49 SD3_CMD SD3_CMD SD3_CMD UART2_CTS_B FLEXCAN1_TX GPIO7_IO02

3.3V Muxing



Pin No.


Description

50 UART2_CTS EIM_D29 EIM_DATA29 IPU1_DI1_PIN15 ECSPI14_SS0 UART2_RTS_B GPIO3_IO29 IPU2_CSI1_VSYNC IPU1_DI0_PIN14

3.3V Muxing

51 KEY_VOL_DN GPIO_5 ESAI_TX2_RX3 KEY_ROW7 CCM_CLKO1 GPIO1_IO05 I2C3_SCL ARM_EVENTI

3.3V Muxing

52 UART2_RTS EIM_D28 EIM_DATA28 I2C1_SDA ECSPI4_MOSI IPU2_CSI1_DATA12 UART2_CTS_B GPIO3_IO28 IPU1_EXT_TRIG IPU1_DI0_PIN13

3.3V Muxing

53 KEY_VOL_UP GPIO_4 ESAI_TX_HF_CLK KEY_COL7 GPIO1_IO04 SD2_CD_B

3.3V Muxing

54 UART2_RXD EIM_D27 EIM_DATA27 IPU1_DI1_PIN13 IPU1_CSI0_DATA00 IPU2_CSI1_DATA13 UART2_RX_DATA GPIO3_IO27 IPU1_SISG3 IPU1_DISP1_DATA23

3.3V Muxing

55 POR_B POR_B SRC_POR_B Input(PU100K) 3.0V Power on Reset

56 UART2_TXD EIM_D26 EIM_DATA26 IPU1_DI1_PIN11 IPU1_CSI0_DATA01 IPU2_CSI1_DATA14 UART2_TX_DATA GPIO3_IO26 IPU1_SISG2 IPU1_DISP1_DATA22

3.3V Muxing

57 UART1_CTS EIM_D19 EIM_DATA19 ECSPI1_SS1 IPU1_DI0_PIN08 IPU2_CSI1_DATA16 UART1_CTS_B GPIO3_IO19 EPIT1_OUT

3.3V Muxing

58 UART3_RXD EIM_D25 EIM_DATA25 ECSPI4_SS3 UART3_RX_DATA ECSPI1_SS3 ECSPI2_SS3 GPIO3_IO25 AUD5_RXC UART1_DSR_B

3.3V Muxing



Pin No.


Description

59 UART1_RTS EIM_D20 EIM_DATA20 ECSPI4_SS0 IPU1_DI0_PIN16 IPU2_CSI1_DATA15 UART1_RTS_B GPIO3_IO20 EPIT2_OUT

3.3V Muxing

60 UART3_TXD EIM_D24 EIM_DATA24 ECSPI4_SS2 UART3_TX_DATA ECSPI1_SS2 ECSPI2_SS2 GPUO3_IO24 AUD5_RXFS UART1_DTR_B

3.3V Muxing

61 UART1_RXD SD3_DAT6 SD3_DATA6 UART1_RX_DATA GPIO6_IO18

3.3V Muxing

62 UART3_RTS EIM_D23 EIM_DATA23 IPU1_DI0_D0_CS UART3_CTS_B UART1_DCD_B IPU2_CSI1_DATA_EN GPIO3_IO23 IPU1_DI1_PIN02 IPU1_DI1_PIN14

3.3V Muxing

63 UART1_TXD SD3_DAT7 SD3_DATA7 UART1_TX_DATA GPIO6_IO17

3.3V Muxing

64 UART3_CTS EIM_EB3 EIM_EB3_B ECSPI4_RDY UART3_RTS_B UART1_RI_B IPU2_CSI1_HSYNC GPIO2_IO31 IPU1_DI1_PIN03 SRC_BOOT_CFG31

3.3V Muxing

65 SOM_3V3 Power Power 3.3V 3.3V Input






71 GND GND Ground 0V GND


73 TXRXN_D From AR8031_TXRX N3

Differential Media- dependent interface 3, differential 100ohm transmission line



Pin No.


Description

74 LVDS0_CLK_P LVDS0_CLK_P LVDS0_CLK_P Differential 2.5V LVDS differential clock positive

75 TXRXP_D From AR8031_TXRX P3


76 LVDS0_CLK_N LVDS0_CLK_N LVDS0_CLK_N Differential 2.5V LVDS differential clock negative

77 TXRXN_C From AR8031_TXRX N2


78 LVDS0_TX3_P LVDS0_TX3_P LVDS0_DATA3_P Differential 2.5V LVDS differential pair3 positive

79 TXRXP_C From AR8031_TXRX P2


80 LVDS0_TX3_N LVDS0_TX3_N LVDS0_DATA3_N Differential 2.5V LVDS differential pair3 negative

81 TXRXN_B From AR8031_TXRX P2



83 TXRXP_B From AR8031_TXRX P2



85 TXRXN_A From AR8031_TXRX P2





Pin No.


Description

87 TXRXP_A From AR8031_TXRX P2



89 RGMII_LED_AC T From AR8031_TXRX P2

Parallel LED output for 10/100/1000 BASE-T activity; active high.

90 LVDS0_TX0_P LVDS0_TX0_P LVDS0_DATA0_P Differential 2.5V LVDS differential0 positive

91 RGMII_LED_10 00

From AR8031_TXRX P2

Parallel LED output for 1000 BASE-T link, active high.


93 RGMII_LED_10 _100

From AR8031_TXRX P2

Parallel LED output for 10/100 BASE-T link, active high.

94 DISP0_CONTRA ST Connect to SD1_DAT3 through level shift NLSV1T34

PWM1_OUT Output 3.3V Backlight PWM

95 I2C1_SCL CSI0_DAT9 IPU1_CSI0_DATA09 EIM_DATA07 ECSPI2_MOSI KEY_ROW7 I2C1_SCL GPIO5_IO27 ARM_TRACE06

1.8V Muxing

96 SD3_WP NANDF_D1 NAND_DATA01 SD1_DATA5 GPIO2_IO01

3.3V Muxing

97 I2C1_SDA CSI0_DAT8 IPU1_CSI0_DATA08 EIM_DATA06 ECSPI2_SCLK KEY_COL7 I2C1_SDA GPIO5_IO26 ARM_TRACE05

1.8V Muxing

98 SD3_CD_B NANDF_D0 NAND_DATA00 SD1_DATA4 GPIO2_IO00

3.3V Muxing

99 PCIE_TXP PCIE_TXP PCIE_TX_P 2.5V PCIe differential transmit positive

100 LED_PWR NANDF_ALE NAND_ALE SD4_RESET GPIO6_IO08

3.3V Muxing

101 PCIE_TXM PCIE_TXM PCIE_TX_N 2.5V PCIe differential transmit negative



Pin No.


Description

102 LED_EN NANDF_CS2 NAND_CE2_B IPU1_SISG0 ESAI_TX0 EIM_CRE CCM_CLKO2 GPIO6_IO15 IPU2_SISG0

3.3V Muxing

103 PCIE_RXP PCIE_RXP PCIE_RX_P 2.5V PCIe differential receive positive

104 LCD_PWR GPIO_16 ESAI_TX3_RX2 ENET_1588_EVENT2_ IN ENET_REF_CLK SD1_LCTL SPDIF_IN GPIO7_IO11 I2C3_SDA JTAG_DE_B

3.3V Muxing

105 PCIE_RXM PCIE_RXM PCIE_RX_N 2.5V PCIe differential receive negative

106 I2C3_SDA GPIO_6 ESAI_TX_CLK I2C3_SDA GPIO1_IO06 SD2_LCTL MLB_SIG

3.3V Muxing

107 PCIE_WAKE_B SD3_DAT4 SD3_DATA4 UART2_RX_DATA GPIO7_IO01

3.3V Muxing

108 I2C3_SCL GPIO_3 ESAI_RX_HF_CLK I2C3_SCL XTALOSC_REF_CLK_2 4M CCM_CLKO2 GPIO1_IO03 USB_H1_OC MLB_CLK

3.3V Muxing

109 Touch_INT EIM_WAIT EIM_WAIT_B EIM_DTACK_B GPIO5_IO00 SRC_BOOT_CFG25

3.3V Muxing

110 EIM_OE EIM_OE EIM_OE_B IPU1_DI1_PIN07 ECSPI2_MISO GPIO2_IO25

3.3V Muxing

111 AUD3_RXD CSI0_DAT7 IPU1_CSI0_DATA07 EIM_DATA05 ECSPI1_SS0 KEY_ROW6 AUD3_RXD GPIO5_IO25 ARM_TRACE04

1.8V Muxing

112 DISP_PWR_EN NANDF_CS1 NAND_CE1_B SD4_VSELECT SD3_VSELECT GPIO6_IO14

3.3V Muxing

113 AUD3_TXFS CSI0_DAT6 IPU1_CSI0_DATA06 EIM_DATA04 ECSPI1_MISO KEY_COL6 AUD3_TXFS GPIO5_IO24 ARM_TRACE03

1.8V Muxing

114 SD3_DATA5 SD3_DAT5 SD3_DATA5 UART2_TX_DATA GPIO7_IO00

3.3V Muxing



Pin No.


Description

115 AUD3_TXD CSI0_DAT5 IPU1_CSI0_DATA05 EIM_DATA03 ECSPI1_MOSI KEY_ROW5 AUD3_TXD GPIO5_IO23 ARM_TRACE02

1.8V Muxing

116 DSI_D1P DSI_D1P DSI_DATA1_P 2.5V MIPI DSI differential data1 positive

117 AUD3_TXC CSI0_DAT4 IPU_CSI0_DATA04 EIM_DATA02 ECSPI1_SCLK KEY_COL5 AUD3_TXC GPIO5_IO22 ARM_TRACE01

1.8V Muxing

118 DSI_D1M DSI_D1M DSI_DATA1_N 2.5V MIPI DSI differential data1 negative

119 HEADPHONE_D ET SD3_RST SD3_RESET UART3_RST_B GPIO7_IO08

3.3V Muxing

120 DSI_D0P DSI_D0P DSI_DATA0_P 2.5V MIPI DSI differential data0 positive

121 KEY_COL6_MIC ROPHONE_DET

GPIO_9 ESAI_RX_FS WDOG1_B KEY_COL6 CCM_REF_EN_B PWM1_OUT GPIO1_IO09 SD1_WP

3.3V Muxing

122 DSI_D0M DSI_D0M DSI_DATA0_N 2.5V MIPI DSI differential data0 negative

123 BT_RST_L EIM_DA1 EIM_AD01 IPU1_DISP1_DATA08 IPU2_CSI1_DATA08 GPIO3_IO01 SRC_BOOT_CFG01

3.3V Muxing

124 DSI_CLK0P DSI_CLK0P DSI_CLK0_P 2.5V MIPI DSI differential clock positive

125 ALS_INT EIM_DA0 EIM_AD00 IPU1_DISP1_DATA09 IPU2_CSI1_DATA09 GPIO3_IO00 SRC_BOOT_CFG00

3.3V Muxing

126 DSI_CLK0M DSI_CLK0M DSI_CLK0_N 2.5V MIPI DSI differential clock negative

127 WAKE_N EIM_D17 EIM_DATA17 ECSPI1_MISO IPU1_DI0_PIN06 IPU2_CSI1_PIXCLK DCIC1_OUT GPIO3_IO17 I2C3_SCL

3.3V Muxing



Pin No.


Description

128 KEY_COL5 GPIO_19 KEY_COL5 ENET_1588_EVENT0_ OUT SPDIF_OUT CCM_CLKO1 ECSPI1_RDY GPIO4_IO05 ENET_TX_ER

3.3V Muxing

129 BT_HOST WAKE EIM_D18 EIM_DATA18 ECSPI1_MOSI IPU1_DI0_PIN07 IPU2_CSI1_DATA17 IPU1_DI1_D0_CS GPIO3_IO18 I2C3_SDA

3.3V Muxing

130 CODEC_PWR_E N GPIO_1 ESAI_RX_CLK WDOG2_B KEY_ROW5 USB_OTG_ID PWM2_OUT GPIO1_IO01 SD1_CD_B

3.3V Muxing

131 3G_PWR_ON EIM_D31 EIM_DATA31 IPU1_DISP1_DATA20 IPU1_DI0_PIN12 IPU1_CSI0_DATA02 UART3_RTS_B GPIO3_IO31 USB_H1_PWR

3.3V Muxing

132 ISP0_PWR_EN ENET_TXD0 ENET_TX_DATA0 ESAI_TX4_RX1 GPIO1_IO30

3.3V Muxing

133 SIMCARD_DET NANDF_CS3 NAND_CE3_B IPU1_SISG1 ESAI_TX1 EIM_ADDR26 GPIO6_IO16 IPU2_SISG1

3.3V Muxing

134 ENET_RXD0 ENET_RXD0 XTALOSC_OSC32K_3 2K_OUT ENET_RX_DATA0 ESAI_TX_HF_CLK SPDIF_OUT GPIO1_IO27

3.3V Muxing

135 WL_RST_L EIM_CS0 EIM_CS0_B IPU1_DI1_PIN05 ECSPI2_SCLK GPIO2_IO23

3.3V Muxing

136 CSI0_DAT19 CSI0_DAT19 IPU1_CSI0_DATA19 EIM_DATA15 UART5_CTS_B GPIO6_IO05

1.8V Muxing

137 CHIP_PWD_L EIM_A25 EIM_ADDR25 ECSPI4_SS1 ECSPI2_RDY IPU1_DI1_PIN12 IPU1_DI0_D1_CS GPIO5_IO02 HDMI_TX_CEC_LINE

3.3V Muxing



Pin No.


Description

138 CSI0_DAT18 CSI0_DAT18 IPU1_CSI0_DATA18 EIM_DATA14 UART5_RTS_B GPIO6_IO04 ARM_TRACE15

1.8V Muxing

139 TRANSLATOR_E N NANDF_CLE NAND_CLE IPU2_SISG4 GPIO6_IO07

3.3V Muxing

140 CSI0_DAT17 CSI0_DAT17 IPU1_CSI0_DATA17 EIM_DATA13 UART4_CTS_B GPIO6_IO03 ARM_TRACE14

1.8V Muxing

141 BT_WAKE_B_1 V8

SD1_CMD SD1_CMD ECSPI5_MOSI PWM4_OUT GPT_COMPARE1 GPIO1_IO18

1.8V Muxing

142 CSI0_DAT16 CSI0_DAT16 IPU1_CSI0_DATA16 EIM_DATA12 UART4_RTS_B GPUO6_IO02 ARM_TRACE13

1.8V Muxing

143 3G_RESET NANDF_RB0 NAND_READY_B IPU2_DI0_PIN01 GPIO6_IO10

3.3V Muxing

144 CSI0_DAT15 CSI0_DAT15 IPU1_CSI0_DATA15 EIM_DATA11 UART5_RX_DATA GPUO6_IO01 ARM_TRACE12

1.8V Muxing

145 WIRELESS_DIS NANDF_WP_B NAND_WP_B IPU2_SISG5 GPIO6_IO09

3.3V Muxing

146 AUX_3V15 PMIC SW4 output(3.15V)

Output 3.15V 3.15V power output

147 RESET PMIC pin PWRON

Input PWRON is an input signal to the PMIC that generates a turn-on event.

148 CSI0_DAT14 CSI0_DAT14 IPU1_CSI0_DATA14 EIM_DATA10 UART5_TX_DATA GPIO6_IO00 ARM_TRACE11

1.8V Muxing

149 USB_H1_OC EIM_D30 EIM_DATA30 IPU1_DISP1_DATA21 IPU1_DI0_PIN11 IPU1_CSI0_DATA03 UART3_CTS_B GPIO3_IO30 USB_H1_OC

3.3V Muxing

150 CSI0_DAT13 CSI0_DAT13 IPU1_CSI0_DATA13 EIM_DATA09 UART4_RX_DATA GPIO5_IO31 ARM_TRACE10

1.8V Muxing



Pin No.


Description

151 USB_OTG_OC EIM_D21 EIM_DATA21 ECSPI4_SCLK IPU1_DI0_PIN17 IPU2_CSI1_DATA11 USB_OTG_OC GPIO3_IO21 I2C1_SCL SPDIF_IN

3.3V Muxing


153 CPUPWRON ONOFF SRC_ONOFF Input(PU100K) 3.0V Muxing

154 CSI0_DAT12 CSI0_DAT12 IPU1_CSI0_DATA12 EIM_DATA08 UART4_TX_DATA GPUO5_IO30 ARM_TRACE09

1.8V Muxing

155 CAN1_RX GPIO_8 ESAI_TX5_RX0 XTALOSC_REF_CLK_3 2K EPIT2_OUT FLEXCAN1_RX UART2_RX_DATA GPIO1_IO08 SPDIF_SR_CLK USB_OTG_PWR_CTL_ WAKE

3.3V Muxing

156 CSI0_DAT11 CSI0_DAT11 IPU1_CSI0_DATA11 AUD3_RXFS ECSPU2_SS0 UART1_RX_DATA GPIO5_IO29 ARM_TRACE08

1.8V Muxing

157 CAN1_TX GPIO_7 ESAI_TX4_RX1 ECSPI5_RDY EPIT1_OUT FLEXCAN1_TX UART2_TX_DATA GPIO1_IO07 SPDIF_LOCK USB_OTG_HOST_MO DE

3.3V Muxing


159 CLK1_P CLK1_P CLK1_P 2.5V PCIe clock differential pair positive

160 CSI0_DAT10 CSI0_DAT10 IPU1_CSI0_DATA10 AUD3_RXC ECSPI2_MISO UART1_TX_DATA GPUO5_IO28 ARM_TRACE07

1.8V Muxing

161 CLK1_N CLK1_N CLK1_N 2.5V PCIe clock differential pair negative

162 CSI0_VSYNCH CSI0_VSYNC IPU1_CSI0_VSYNC EIM_DATA01 GPIO5_IO21 ARM_TRACE00

1.8V Muxing




Pin No.


Description

164 CSI0_HSYNCH CSI0_MCLK IPU1_CSI0_HSYNC CCM_CLKO1 GPUO5_IO19 ARM_TRACE_CTL

1.8V Muxing

165 PCIE_RST_B GPIO_17 ESAI_TX0 ENET_1588_EVENT3_ IN CCM_PMIC_READY SDMA_EXT_EVENT0 SPDIF_OUT GPIO7_IO12

3.3V Muxing


167 PCIE_DIS_B GPIO_2 ESAI_TX_FS KEY_ROW6 GPIO1_IO02 SD2_WP MLB_DATA

3.3V Muxing

168 CSI0_STROBE CSI0_DATA_E N IPU1_CSI0_DATA_EN EIM_DATA00 GPIO5_IO20 ARM_TRACE_CLK

1.8V Muxing


170 USBHUB_nRST EIM_BCLK EIM_BCLK IPU1_DI1_PIN16 GPIO6_IO31

3.3V Muxing

171 I2C2_SCL EIM_EB2, PMIC_SCL

I2C2_SCL 3.3V Muxing


173 I2C2_SDA EIM_D16, PMIC_SDA

I2C2_SDA 3.3V Muxing

174 CSI0_RST_B SD1_DAT1 SD1_DATA1 ECSPI5_SS0 PWM3_OUT GPT_CAPTURE2 GPIO1_IO17

1.8V Muxing


176 CSI0_PWN SD1_DAT0 SD1_DATA0 CESPI5_MISO GPT_CAPTURE1 GPIO1_IO16

1.8V Muxing

177 KEY_ROW4 KEY_ROW4 FLEXCAN2_RX IPU1_SISG5 USB_OTG_PWR KEY_ROW4 UART5_CTS_B GPIO4_IO15

3.3V Muxing


179 KEY_COL4 KEY_COL4 FLEXCAN2_TX IPU1_SISG4 USB_OTG_OC KEY_COL4 UART5_RTS_B GPIO4_IO14

3.3V Muxing

180 CSI0_PIXCLK CSI0_PIXCLK IPU1_CSI0_PIXCLK GPIO5_IO18 ARM_EVENTO

1.8V Muxing




Pin No.


Description

182 GPIO_0_CLKO GPIO_0 CCM_CLKO1 KEY_COL5 ASRC_EXT_CLK EPIT1_OUT GPIO1_IO00 USB_H1_PWR SNVS_VIO_5

3.3V Muxing

183 KEY_ROW3 KEY_ROW3 XTALOSC_OSC32K_3 2K_OUT ASRC_EXT_CLK HDMI_TX_DDC_SDA KEY_ROW3 I2C2_SDA GPIO4_IO13 SD1_VSELECT

3.3V Muxing


185 KEY_COL3 KEY_COL3 ECSPI1_SS3 ENET_CRS HDMI_TX_DDC_SCL KEY_COL3 I2C2_SCL GPIO4_IO12 SPDIF_IN

3.3V Muxing

186 CSI_PWN SD1_DAT2 SD1_DATA2 ECSPI5_SS1 GPT_COMPARE2 PWM2_OUT WDOG1_B GPIO1_IO19 WDOG1_RESET_B_D EB

1.8V Muxing


188 CSI_RST_B SD1_CLK SD1_CLK ECSPI5_SCLK XTALOSC_OSC32K_3 2K_OUT GPT_CLKIN GPIO1_IO20

1.8V Muxing

189 KEY_ROW2_HD MI_CEC_IN

KEY_ROW2 ECSPI1_SS2 ENET_TX_DATA2 FLEXCAN1_RX KEY_ROW2 SD2_VSLECT GPIO4_IO11 HDMI_TX_CEC_LINE

3.3V Muxing


191 KEY_COL2 KEY_COL2 ECSPI1_SS1 ENET_RX_DATA2 FLEXCAN1_TX KEY_COL2 ENET_MDC GPIO4_IO10 USN_H1_PWR_CTL_ WAKE

3.3V Muxing

192 CSI_D1P CSI_D1P CSI_DATA1_P 2.5V MIPI CSI differential data1 positive




Pin No.


Description

194 CSI_D1M CSI_D1M CSI_DATA1_N 2.5V MIPI CSI differential data1 negative

195 KEY_ROW1 KEY_ROW1 ECSPI1_SS0 ENET_COL AUD5_RXD KEY_ROW1 UART5_RX_DATA GPIO4_IO09 SD2_VSELECT

3.3V Muxing

196 CSI_D0P CSI_D0P CSI_DATA0_P 2.5V MIPI CSI differential data0 positive

197 KEY_COL1 KEY_COL1 ECSPI1_MISO ENET_MDIO AUD5_TXFS KEY_COL1 UART5_TX_DATA GPIO4_IO08 SD1_VSELECT

3.3V Muxing

198 CSI_D0M CSI_D0M CSI_DATA0_N 2.5V MIPI CSI differential data0 negative



201 KEY_ROW0 KEY_ROW0 ECSPI1_MOSI ENET_TX_DATA3 AUD5_TXD KEY_ROW0 UART4_RX_DATA GPIO4_IO07 DCIC2_OUT

3.3V Muxing

202 CSI_CLK0P CSI_CLK0P CSI_CLK0_P 2.5V MIPI CSI differential clock positive

203 KEY_COL0 KEY_COL0 ECSPI1_SCLK ENET_RX_DATA3 AUD5_TXC KEY_COL0 UART4_TX_DATA GPIO4_IO06 DCIC1_OUT

3.3V Muxing

204 CSI_CLK0M CSI_CLK0M CSI_CLK1_N 2.5V MIPI CSI differential clock negative

Table 3-1: 204-pin SO-DIMM Pin Assignment



4 SIGNAL DESCRIPTION PER BLOCK/INSTANCE

This chapter describes in detail the external interfaces per block/instance, referring to the default SOM pin names.

SIGNAL:

Signal name on the block/instance

PIN NO. :

Pin number on the 204pin SO-DIMM connector

PIN NAME:

Pin name on the 204pin SO-DIMM connector

IMX6 PAD NAME:

Pad name on iMX6

SIGNAL TYPE:

I – In

Out

I/O – Input/Output

DESCRIPTION:

Short pin functionality description

4.1 ASYNCHRONOUS SAMPLE RATE CONVERTER (ASRC) The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a signal associated with an input clock into a signal associated with a different output clock.

The ASRC is implemented as a co-processor in hardware, with minimal ARM Platform intervention required.

The following table describes the external signals of ASRC:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

ASRC_EXT_CLK 182 GPIO_0_CLKO GPIO_0 O 3.3V -

183 KEY_ROW3 KEY_ROW3 3.3V -

Table 4-1: External Signals Of ASRC

4.2 DIGITAL AUDIO MUX (AUDMUX) The Digital Audio Multiplexer (AUDMUX) provides a programmable interconnect device for voice, audio, and synchronous data routing between Synchronous Serial Interface Controller (SSI) and audio/voice codec’s (also known as coder-decoders) peripheral serial interfaces.



The following table describes the external signals of AUDMUX:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

AUD3_RXC 160 CSI0_DAT10 CSI0_DAT10 I/O 1.8V Receive clock signal

AUD3_RXD 111 AUD3_RXD CSI0_DAT7 I/O 1.8V Data receive signal

AUD3_RXFS 156 CSI0_DAT11 CSI0_DAT11 I/O 1.8V Receive frame sync signal

AUD3_TXC 117 AUD3_TXC CSI0_DAT4 I/O 1.8V Transmit clock signal

AUD3_TXD 115 AUD3_TXD CSI0_DAT5 I/O 1.8V Data transmit signal

AUD3_TXFS 113 AUD3_TXFS CSI0_DAT6 I/O 1.8V Transmit frame sync signal

AUD4_RXC 24 SD2_CMD SD2_CMD I/O 1.8V Receive clock signal

AUD4_RXD 20 SD2_DATA0 SD2_DAT0 I/O 1.8V Data receive signal

AUD4_RXFS 22 SD2_CLK SD2_CLK I/O 1.8V Receive frame sync signal

AUD4_TXC 14 SD2_DATA3 SD2_DAT3 I/O 1.8V Transmit clock signal

AUD4_TXD 16 SD2_DATA2 SD2_DAT2 I/O 1.8V Data transmit signal

AUD4_TXFS 18 SD2_DATA1 SD2_DAT1 I/O 1.8V Transmit frame sync signal

AUD5_RXC 58 UART3_RXD EIM_D25 I/O 3.3V Receive clock signal

AUD5_RXD 195 KEY_ROW1 KEY_ROW1 I/O 3.3V Data receive signal

AUD5_RXFS 60 UART3_TXD EIM_D24 I/O 3.3V Receive frame sync signal

AUD5_TXC 203 KEY_COL0 KEY_COL0 I/O 3.3V Transmit clock signal

AUD5_TXD 201 KEY_ROW0 KEY_ROW0 I/O 3.3V Data transmit signal

AUD5_TXFS 197 KEY_COL1 KEY_COL1 I/O 3.3V Transmit frame sync signal

Table 4-2: External Signals Of AUDMUX

4.3 CLOCK CONTROLLER MODULE (CCM) The Clock Control Module (CCM) generates and controls clocks to the various modules in the design and manages low power modes. This module uses the available clock sources to generate the clock roots.

The following table describes the external signals of CCM:



Signal Pin No. Pin Name iMX6 pad name Signal

Type

Voltage

Level

Description

CCM_CLKO1 164 CSI0_HSYNC H

CSI0_MCLK O 1.8V Observability clock 1 output

182 GPIO_0_CLK O

GPIO_0 3.3V

51 KEY_VOL_D N

GPIO_5 3.3V

128 KEY_COL5 GPIO_19 3.3V

CCM_CLKO2 108 I2C3_SCL GPIO_3 O 3.3V Observability clock 2 output

102 LED_EN NANDF_CS2 3.3V

CCM_PMIC_ READY

165 PCIE_RST_B GPIO_17 I 3.3V Signal coming from PMIC to indicate that the voltage started to change as result of change in CCM_PMIC_VSTBY_REQ

CCM_REF_EN _B

121 KEY_COL6_ MICROPHO NE_DET

GPIO_9 O 3.3V Enabled external reference clock(CKIH)

Table 4-3: External Signals Of CCM

4.4 DISPLAY CONTENT INTEGRITY CHECKER (DCIC) The goal of the DCIC is to verify that a safety-critical information sent to a display is not corrupted.

Such a verification is mandatory for warning icons in the instrument cluster of a car, to comply with the ASIL B (Automotive Safety Integrity Level B) specification. It is also required in other safety-sensitive systems.



Using external muxing DCIC can monitor either one of the IPU display port outputs or feedback signals going from IO pads of Parallel display interface.

The following table describes the external signals of DCIC:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

DCIC1_OUT

127 WAKE_N EIM_D17 O

3.3V DCIC1

203 KEY_COL0 KEY_COL0 3.3V

DCIC2_OUT

201 KEY_ROW0 KEY_ROW0 O

3.3V DCIC2

20 SD2_DATA0 SD2_DAT0 1.8V

Table 4-4: External Signals Of DCIC

4.5 ENHANCED CONFIGURABLE SPI (ECSPI) The Enhanced Configurable Serial Peripheral Interface (ECSPI) is a full-duplex, synchronous, four-wire serial communication block.

The ECSPI contains a 64 x 32 receive buffer (RXFIFO) and a 64 x 32 transmit buffer (TXFIFO). With data FIFOs, the ECSPI allows rapid data communication with fewer software interrupts.

The following table describes the external signals of ECSPI 1:

Signal Pin No. Pin Name iMX6 pad name Signal Type

Voltage Level

Description

ECSPI1_MISO 113 AUD3_TXFS CSI0_DAT6 I/O 1.8V Master data in; slave data out

127 WAKE_N EIM_D17 3.3V


ECSPI1_MOSI 115 AUD3_TXD CSI0_DAT5 I/O 1.8V Master data out; slave data in

129 BT_HOST WAKE

EIM_D18 3.3V

201 KEY_ROW0 KEY_ROW0 3.3V

ECSPI1_RDY 128 KEY_COL5 GPIO_19 I 3.3V SPI data ready signal

ECSPI1_SCLK 117 AUD3_TXC CSI0_DAT4 I/O 1.8V SPI clock signal


ECSPI1_SS0 111 AUD3_RXD CSI0_DAT7 I/O 1.8V Chip select signal


ECSPI1_SS1 57 UART1_CTS EIM_D19 I/O 3.3V Chip select signal



Signal Pin No. Pin Name iMX6 pad name Signal Type

Voltage Level

Description


ECSPI1_SS2 60 UART3_TXD EIM_D24 I/O 3.3V Chip select signal

189 KEY_ROW2_H DMI_CEC_IN

KEY_ROW2 3.3V

Table 4-5: External Signals Of ECSPI 1


Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

ECSPI2_MISO

160 CSI0_DAT10 CSI0_DAT10 I/O

1.8V Master data in; slave data out

110 EIM_OE EIM_OE 3.3V

ECSPI2_MOSI 95 I2C1_SCL CSI0_DAT9 I/O 1.8V Master data out; slave data in

ECSPI2_RDY 137 CHIP_PWD_L EIM_A25 I 3.3V SPI data ready signal

ECSPI2_SCLK

97 I2C1_SDA CSI0_DAT8 I/O

1.8V SPI clock signal

135 WL_RST_L EIM_CS0 3.3V

ECSPI2_SS0 156 CSI0_DAT11 CSI0_DAT11 I/O 1.8V Chip select signal

ECSPI2_SS2 60 UART3_TXD EIM_D24 I/O 3.3V Chip select signal

ECSPI2_SS3 58 UART3_RXD EIM_D25 I/O 3.3V Chip select signal



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

ECSPI4_MISO 31 USB_OTG_PW R_EN

EIM_D22 I/O 3.3V Master data in; slave data out

ECSPI4_MOSI 52 UART2_RTS EIM_D28 I/O 3.3V Master data out; slave data in

ECSPI4_RDY 64 UART3_CTS EIM_EB3 I 3.3V SPI data ready signal

ECSPI4_SCLK 151 USB_OTG_OC EIM_D21 I/O 3.3V SPI clock signal

ECSPI4_SS0 59 UART1_RTS EIM_D20 I/O 3.3V Chip select signal

50 UART2_CTS EIM_D29 3.3V

ECSPI4_SS1 137 CHIP_PWD_L EIM_A25 I/O 3.3V Chip select signal



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

ECSPI4_SS2 60 UART3_TXD EIM_D24 IO 3.3V Chip select signal

ECSPI4_SS3 58 UART3_RXD EIM_D25 I/O 3.3V Chip select signal



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

ECSPI5_MISO

176 CSI0_PWN SD1_DAT0 I/O

1.8V Master data in; slave data out


ECSPI5_MOSI

141 BT_WAKE_B_

1V8

SD1_CMD

I/O

1.8V

Master data out; slave data in 24 SD2_CMD SD2_CMD 1.8V

ECSPI5_RDY 157 CAN1_TX GPIO_7 I 3.3V SPI data ready signal

ECSPI5_SCLK

188 CSI_RST_B SD1_CLK I/O

1.8V SPI clock signal

22 SD2_CLK SD2_CLK 1.8V


4.6 ENHANCED PERIODIC INTERRUPT TIMER (EPIT)

EPIT is a 32-bit set-and-forget timer that is capable of providing precise interrupts at regular intervals with minimal processor intervention. EPIT begins counting after it is enabled by software.

The following table describes the external signals of EPIT:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal

Type

Voltage

Level

Description

EPIT1_OUT 57 UART1_CTS EIM_D19 O 3.3V Output 1 pin at chip boundary

for indicating the occurrence of

An output compare event

through a specified transition.

182 GPIO_0_CLKO GPIO_0 3.3V

157 CAN1_TX GPIO_7 3.3V

EPIT2_OUT 59 UART1_RTS EIM_D20 O 3.3V Output 2 pin at chip boundary for indicating the occurrence of an output compare event through a specified transition.

155 CAN1_RX GPIO_8 3.3V

Table 4-9: External Signals Of EPIT



4.7 ENHANCED SERIAL AUDIO INTERFACE (ESAI)

The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, Sony/Phillips Digital Interface (SPDIF) transceivers, and other DSPs.

The following table describes the external signals of ESAI:

Signal

Pin No.

Pin Name

iMX6

pad

name

Signal

Type

Voltage

Level

Description

ESAI_RX_CLK

130 CODEC_P WR_EN

GPIO_1 I/O

3.3V RX serial bit clock for the ESAI interface. The direction can be programmed.

ESAI_RX_FS

121 KEY_COL6 _MICROPH ONE_DET

GPIO_9

I/O

3.3V RX frame sync signal for the ESAI interface.

ESAI_RX_HF_C LK

25 USB_OTG_ ID

ENET_RX_ER

I/O

3.3V RX high frequency clock for the ESAI interface.

108 I2C3_SCL GPIO_3 3.3V

ESAI_TX0

165 PCIE_RST_ B

GPIO_17

I/O

3.3V Used for transmitting data from the ESAI_TX0 serial transmit shift 102 LED_EN NANDF_CS2 3.3V

ESAI_TX1

133 SIMCARD_ DET

NANDF_CS3

I/O

3.3V Used for transmitting data from the

ESAI_TX1 serial transmit shift

register.

ESAI_TX2_RX3 33 USB_H1_P WR_EN

ENET_TXD1 I/O 3.3V Used as TX2 for transmitting data from the ESAI_TX2 serial transmit shift register when programmed as a transmitter pin Used as the RX3 signal for receiving serial data to the ESAI_RX3 serial receive shift register when programmed as a receiver pin

51 KEY_VOL_ DN

GPIO_5 3.3V

ESAI_TX3_RX2 104 LCD_PWR GPIO_16 I/O 3.3V Used as TX3 for transmitting data from the ESAI_TX2 serial transmit shift register when programmed as a transmitter pin Used as the RX2 signal for receiving

serial data to the ESAI_RX3 serial

receive shift register when programmed as a receiver pin

ESAI_TX4_RX1 132 DISP0_PW R_EN

ENET_TXD0 I/O 3.3V Used as TX4 for transmitting data from the ESAI_TX2 serial



Signal

Pin No.

Pin Name

iMX6

pad

name

Signal

Type

Voltage

Level

Description

157 CAN1_TX GPIO_7 3.3V transmit shift register when programmed as a transmitter pin Used as the RX1 signal for receiving serial data to the ESAI_RX3 serial receive shift register when programmed as a receiver pin

ESAI_TX5_RX0 155 CAN1_RX GPIO_8 I/O 3.3V Used as TX5 for transmitting data from the ESAI_TX2 serial transmit shift register when programmed as a transmitter pin Used as the RX0 signal for receiving

serial data to the ESAI_RX3 serial

receive shift register when programmed as a receiver pin

ESAI_TX_CLK

106 I2C3_SDA GPIO_6

I/O

3.3V TX serial bit clock for the ESAI interface. The direction can be programmed.

ESAI_TX_FS 167 PCIE_DIS_ B

GPIO_2 I/O 3.3V Frame sync for both the transmitters and receivers in the synchronous mode (SYN=1) and for the transmitters only in asynchronous mode

ESAI_TX_HF_C LK

134 ENET_RXD 0

ENET_RXD0 I/O 3.3V

TX high frequency clock for the ESAI interface. 53 KEY_VOL_

UP

GPIO_4 3.3V

Table 4-10: External Signals Of ESAI

4.8 FLEXIBLE CONTROLLER AREA NETWORK (FLEXCAN)

The Flexible Controller Area Network (FLEXCAN) module is a communication controller implementing the CAN protocol according to the CAN 2.0B protocol specification. The CAN protocol was primarily designed to be used as a vehicle serial data bus meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN module is a full implementation of the CAN protocol specification, which supports both standard and extended message frames. 64 Message Buffers are supported.

The following table describes the external signals of FLEXCAN:



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

FLEXCAN1_RX 155 CAN1_RX GPIO_8 I 3.3V FLEXCAN receive pin. This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.


KEY_ROW2 3.3V


FLEXCAN1_TX 157 CAN1_TX GPIO_7 O 3.3V FLEXCAN transmit pin. This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.


49 SD3_CMD SD3_CMD 3.3V

FLEXCAN2_RX 177 KEY_ROW4 KEY_ROW4 I 3.3V FLEXCAN receive pin. This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.


FLEXCAN2_TX 179 KEY_COL4 KEY_COL4 O 3.3V FLEXCAN transmit pin. This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level '0'. Recessive state is represented by logic level '1'.


Table 4-11: External Signals Of FLEXCAN

4.9 GENERAL PURPOSE INPUT/OUTPUT (GPIO)

The GPIO general-purpose input/output peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs.

When configured as an output, it is possible to write to an internal register to control the state driven on the output pin. When configured as an input, it is possible to detect the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce CORE interrupts.



The following table describes the external signals of GPIO1:

Signal Pin No. Pin Name iMX6 pad name Signal Type Voltage Level Description

GPIO1_IO00 182 GPIO_0_CLKO GPIO_0 I/O 3.3V -

GPIO1_IO01 130 CODEC_PWR_EN GPIO_1 I/O 3.3V -

GPIO1_IO02 167 PCIE_DIS_B GPIO_2 I/O 3.3V -

GPIO1_IO03 108 I2C3_SCL GPIO_3 I/O 3.3V -

GPIO1_IO04 53 KEY_VOL_UP GPIO_4 I/O 3.3V -

GPIO1_IO05 51 KEY_VOL_DN GPIO_5 I/O 3.3V -

GPIO1_IO06 106 I2C3_SDA GPIO_6 I/O 3.3V -

GPIO1_IO07 157 CAN1_TX GPIO_7 I/O 3.3V -

GPIO1_IO08 155 CAN1_RX GPIO_8 I/O 3.3V -

GPIO1_IO09 121 KEY_COL6_MICROPH ONE_DET

GPIO_9 I/O 3.3V -

GPIO1_IO10 22 SD2_CLK SD2_CLK I/O 1.8V -

GPIO1_IO11 24 SD2_CMD SD2_CMD I/O 1.8V -

GPIO1_IO12 14 SD2_DATA3 SD2_DAT3 I/O 1.8V -




GPIO1_IO16 176 CSI0_PWN SD1_DAT0 I/O 1.8V -

GPIO1_IO17 174 CSI0_RST_B SD1_DAT1 I/O 1.8V -

GPIO1_IO18 141 BT_WAKE_B_1V8 SD1_CMD I/O 1.8V -

GPIO1_IO19 186 CSI_PWN SD1_DAT2 I/O 1.8V -

GPIO1_IO20 188 CSI_RST_B SD1_CLK I/O 1.8V -

GPIO1_IO24 25 USB_OTG_ID ENET_RX_ER I/O 3.3V -

GPIO1_IO27 134 ENET_RXD0 ENET_RXD0 I/O 3.3V -

GPIO1_IO29 33 USB_H1_PWR_EN ENET_TXD1 I/O 3.3V -

GPIO1_IO30 132 DISP0_PWR_EN ENET_TXD0 I/O 3.3V -

Table 4-12: External Signals Of GPIO1




Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

GPIO2_IO00 98 SD3_CD_B NANDF_D0 I/O 3.3V -

GPIO2_IO01 96 SD3_WP NANDF_D1 I/O 3.3V -

GPIO2_IO02 28 SD2_CD_B NANDF_D2 I/O 3.3V -

GPIO2_IO03 26 SD2_WP NANDF_D3 I/O 3.3V -

GPIO2_IO04 12 SD2_DATA4 NANDF_D4 I/O 3.3V -




GPIO2_IO23 135 WL_RST_L EIM_CS0 I/O 3.3V -

GPIO2_IO25 110 EIM_OE EIM_OE I/O 3.3V -

GPIO2_IO31 64 UART3_CTS EIM_EB3 I/O 3.3V -



Signal Pin No. Pin Name iMX6 pad name Signal Type Voltage Level

Description

GPIO3_IO00 125 ALS_INT EIM_DA0 I/O 3.3V -

GPIO3_IO01 123 BT_RST_L EIM_DA1 I/O 3.3V -

GPIO3_IO17 127 WAKE_N EIM_D17 I/O 3.3V -

GPIO3_IO18 129 BT_HOST WAKE EIM_D18 I/O 3.3V -

GPIO3_IO19 57 UART1_CTS EIM_D19 I/O 3.3V -

GPIO3_IO20 59 UART1_RTS EIM_D20 I/O 3.3V -

GPIO3_IO21 151 USB_OTG_OC EIM_D21 I/O 3.3V -

GPIO3_IO22 31 USB_OTG_PWR_EN EIM_D22 I/O 3.3V -


GPIO3_IO24 60 UART3_TXD EIM_D24 I/O 3.3V -

GPIO3_IO25 58 UART3_RXD EIM_D25 I/O 3.3V -

GPIO3_IO26 56 UART2_TXD EIM_D26 I/O 3.3V -




Description

GPIO3_IO27 54 UART2_RXD EIM_D27 I/O 3.3V -


GPIO3_IO29 50 UART2_CTS EIM_D29 I/O 3.3V -

GPIO3_IO30 149 USB_H1_OC EIM_D30 I/O 3.3V -

GPIO3_IO31 131 3G_PWR_ON EIM_D31 I/O 3.3V -



Signal Pin No. Pin Name iMX6 pad name Signal Type Voltage

Level

Description

GPIO4_IO05 128 KEY_COL5 GPIO_19 I/O 3.3V -

GPIO4_IO06 203 KEY_COL0 KEY_COL0 I/O 3.3V -

GPIO4_IO07 201 KEY_ROW0 KEY_ROW0 I/O 3.3V -




GPIO4_IO11

189 KEY_ROW2_HDMI_C EC_IN

KEY_ROW2 I/O 3.3V -








Description

GPIO5_IO00 109 Touch_INT EIM_WAIT I/O 3.3V -

GPIO5_IO02 137 CHIP_PWD_L EIM_A25 I/O 3.3V -




Description

GPIO5_IO18 180 CSI0_PIXCLK CSI0_PIXCLK I/O 1.8V -

GPIO5_IO19 164 CSI0_HSYNCH CSI0_MCLK I/O 1.8V -

GPIO5_IO20 168 CSI0_STROBE CSI0_DATA_EN I/O 1.8V -

GPIO5_IO21 162 CSI0_VSYNCH CSI0_VSYNC I/O 1.8V -

GPIO5_IO22 117 AUD3_TXC CSI0_DAT4 I/O 1.8V -

GPIO5_IO23 115 AUD3_TXD CSI0_DAT5 I/O 1.8V -

GPIO5_IO24 113 AUD3_TXFS CSI0_DAT6 I/O 1.8V -

GPIO5_IO25 111 AUD3_RXD CSI0_DAT7 I/O 1.8V -

GPIO5_IO26 97 I2C1_SDA CSI0_DAT8 I/O 1.8V -

GPIO5_IO27 95 I2C1_SCL CSI0_DAT9 I/O 1.8V -

GPIO5_IO28 160 CSI0_DAT10 CSI0_DAT10 I/O 1.8V -







Description







GPIO6_IO07 139 TRANSLATOR_EN NANDF_CLE I/O 3.3V -

GPIO6_IO08 100 LED_PWR NANDF_ALE I/O 3.3V -

GPIO6_IO09 145 WIRELESS_DIS NANDF_WP_B I/O 3.3V -




Description

GPIO6_IO10 143 3G_RESET NANDF_RB0 I/O 3.3V -

GPIO6_IO11 48 DISP_RST_B NANDF_CS0 I/O 3.3V -

GPIO6_IO14 112 DISP_PWR_EN NANDF_CS1 I/O 3.3V -

GPIO6_IO15 102 LED_EN NANDF_CS2 I/O 3.3V -

GPIO6_IO16 133 SIMCARD_DET NANDF_CS3 I/O 3.3V -

GPIO6_IO17 63 UART1_TXD SD3_DAT7 I/O 3.3V -

GPIO6_IO18 61 UART1_RXD SD3_DAT6 I/O 3.3V -

GPIO6_IO31 170 USBHUB_nRST EIM_BCLK I/O 3.3V -




Description


GPIO7_IO01 107 PCIE_WAKE_B SD3_DAT4 I/O 3.3V -

GPIO7_IO02 49 SD3_CMD SD3_CMD I/O 3.3V -

GPIO7_IO03 47 SD3_CLK SD3_CLK I/O 3.3V -





GPIO7_IO08 119 HEADPHONE_DET SD3_RST I/O 3.3V -

GPIO7_IO11 104 LCD_PWR GPIO_16 I/O 3.3V -

GPIO7_IO12 165 PCIE_RST_B GPIO_17 I/O 3.3V -


4.10 GENERAL PURPOSE TIMER (GPT) The GPT has a 32-bit up-counter. The timer counter value can be captured in a register using an event on an external pin. The capture trigger can be programmed to be a rising or/and falling edge. The GPT can also generate an event on the DO_CMPOUTn pins and an interrupt when the timer reaches a programmed



value. The GPT has a 12-bit prescaler, which provides a programmable clock frequency derived from multiple clock sources.

The following table describes the external signals of GPT:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

GPT_CAPTURE 1

176 CSI0_PWN SD1_DAT0 I 1.8V Input pin for a capture event for Input Capture Channel 1.

GPT_CAPTURE 2

174 CSI0_RST_B SD1_DAT1 I 1.8V Input pin for a capture event for Input Capture Channel 2.

GPT_CLKIN

188 CSI_RST_B SD1_CLK I 1.8V Input pin for an external clock that the counter can be operated at.

GPT_COMPAR E1

141 BT_WAKE_B

_1V8

SD1_CMD O 1.8V Output pin that indicates a "compare event" occurrence in Output Compare Channel 1.

GPT_COMPAR E2

186 CSI_PWN SD1_DAT2 O 1.8V Output pin that indicates a "compare event" occurrence in Output Compare Channel 2.

Table 4-19: External Signals Of GPT

4.11 HDMI The High Definition Multimedia Interface (HDMI) is a wired digital interconnect that replaces the analog TV out or VGA out.

HDMI is capable of transferring uncompressed video, audio, and data using a single cable.

The following table describes the external signals of HDMI:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

HDMI_TX_CEC _LINE

137 CHIP_PWD_L EIM_A25 I/O 3.3V CEC line between source and sink


KEY_ROW2 3.3V

HDMI_TX_CLK

_N

44 HDMI_CLKM HDMI_CLKM I

2.5V Negative clock signal

HDMI_TX_CLK

_P

42 HDMI_CLKP HDMI_CLKP I

2.5V Positive clock signal

HDMI_TX_DAT A0_N

40 HDMI_D0M HDMI_D0M I/O

2.5V Negative data signal 0

HDMI_TX_DAT A0_P

38 HDMI_D0P HDMI_D0P I/O

2.5V Positive data signal 0

HDMI_TX_DAT A1_N

36 HDMI_D1M HDMI_D1M I/O

2.5V Negative data signal 1



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

HDMI_TX_DAT A1_P

34 HDMI_D1P HDMI_D1P I/O 2.5V

Positive data signal 1

HDMI_TX_DAT A2_N

32 HDMI_D2M HDMI_D2M I/O 2.5V

Negative data signal 2

HDMI_TX_DAT A2_P

30 HDMI_D2P HDMI_D2P I/O 2.5V

Positive data signal 2

HDMI_TX_DD C_SCL

171 I2C2_SCL EIM_EB2, PMIC_SCL

I/O 3.3V

SCL signal


HDMI_TX_DD C_SDA

173

I2C2_SDA EIM_D16, PMIC_SDA

I/O 3.3V

SDA signal


HDMI_TX_HP D 46 HDMI_HPD HDMI_HPD I/O 2.5V

HPD signal

Table 4-20: External Signals Of HDMI

4.12 I2C The Inter IC (I2C) provides functionality of a standard I2C slave and master. The I2C is designed to be compatible with the standard NXP I2C bus protocol.

I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices. The flexible I2C standard allows additional devices to be connected to the bus for expansion and system development.

The following table describes the external signals of I2C 1:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

I2C1_SCL

95 I2C1_SCL CSI0_DAT9 I/O

1.8V Serial clock

151 USB_OTG_OC EIM_D21 3.3V

I2C1_SDA


1.8V Serial data

52 UART2_RTS EIM_D28 3.3V

Table 4-21: External Signals Of I2C 1




Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

I2C2_SCL 171 I2C2_SCL EIM_EB2, PMIC_SCL

I/O 3.3V Serial clock


I2C2_SDA 173 I2C2_SDA EIM_D16, PMIC_SDA

I/O 3.3V Serial data




Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

I2C3_SCL

127 WAKE_N EIM_D17

I/O

3.3V

Serial clock 108 I2C3_SCL GPIO_3 3.3V

51 KEY_VOL_DN GPIO_5 3.3V

I2C3_SDA 129 BT_HOST WAKE EIM_D18 I/O 3.3V Serial data

106 I2C3_SDA GPIO_6 3.3V

104 LCD_PWR GPIO_16 3.3V


4.13 IMAGE PROCESSING UNIT (IPU) The IPU is planned to be a part of the video and graphics subsystem in an application processor.

The goal of the IPU is to provide comprehensive support for the flow of data from an image sensor and/or to a display device.

The following table describes the external signals of IPU1:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

IPU1_CSI0_DATA00 54 UART2_RXD EIM_D27 I 3.3V -

IPU1_CSI0_DATA01 56 UART2_TXD EIM_D26 I 3.3V -

IPU1_CSI0_DATA02 131 3G_PWR_ON EIM_D31 I 3.3V -

IPU1_CSI0_DATA03 149 USB_H1_OC EIM_D30 I 3.3V -

IPU1_CSI0_DATA04 117 AUD3_TXC CSI0_DAT4 I 1.8V -

IPU1_CSI0_DATA05 115 AUD3_TXD CSI0_DAT5 I 1.8V -



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

IPU1_CSI0_DATA06 113 AUD3_TXFS CSI0_DAT6 I 1.8V -

IPU1_CSI0_DATA07 111 AUD3_RXD CSI0_DAT7 I 1.8V -

IPU1_CSI0_DATA08 97 I2C1_SDA CSI0_DAT8 I 1.8V -

IPU1_CSI0_DATA09 95 I2C1_SCL CSI0_DAT9 I 1.8V -

IPU1_CSI0_DATA10 160 CSI0_DAT10 CSI0_DAT10 I 1.8V -










IPU1_CSI0_DATA_EN 168 CSI0_STROBE CSI0_DATA_EN I 1.8V -

IPU1_CSI0_HSYNC 164 CSI0_HSYNCH CSI0_MCLK I 1.8V -

IPU1_CSI0_PIXCLK 180 CSI0_PIXCLK CSI0_PIXCLK I 1.8V -

IPU1_CSI0_VSYNC 162 CSI0_VSYNCH CSI0_VSYNC I 1.8V -

Table 4-24: External Signals Of IPU1

The following table describes the external signals of IPU2:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

IPU2_CSI1_DATA08 123 BT_RST_L EIM_DA1 I 3.3V -

IPU2_CSI1_DATA09 125 ALS_INT EIM_DA0 I 3.3V -

IPU2_CSI1_DATA10 31 USB_OTG_PWR_EN EIM_D22 I 3.3V -



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

IPU2_CSI1_DATA11 151 USB_OTG_OC EIM_D21 I 3.3V -

IPU2_CSI1_DATA12 52 UART2_RTS EIM_D28 I 3.3V -

IPU2_CSI1_DATA13 54 UART2_RXD EIM_D27 I 3.3V -

IPU2_CSI1_DATA14 56 UART2_TXD EIM_D26 I 3.3V -

IPU2_CSI1_DATA15 59 UART1_RTS EIM_D20 I 3.3V -

IPU2_CSI1_DATA16 57 UART1_CTS EIM_D19 I 3.3V -

IPU2_CSI1_DATA17 129 BT_HOST WAKE EIM_D18 I 3.3V -

IPU2_CSI1_DATA_EN 62 UART3_RTS EIM_D23 I 3.3V -

IPU2_CSI1_HSYNC 64 UART3_CTS EIM_EB3 I 3.3V -

IPU2_CSI1_PIXCLK 127 WAKE_N EIM_D17 I 3.3V -

IPU2_CSI1_VSYNC 50 UART2_CTS EIM_D29 I 3.3V -

Table 4-25: External Signals Of IPU2

4.14 KEYPAD PORT (KPP) The Keypad Port (KPP) is a 16-bit peripheral that can be used as a keypad matrix interface or as general purpose input/output (I/O).

The following table describes the external signals of KPP:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

KEY_COL0 203 KEY_COL0 KEY_COL0 I/O 3.3V Column input or output pin





KEY_COL5 117 AUD3_TXC CSI0_DAT4 I/O 1.8V Column input or output pin

182 GPIO_0_CLKO GPIO_0 3.3V



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description



KEY_COL6 113 AUD3_TXFS CSI0_DAT6 I/O 1.8V Column input or output pin

121 KEY_COL6_MI CROPHONE_D ET

GPIO_9 3.3V


KEY_COL7


1.8V Column input or output pin 53 KEY_VOL_UP GPIO_4 3.3V


KEY_ROW0 201 KEY_ROW0 KEY_ROW0 I/O 3.3V Row input or output pin


KEY_ROW2


KEY_ROW2 I/O 3.3V Row input or output pin



KEY_ROW5 115 AUD3_TXD CSI0_DAT5 I/O 1.8V Row input or output pin

130 CODEC_PWR_ EN GPIO_1 3.3V


KEY_ROW6

111 AUD3_RXD CSI0_DAT7 I/O 1.8V Row input or output pin 167 PCIE_DIS_B GPIO_2 3.3V


KEY_ROW7

95 I2C1_SCL CSI0_DAT9 I/O 1.8V Row input or output pin 51 KEY_VOL_DN GPIO_5 3.3V


Table 4-26: External Signals Of KPP



4.15 LVDS DISPLAY BRIDGE (LDB) The LVDS Display Bridge (LDB) connects the IPU (Image Processing Unit) to an External LVDS Display Interface.

The purpose of the LDB is to support flow of synchronous RGB data from the IPU to external display devices through LVDS interface.

The following table describes the external signals of LDB:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

LVDS0_CLK_N 76 LVDS0_CLK_N LVDS0_CLK_N I/O 2.5V LVDS0 negative clock signal

LVDS0_CLK_P 74 LVDS0_CLK_P LVDS0_CLK_P I/O 2.5V LVDS0 positive clock signal

LVDS0_DATA0_N 92 LVDS0_TX0_N LVDS0_TX0_N I/O 2.5V LVDS0 negative data 0 signal

LVDS0_DATA0_P 90 LVDS0_TX0_P LVDS0_TX0_P I/O 2.5V LVDS0 positive data 0 signal







Table 4-27: External Signals Of LDB

4.16 MIPI- CAMERA SERIAL INTERFACE HOST CONTROLLER (MIPI_CSI)

CSI-2 is a high performance serial interconnect bus for mobile applications connecting camera sensors to the host system.

The CSI-2 Host Controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 Specification, providing an interface between the System and the MIPI D-PHY, allowing the communication with a MIPI CSI-2 compliant Camera Sensor.

The following table describes the external signals of MIPI_CSI:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

CSI_CLK0_N 204 CSI_CLK0M CSI_CLK0M I 2.5V -

CSI_CLK0_P 202 CSI_CLK0P CSI_CLK0P I 2.5V -

CSI_DATA0_N 198 CSI_D0M CSI_D0M I 2.5V -



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

CSI_DATA0_P 196 CSI_D0P CSI_D0P I 2.5V -

CSI_DATA1_N 194 CSI_D1M CSI_D1M I 2.5V -

CSI_DATA1_P 192 CSI_D1P CSI_D1P I 2.5V -

Table 4-28: External Signals Of MIPI_CSI

4.17 MIPI DISPLAY SERIAL INTERFACE HOST CONTROLLER (MIPI_DSI) DSI is a high performance serial interconnect bus for mobile applications connecting display system to the host system.

The DSI Host Controller is a digital core that implements all protocol functions defined in the MIPI DSI Specification, providing an interface between the System and the MIPI D-PHY, and allowing communication with a MIPI DSI-compliant Display.

The following table describes the external signals of MIPI_DSI:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

DSI_CLK0_N 126 DSI_CLK0M DSI_CLK0M I 2.5V -

DSI_CLK0_P 124 DSI_CLK0P DSI_CLK0P I 2.5V -

DSI_DATA0_N 122 DSI_D0M DSI_D0M I 2.5V -

DSI_DATA0_P 120 DSI_D0P DSI_D0P I 2.5V -

DSI_DATA1_N 118 DSI_D1M DSI_D1M I 2.5V -

DSI_DATA1_P 116 DSI_D1P DSI_D1P I 2.5V -

Table 4-29: External Signals Of MIPI_DSI

4.18 PCI EXPRESS (PCIE) PCI Express includes the following cores:

PCI Express Dual Mode (DM) core

PCI Express Root Complex (RC) core

PCI Express Endpoint (EP) core

The following table describes the external signals of PCIe:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

PCIE_RX_N 105 PCIE_RXM PCIE_RXM 2.5V



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

PCIE_RX_P 103 PCIE_RXP PCIE_RXP 2.5V

PCIE_TX_N 101 PCIE_TXM PCIE_TXM 2.5V

PCIE_TX_P 99 PCIE_TXP PCIE_TXP 2.5V

Table 4-30: External Signals Of PCIe

4.19 PULSE WIDTH MODULATION (PWM) The Pulse Width Modulation (PWM) has a 16-bit counter, and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 x 16 data FIFO.

The following table describes the external signals of PWM:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

PWM1_OUT 121 KEY_COL6_ MICROPHON E_DET

GPIO_9 O 3.3V This is the PWM1 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.

94 DISP0_CONT RAST

Connect to SD1_DAT3 through level shift NLSV1T34

3.3V

PWM2_OUT 130 CODEC_PWR_EN

GPIO_1 O 3.3V This is the PWM2 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.

186 CSI_PWN SD1_DAT2 1.8V

PWM3_OUT 174 CSI0_RST_B SD1_DAT1 O 1.8V This is the PWM3 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.

PWM4_OUT 141 BT_WAKE_B_1V8

SD1_CMD O 1.8V This is the PWM4 functional output of the PWM. A modulated signal of the block is observed at this pin. It can be viewed as a clock signal whose period and duty cycle can be varied with different settings of the cycle of 50%.

Table 4-31: External Signals Of PWM

4.20 SERIAL ADVANCED TECHNOLOGY ATTACHMENT PHY (SATA PHY) The Serial-ATA PHY is an ultra low-power SATA physical layer that complies with Serial ATA , Revision 2.5. The following table describes the external signals of SATA PHY:



Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

SATA_PHY_RX_N 17 SATA_RXN SATA_RXM I 2.5V Negative receive signal

SATA_PHY_RX_P 19 SATA_RXP SATA_RXP I 2.5V Positive receive signal

SATA_PHY_TX_N 15 SATA_TXN SATA_TXM O 2.5V Negative transmit signal

SATA_PHY_TX_P 13 SATA_TXP SATA_TXP O 2.5V Positive transmit signal

Table 4-32: External Signals Of SATA PHY

4.21 SYSTEM JTAG CONTROLLER (SJC) The System JTAG Controller (SJC) provides debug and test control with the maximum security.

The following table describes the external signals of SJC:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal

Type

Voltage

Level

Description

JTAG_DE_B 104 LCD_PWR GPIO_16 O 3.3V SoC debug request/acknowledge pin. The DE_IN_B pin is used to propagate an external debug request event to the core(s). This functionality must be enabled first, by set of DE_to_ARM /DE_to_SDMA bits in SJC's DCR register. It is SoC implementation dependent, whether this pin can also be used to reflect the debug acknowledge event back from the cores (in the case where an Open-Drain scheme is used externally).

JTAG_MOD 1 JTAG_MOD JTAG_MOD I 3.3V SJC mode selection. This pin is sampled at TRST reset to determine two possible modes for the TAP connection configuration.

JTAG_TCK 11 JTAG_TCK JTAG_TCK I 3.3V Test Clock (TCK). This is used to synchronize the test logic and includes an internal pull-up resistor

JTAG_TDI 7 JTAG_TDI JTAG_TDI I 3.3V Test Data Input (TDI). Serial test instruction and data are received through the test data input (TDI) pin. TDI is sampled on the rising edge of TCK and includes an internal pull-up resistor

JTAG_TDO 5 JTAG_TDO JTAG_TDO O 3.3V Test Data Output (TDO). The serial output for test instructions and data. TDO is tri- stable and is actively driven in the shift- IR and shift-DR controller states. TDO changes on the falling edge of TCK



Signal

Pin No.

Pin Name

iMX6 pad name

Signal

Type

Voltage

Level

Description

JTAG_TMS 9 JTAG_TMS JTAG_TMS I 3.3V Test Mode Select (TMS). This is used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and includes an internal pull-up resistor

JTAG_TRSTB 3 JTAG_nTRST JTAG_TRSTB I 3.3V Test Reset (TRST). This is used to asynchronously initialize the test controller. The TRST pin has an internal pull-up resistor

Table 4-33: External Signals Of SJC

4.22 SONY/PHILIPS DIGITAL INTERFACE (SPDIF) The Sony/Philips Digital Interface (SPDIF) audio block is a stereo transceiver that allows the processor to receive and transmit digital audio.

The following table describes the external signals of SPDIF:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

SPDIF_IN 151 USB_OTG_OC EIM_D21 I 3.3V Input line

25 USB_OTG_ID ENET_RX_ER 3.3V

104 LCD_PWR GPIO_16 3.3V


SPDIF_LOCK 157 CAN1_TX GPIO_7 O 3.3V Lock signal

SPDIF_OUT 31 USB_OTG_PWR_EN EIM_D22 O 3.3V Output line signal

134 ENET_RXD0 ENET_RXD0 3.3V

165 PCIE_RST_B GPIO_17 3.3V


SPDIF_SR_CLK 155 CAN1_RX GPIO_8 O 3.3V SR lock signal

Table 4-34: External Signals Of SPDIF

4.23 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) Universal Asynchronous Receiver/Transmitter (UART) provides serial communication capability with external devices through a level converter and an RS-232 cable or through use of external circuitry that converts infrared signals to electrical signals (for reception) or transforms electrical signals to signals that drive an infrared LED (for transmission) to provide low speed IrDA compatibility.



UART supports NRZ encoding format, RS485 compatible 9-bit data format and IrDA-compatible infrared slow data rate (SIR) format.

The following table describes the external signals of UART1:

Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

UART1_CTS_B

57 UART1_CTS EIM_D19 O

3.3V Clear to send


UART1_DCD_B 62 UART3_RTS EIM_D23 IO 3.3V Data carrier detected

UART1_DSR_B 58 UART3_RXD EIM_D25 IO 3.3V Data set ready

UART1_DTR_B 60 UART3_TXD EIM_D24 IO 3.3V Data terminal ready

UART1_RI_B 64 UART3_CTS EIM_EB3 IO 3.3V Ring indicator

UART1_RTS_B

59 UART1_RTS EIM_D20 I

3.3V Request to send


UART1_RX_DATA

156 CSI0_DAT11 CSI0_DAT11 I

1.8V Serial / infrared data receive

61 UART1_RXD SD3_DAT6 3.3V

UART1_TX_DATA

160 CSI0_DAT10 CSI0_DAT10 O

1.8V Serial / infrared data transmit

63 UART1_TXD SD3_DAT7 3.3V

Table 4-35: External Signals Of UART1


Signal

Pin No.

Pin Name iMX6 pad name

Signal Type

Voltage Level

Description

UART2_CTS_B 52 UART2_RTS EIM_D28

O 3.3V

Clear to send


UART2_RTS_B 50 UART2_CTS EIM_D29

I 3.3V

Request to send


UART2_RX_DATA

54 UART2_RXD EIM_D27 I

3.3V Serial / infrared data receive

155 CAN1_RX GPIO_8 3.3V

107 PCIE_WAKE_B SD3_DAT4 3.3V

UART2_TX_DATA

56 UART2_TXD EIM_D26 O

3.3V Serial / infrared data transmit 157 CAN1_TX GPIO_7 3.3V



Signal

Pin No.


Signal Type

Voltage Level

Description




Signal

Pin No.


Signal

Type

Voltage

Level

Description

UART3_CTS_B

62 UART3_RTS EIM_D23 O

3.3V Clear to send

149 USB_H1_OC EIM_D30 3.3V


UART3_RTS_B

131 3G_PWR_ON EIM_D31 I

3.3V Request to send

64 UART3_CTS EIM_EB3 3.3V

119 HEADPHONE_DET SD3_RST 3.3V

UART3_RX_DATA 58 UART3_RXD EIM_D25 I 3.3V Serial / infrared data receive

UART3_TX_DATA 60 UART3_TXD EIM_D24 O 3.3V Serial / infrared data transmit



Signal

Pin No.

Pin Name

iMX6 pad name Signal Type

Voltage Level

Description

UART4_CTS_B 140 CSI0_DAT17 CSI0_DAT17 O 1.8V Clear to send

UART4_RTS_B 142 CSI0_DAT16 CSI0_DAT16 I 1.8V Request to send

UART4_RX_DATA 150 CSI0_DAT13 CSI0_DAT13 I 1.8V Serial /

infrared data receive 201 KEY_ROW0 KEY_ROW0 3.3V

UART4_TX_DATA 154 CSI0_DAT12 CSI0_DAT12 O 1.8V Serial /

infrared data transmit






Signal

Pin No.

Pin Name

iMX6 pad name

Signal Type

Voltage Level

Description

UART5_CTS_B 136 CSI0_DAT19 CSI0_DAT19 O 1.8V Clear to send


UART5_RTS_B 138 CSI0_DAT18 CSI0_DAT18 I 1.8V Request to send


UART5_RX_DATA 144 CSI0_DAT15 CSI0_DAT15 I 1.8V Serial / infrared data receive


UART5_TX_DATA 148 CSI0_DAT14 CSI0_DAT14 O 1.8V Serial / infrared data transmit



4.24 UNIVERSAL SERIAL BUS CONTROLLER (USB) The USB controller block provides high performance USB functionality that conforms to the Universal Serial Bus Specification, Rev. 2.0, and the On-The-Go and Embedded Host Supplement to the USB Revision 2.0 Specification.

The following table describes the external signals of USB:

Signal Pin No.


Signal Type

Voltage Level

Description

USB_H1_DN 21 USB_HOST_DN USB_H1_DN IO DN host 1 signal

USB_H1_DP 23 USB_HOST_DP USB_H1_DP IO DP host 1 signal

USB_H1_OC

149 USB_H1_OC EIM_D30 I

3.3V Host 1 external input for VBUS overcurrent detection

108 I2C3_SCL GPIO_3 3.3V

USB_H1_PWR

131 3G_PWR_ON EIM_D31 O

3.3V To control power

switch to supply

VBUS voltage 182 GPIO_0_CLKO GPIO_0 3.3V

USB_H1_PWR_CTL_WAKE 191 KEY_COL2 KEY_COL2 3.3V -

USB_OTG_DN 29 USB_OTG_DN USB_OTG_DN IO DN OTG signal

USB_OTG_DP 27 USB_OTG_DP USB_OTG_DP IO DP OTG signal



Signal Pin No.


Signal Type

Voltage Level

Description

USB_OTG_HOST_MODE 157 CAN1_TX GPIO_7 3.3V -

USB_OTG_ID 25 USB_OTG_ID ENET_RX_ER

I 3.3V

ID signal

130 CODEC_PWR_EN GPIO_1 3.3V

USB_OTG_OC

151 USB_OTG_OC EIM_D21 I

3.3V OTG external input for VBUS overcurrent detection


USB_OTG_PWR

31 USB_OTG_PWR_EN EIM_D22 O

3.3V To control power switch to supply VBUS voltage 177 KEY_ROW4 KEY_ROW4 3.3V

USB_OTG_PWR_CTL_WAKE 155 CAN1_RX GPIO_8 3.3V -

Table 4-40: External Signals Of USB

4.25 ULTRA SECURED DIGITAL HOST CONTROLLER (USDHC) The Ultra Secured Digital Host Controller (uSDHC) provides the interface between the host system and the SD/SDIO/MMC cards.

The uSDHC acts as a bridge, passing host bus transactions to the SD/SDIO/MMC cards by sending commands and performing data accesses to/from the cards.

It handles the SD/SDIO/MMC protocols at the transmission level.

The following table describes the external signals of USDHC2:

Signal Pin

No.


Signal

Type

Voltage

Level

Description

SD2_CD_B 53 KEY_VOL_UP GPIO_4 I 3.3V Card detection pin If not used (for the embedded

memory),tie low to indicate there is a card attached.

SD2_CLK 22 SD2_CLK SD2_CLK O 1.8V Clock for MMC/SD/SDIO card

SD2_CMD 24 SD2_CMD SD2_CMD IO 1.8V CMD line connect to card

SD2_DATA0 20 SD2_DATA0 SD2_DAT0

IO 1.8V DATA0 line in all modes

Also used to detect busy state

SD2_DATA1

18 SD2_DATA1 SD2_DAT1 IO

1.8V DATA1 line in 4/8-bit mode Also used to detect interrupt in 1/4-bit mode


IO 1.8V DATA2 line or Read Wait in 4-bit mode

Read Wait in 1-bit mode

SD2_DATA3


1.8V DATA3 line in 4/8-bit mode or configured as card detection pin May be configured as card detection pin in 1-bit mode



Signal Pin

No.


Signal

Type

Voltage

Level

Description

SD2_DATA4 12 SD2_DATA4 NANDF_D4

IO 3.3V DATA4 line in 8-bit mode, not

used in other modes



used in other modes



used in other modes


IO 3.3V DATA7 line in 8-bit mode,

not used in other modes

SD2_LCTL

106 I2C3_SDA GPIO_6 O

3.3V LED control used to drive an external LED Active high Fully controlled by the driver Optional output

SD2_VSELECT

195 KEY_ROW1 KEY_ROW1 O

3.3V IO power voltage selection signal


KEY_ROW2 3.3V

SD2_WP

167 PCIE_DIS_B GPIO_2 I

3.3V Card write protect detect If not used(for the embedded memory), tie low to indicate it's not write protected.

Table 4-41: External Signals Of uSDHC2

The following table describes the external signals of USDHC3:

Signal Pin

No.


Signal

Type

Voltage

Level

Description

SD3_CLK 47 SD3_CLK SD3_CLK O 3.3V Clock for MMC/SD/SDIO card

SD3_CMD 49 SD3_CMD SD3_CMD IO 3.3V CMD line connect to card


IO 3.3V DATA0 line in all modes

Also used to detect busy state

SD3_DATA1


3.3V DATA1 line in 4/8-bit mode Also used to detect interrupt in 1/4-bit mode


IO 3.3V DATA2 line or Read Wait in 4-bit mode

Read Wait in 1-bit mode

SD3_DATA3 39 SD3_DATA3 SD3_DAT3 IO 3.3V DATA3 line in 4/8-bit mode or configured as card detection pin May be configured as card detection pin in 1-bit mode

SD3_DATA4 107 PCIE_WAKE_B SD3_DAT4

IO 3.3V DATA4 line in 8-bit mode, not used in

other modes



other modes

SD3_DATA6 61 UART1_RXD SD3_DAT6


other modes



Signal Pin

No.


Signal

Type

Voltage

Level

Description

SD3_DATA7 63 UART1_TXD SD3_DAT7


other modes

SD3_RESET 119 HEADPHONE_

DET SD3_RST

O 3.3V

Card hardware reset signal, active LOW

SD3_VSELECT 112 DISP_PWR_EN NANDF_CS1

O 3.3V IO power voltage selection signal

Table 4-42: External Signals Of uSDHC3

4.26 WATCHDOG TIMER (WDOG) The Watchdog Timer (WDOG) protects against system failures by providing a method by which to escape from unexpected events or programming errors.

Once the WDOG is activated, it must be serviced by the software on a periodic basis. If servicing does not take place, the timer times out. Upon timeout, the WDOG asserts the internal system reset signal, WDOG_RESET_B_DEB to the System Reset Controller (SRC).

The following table describes the external signals of WDOG:

Signal Pin

No.


Signal

Type

Voltage

Level

Description

WDOG1_B 121 KEY_COL6_MICROPHONE_DET GPIO_9

IO 3.3V This signal

will power down the chip.

186 CSI_PWN SD1_DAT2 1.8V

WDOG1_RESET_B_DEB 186 CSI_PWN SD1_DAT2

O 1.8V This signal

is a reset source for the chip.

Table 4-43: External Signals Of WDOG

4.27 CRYSTAL OSCILLATOR (XTALOSC) This block comprises both the 24 MHz and 32 kHz implementation of a biased amplifier that when combined with a suitable external quartz crystal and external load capacitors, implements an oscillator.

The following table describes the external signals of XTALOSC:

Signal

Pin No.


Signal Type

Voltage Level

Description

XTALOSC_CLK1_N 161 CLK1_N CLK1_N O 2.5V Negative differential clock

XTALOSC_CLK1_P 159 CLK1_P CLK1_P O 2.5V Positive differential

clock

XTALOSC_OSC32K_32K_OUT 134 ENET_RXD0 ENET_RXD0 O 3.3V -




Signal

Pin No.


Signal Type

Voltage Level

Description

188 CSI_RST_B SD1_CLK 1.8V

XTALOSC_REF_CLK_24M 108 I2C3_SCL GPIO_3 O 3.3V 24MHz reference clock

XTALOSC_REF_CLK_32K 155 CAN1_RX GPIO_8 O 3.3V 32KHz reference clock

Table 4-44: External Signals Of XTALOSC

4.28 10/100/1000-MBPS ETHERNET (ENET) The ENET is connect from AR8031, the AR8031 is Atheros’ 4th generation, single port, 10/100/1000

Mbps, Tri-speed Ethernet PHY which compliant with the IEEE802.3-2002 standard.

The following table describes the external signals of ENET:

Signal Pin No.

Pin Name

iMX6 pad name Signal Type

Voltage Level

Description

TXRXN_D

73

TXRXN_D From AR8031_TXRXN3

I/O

- Media-dependent interface 3, differential 100ohm transmission line

TXRXP_D

75

TXRXP_D From AR8031_TXRXP3

I/O


TXRXN_C

77

TXRXN_C From AR8031_TXRXN2

I/O


TXRXP_C

79

TXRXP_C From AR8031_TXRXP2

I/O


TXRXN_B

81

TXRXN_B From

AR8031_TXRXN1

I/O


TXRXP_B

83

TXRXP_B From

AR8031_TXRXP2

I/O


TXRXN_A

85

TXRXN_A From

AR8031_TXRXN0

I/O


TXRXP_A

87

TXRXP_A From AR8031_TXRXP0

I/O


LED_ACT

89

RGMII_LED_ACT

From AR8031

LED_ACT

I/O

3.3V

Parallel LED output for 10/100/1000 BASE-T activity; active high. See note 1

LED_1000

91

RGMII_LED_1000

From AR8031

LED_LINK1000

I/O

3.3V

Parallel LED output for 1000 BASE-T link, active high. See note 1

LED_10_100

93

RGMII_LED_10_100

From AR8031 LED_LINK10_100

I/O

3.3V

Parallel LED output for 10/100 BASE- T link, active high.

See note 1

Table 4-45: External Signals Of ENET



Note 1: LED Status

Signal 10M Link 10M Active 100M Link 100M Active 1000M Link 1000M Active

LED_ACT Active Blink Active Blink Active Blink

LED_1000 Inactive Inactive Inactive Inactive Active Active

LED_10_100 Inactive Inactive Active Active Inactive Inactive

Table 4-46: LED Status



5 ELECTRICAL SPECIFICATION

5.1 ABSOLUTE MAXIMUM CHARACTERISTICS Minimum Maximum Unit

Main Power Supply, DC-IN -0.3 5.5 V

Table 5-1: Absolute Maximum Characteristics

5.2 OPERATIONAL CHARACTERISTICS

5.2.1 Power Supplies The VS8100 SOM is designed to be driven with a single +5V input power from SO-DIMM connector.

Power Suppliers Requirement

Minimum Typical Maximum Unit

Voltage of Input Power 4.76 5.0 5.25 V

Current of Input Power 2 A

Table 5-2: Power Supply Requirement

5.2.2 Power Consumption The VS8100 SOM power consumption is measured while running different power scripts under Android 4.2.2.

No. Power Script Power Script Operation Imax(A) @ 5.0V Input

1 Power Script 1 LVDS – Scrolling the ‘H’ pattern

Audio – Run MP3 file on audio out

USB – Keyboard and Mouse

0.82A (Dual core)

0.83A (Quad core)

2 Power Script 2 HDMI – Scrolling the ‘H’ pattern

LVDS – Scrolling the ‘H’ pattern

Audio – Run MP3 file on audio out

Ethernet – Ping test

USB – Transfer the files between USB and MicroSD

1.32A (Dual core)

1.46A (Quad core)

3 Standby OS is in idle mode 0.046A (Dual core)

0.055A (Quad core)

Table 5-3: Power Consumption



Note: Power consumption is measured in particular condition and it may vary platform to platform based on board configuration. Depending upon board configuration, overall system design and cooling mechanism, customer may need to choose the appropriate heat solution.



6 ENVIRONMENTAL SPECIFICATION

6.1 TEMPERATURE SPECIFICATION The VS8100 SOM has 3 product variants with operating temperature from 5℃to 50℃ and storage temperature from -20℃ to 70℃. For detail, please refer to Section 8 Board Options.

6.2 HUMIDITY • Operating: 10% to 90% (Non-condensing)

• Non-operating: 5% to 95% (Non-condensing)



7 MECHANICAL SPECIFICATION

7.1 MODULE DIMENSION • 68mm x 60mm

7.2 HEIGHT ON TOP • Maximum 3.0mm (without printed circuit board)

• Height is depending on (optional) CPU cooler/heat spreader

7.3 HEIGHT ON BOTTOM • Maximum approximately 1.3mm (without printed circuit board)



7.4 MECHANICAL DIMENSION

Figure 7-1: Top View

Figure 7-2: Bottom View



8 BOARD OPTIONS

Part No. CPU CPU Grade DDR3 eMMC Operating Temperature

Storage Temperature

VS601DAC20 i.MX 6Dual, 1.0GHz Commercial 1GB 4GB 5°C to 50°C -20°C to 70℃

VS601QAC42 i.MX 6Quad, 1.0GHz Commercial 4GB 16GB 5°C to 50°C -20°C to 70℃

VS601QAC20 i.MX 6Quad, 1.0GHz Commercial 1GB 4GB 5°C to 50°C -20°C to 70℃

Table 8-1: VS8100 SOM Ordering Part Numbers

Customization options are available. Please contact your sales representative for more information.



9 REVISION HISTORY

Version Date Released Changes

1.0 23 FEB 2016 Initial Release

A 29 MAR 2016 First Official Release



10 LEGAL NOTICES

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Testing and other quality control techniques are used to the extent that APC deems necessary to support its warranty.

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