vol. 93/mar. 2001 - mitsubishi electric · 2020. 2. 18. · vol. 93/march 2001 mitsubishi electric...

Submarine OpticalCable System

ATM Network

Long-haulOptical Receiver

ISSN 1345-3041

VOL. 93/MAR. 2001

MITSUBISHIELECTRIC

ATM Edition

● Vol. 93/March 2001 Mitsubishi Electric ADVANCE

A Quarterly Survey of New Products, Systems, and Technology

TECHNICAL REPORTSScope of ATM Network System ......................................................... 1by Katsuaki Kikuchi

ATM Cross Connect System .............................................................. 6by Hiroyoshi Inoue

ATM Access System UsingAPON Technology ............................................................................... 8by Hiroyuki Ueda

New Products SupportIP-over-ATM Network System .......................................................... 10by Keiichi Edahiro

R&D PROGRESS REPORTSATM Traffic Control for Guaranteed QoS ......................................... 12by Tetsuya Yokotani

New LSI Chips Provide ATM Termination, OAM Processing andTraffic Control for Broadband Communications ............................. 16by Kazuumi Koguchi & Seiji Kozaki

Devices for ATM Fiber Optics Communication ............................... 20by Shin-ichi Kaneko

CONTENTS

Mitsubishi Electric Advance is published online quarterly (in March, June, September,and December) by Mitsubishi ElectricCorporation.Copyright © 2001 by Mitsubishi ElectricCorporation; all rights reserved.Printed in Japan.

Cover StoryOur cover illustrates how MitsubishiElectric has taken the concept of IP overATM over photonics as the basis for thebackbone of next-generation Internetcommunications, and is developing therelated ATM network systems and thenecessary IP communication equipmentand optical devices.

Kiyoshi Ide

Haruki NakamuraHiroo FujikawaKeizo HamaKazunori SasakiMasao HatayaHiroshi MuramatsuTakashi ItoMasatoshi ArakiHiroaki KawachiHiroshi KayashimaTakao YoshiharaOsamu MatsumotoKazuharu Nishitani

Yasuo Tobita

Keizo HamaCorporate Total Productivity Management& Environmental ProgramsMitsubishi Electric Corporation2-2-3 MarunouchiChiyoda-ku, Tokyo 100-8310, JapanFax 03-3218-2465

Yasuhiko KaseGlobal Strategic Planning Dept.Corporate Marketing GroupMitsubishi Electric Corporation2-2-3 MarunouchiChiyoda-ku, Tokyo 100-8310, JapanFax 03-3218-3455

Editor-in-Chief

Editorial Advisors

Vol. 93 Feature Articles Editor

Editorial Inquiries

Product Inquiries

ATM Edition

· 1March 2001

TECHNICAL REPORTS

This article describes the system architectureand features of the ATM backbone network thatwill provide the multimedia communicationsunderpinning the next-generation Internet. Italso describes the new service network that isbuilt into the ATM backbone network.

Issues Facing the Next-GenerationTelecommunications NetworkThe Internet has experienced explosive growthsince it began commercial services in NorthAmerica in the 1980s and now handles not onlydata traffic but also traffic for applications suchas telephone, video, and entertainment softwarethat require responses in near real time. In thefuture, we can anticipate application of theInternet to electronic commerce, and remoteeducation and medical treatment, requiring fur-ther advances in the Internet as the foundationfor service industries requiring even higher lev-els of real-time responsiveness and reliability.This new Internet will have major repercussionson existing communications networks, andqualitative and quantitative changes in traffic,increases in access speed, redesign of commu-nications billing systems and the like includeelements that will dramatically change the struc-ture of conventional telecommunications net-works. One of the critical issues facing networkoperators is that of providing cost effective net-work capability sufficient for the explosivegrowth in demand for data traffic while still pro-viding the quality of service that will set themapart from other firms. If they are to succeed inthese ends, the network operators will have tomake a critical decision about the type of archi-tecture to use in the next-generation network.The choice of whether to create a new networkinfrastructure centering on IP services, orwhether to evolve from the existing networksfocusing on multiple services including existingservices, is also critical.

In order to respond to the rapid growth of high-speed/wide-band communications accompany-ing increasing use of multimedia applications,the major network operators (including NTT)are pushing to move to integrated/backbonenetworks using ATM communications technol-

*Katsuaki Kikuchi is with Communication Systems R&D Center.

by Katsuaki Kikuchi*

Scope of ATM Network System

ogy. ATM communications technology has thebenefits of (1) uniformly handling multimediadata of all different speeds, (2) high-speed non-hierarchical multiplexing/switching, (3) superiorcontrol of the quality of service, etc, making itpossible to structure an ATM backbone networkthat will integrate the handling of the multime-dia communications services of the future. Innetworks that handle data traffic, network inte-gration using ATM communications technolo-gies will be particularly useful because therequirements for communications quality differdepending on the type of data handled.

Mitsubishi Electric has been championingtechnology development from a global perspec-tive taking the latest market trends into ac-count, and even in the coming age of IP-centriccommunications, the corporation wants to besure that it continues to provide the optimalvalue-adding solution.

With the basic concept behind the next-gen-eration network structure being “IP over ATMover photonics and wireless,” the developmentof the backbone network and of the next-gen-eration Internet will provide the foundation forthe creation and development of new commu-nications markets.

Next-Generation Communications NetworkArchitectureResearch is underway worldwide on a variety ofissues related to network architecture, issuessuch as reliability, safety, and quality — in addi-tion to higher access speeds — allowing thenetwork of today to become the foundation forsocial and economic activities in the future. Onecritical area of research is the form that the IPtelecommunications infrastructure should take.The critical debates around this issue focus onthe following (see Fig. 1):

● IP over asynchronous transfer mode (ATM)● IP over synchronous digital hierarchy (SDH)● IP over wavelength division multiplexing

(WDM)

In terms of the general characteristics, fromthe perspective of the communications network

TECHNICAL REPORTS

Mitsubishi Electric ADVANCE2 ·

TECHNICAL REPORTS

structure, IP over WDM, which has the simplestprotocol stack, has the potential for the great-est network cost reductions, while the IP overATM approach would be useful in providing so-phisticated network services such as virtual pri-vate networking (VPN) because of its excellentcontrol capabilities.

Communications network cost reductions willbe critically important in the future, and the sim-plification of network structures is essential. Akey to these simplified structures will be to jet-tison the current multiplexing structures thatare based on SDH. The essence of the ATM tech-nology is non-hierarchical multiplexing, whichdoes not require SDH multiplexing structures.Note that this approach is not in conflict withthe approach of creating ATM network struc-tures. If we reexamine the protocol stack fromthis perspective, the protocols can be summa-rized as shown in Fig. 2. The future of IP overWDM is a focus of current research, where theoptions at this point are:

● IP/ATM/STM Frame/WDM● IP/PPP/STM Frame/WDM

Fig. 1 Issues to be resolved in the backbone network.

These are compared in Fig. 3. IP over WDMhas benefits in terms of transmission efficiency,while IP over ATM has benefits in terms of thecontrol of quality of service and in terms of net-work services. However, it is essential to in-crease the speed of access for the Internet ofthe future, and because the application of ATMtechnology is anticipated to be important in thefuture of access systems, IP over ATM is a supe-rior solution from the perspective of access sys-tem compatibility.

ATM Backbone NetworksATM system services such as “megalink ser-vices” (which are ATM leased-line services),“shared link services” and “cell relay services”(which are forms of ATM switching services) areexpanding steadily. In Japan, NTT is promotingthe construction of an ATM backbone networkas the shared foundation for these services,where, as shown in Fig. 4, this ATM backbonenetwork will comprise an ATM switching sys-tem (which has virtual path/virtual channel(VP/VC)) handling functions, an ATM cross-con-nect system (which has VP handling functions),

KEYPPP Point-to-Point ProtocolSDL Simple Data Link

IP over ATM IP over WDM IP over SDH

L3

L1

L2

IP

IP

IP

AAL5

TC, VP/VC

VC VCSDH SDH

ATM

Section management Section management

Optical fiber (WDM) Optical fiber (WDM) Optical fiber (WDM)

PPP

SDL (?)

Section management (?)

High Low

High Low

Network Cost

Control Capability (QoS etc)

· 3March 2001

TECHNICAL REPORTS

Fig. 2 Protocol structure for backbone network simplification.

and an ATM access system (which provides in-tegrated access functions for the various ser-vices) in a structure with the three-part networkelement (NE), NE-OpS, and network-OpS (NW)-OpS structure.

THE ATM CROSS-CONNECT SYSTEM. The basicfunction of the ATM cross-connect system is ef-

ficient VP setup, and in the network it has therole of providing the structure of VP bundledwith VC on the network and providing the struc-ture that supplies direct-connect VP between endusers. This equipment has a system configura-tion that is easily scalable, is able to provide ahigh-speed ATM interface, and makes it possibleto structure an ATM backbone network eco-nomically.

ATM ACCESS SYSTEMS. These can transmit allspeeds of signals efficiently while providing in-dispensable cost reductions, and there are callsfor it to become the integrated access platformfor all types of services.

The ATM-passive optical network (PON) tech-nology, which is becoming the international stan-dard in, for example, full service access networks(FSANs), is used to reduce the cost of accesssystems. This technology is equipped with so-phisticated traffic control functions for support-ing a variety of quality-of-service classes.

Next-Generation IP NetworksFig. 5 shows the structure of the next-genera-tion IP network conceived by Mitsubishi Elec-tric. Faster access speeds will be important inthe next-generation Internet, and there is theFig. 3 IP over ATM vs. IP over WDM.

STM Frame

IP over ATM IP over WDM

WDM

PPP

STM Frame

WDM

SDL(?)

New Frame

WDM

ProcessingProcessingNodeNode

WWDDM

WWDDM

(New protocol)

ATMAAL5

TC,VP/VC

Network Cost Reduction : Directly linked to high capacity processing nodes and highcapacity transmission paths.

WDM transmission path (2.4 GxN signals)

WDM transmission path (2.4 GxN signals)

Intra-office IF(2.4Gbps)

Intra-office IF(2.4Gbps)

Eliminate the SDH (multiplexed structure) and use the STM frame as the section control function.

(Existing protocols)


TECHNICAL REPORTS

Relay Network (VP/VC processing)

ATM Switch System

ATM Switch System

ATM XC System ATM XC System

Relay Network (VP processing)

ATM Access System

ATM Access System

Access Network Access Network

ONU ONU ONU ONU ONU ONU ONU ONU

OLT OLT OLT OLT

NW-OpS

NE-OpS

NE-OpS

NE-OpS

Fig. 4 ATM backbone network structure.

NA

NA

AAL5

AAL5

AAL5ADP ADP

NA

NA

AAL5

AAL5

AAL5

Edge Node

Core Node Core Node

Edge Node

Edge Node

Edge Node

Service Server

Seamless Transmission Using ATM Cells

IP Core Network

IP/ATM/Photonics

ATM Access System

ATM Access System

ATM Access System

STM Access System

STM Access System

ATM Access System

Label switch router based

on ATM switching

Fig. 5 Next-generation IP network concept.

· 5March 2001

TECHNICAL REPORTS

potential for a variety of different access meth-ods, such as fiberoptic access, metallic access,and wireless access to provide the faster access.However, ATM technology is central, and inte-grated access to IP services and ATM-systemservices (which will be at the heart of the high-speed/wide-band services of the future) is now areality. The IP core network will be structuredon the ATM backbone network, and will beequipped with core nodes and edge nodes struc-tured from label switch routers (LSRs) that haveIP packet routing functions. Furthermore, it islikely that a variety of service servers, such asgateway servers and policy servers, will be nec-essary as a result of the development of a vari-ety of services in the future.

Not only will the IP core network need to pro-vide minimal delay times and high throughputsthrough high-speed cut-through transmission,but will also have to provide a variety of quality-of-service levels. This architecture can provideseamless transmission using end-to-end ATMcells, and can provide for variety in QoS.

Even though the GMN-CL, proposed by NTT,uses as its core protocol a base of IPv6 in the IPcore network, the use of MPLS in the futurelooks promising.

Whatever choices are made, the next-genera-tion communications network centering on IPwill need to make steady progress, whereMitsubishi Electric feels that it will be criticalto continue to provide products with high levelsof added value, and to continue to respond tothe requests of its customers.❑

TECHNICAL REPORTS


Mitsubishi Electric Corporation has developeda large-capacity ATM cross-connect system(ATM-XC) supporting ATM backbone networks.Its role is to distribute multiplexed virtual paths(VPs) by destination.

The ATM-XC, which connects to ATM switch-ing systems (ATM-SW) and ATM access systems(ATM-OLT), achieves a maximum throughputof 20Gbps. With intra-office and inter-office in-terfaces of 150Mbps, 600Mbps and 2.4Gbps, ithas functions for multiplexing, demultiplexingand routing across interfaces in VP units.

FeaturesMajor features of the new ATM cross-connectsystem include its high throughput, scalabilityand reliability. It incorporates large-capacity

*Hiroyoshi Inoue is with Communication Systems Business Division.

by Hiroyoshi Inoue*

ATM Cross Connect System

Fig. 1 A typical ATM backbone network.

ATM switch circuits to realize throughput of upto 20Gbps. It expands readily from the basicconfiguration of two upper units (sub-racks), witheach cabinet housing up to four units. The trans-mission capacity can be enhanced in2.4Gbps steps by adding one MUX block whichmultiplexes and demultiplexes signals from/to16 × 150Mbps interfaces.

Examples of the interfaces accommodated perunit are given below:

● 150Mbps interfaces: 128 single (all-simplex),64 sets (all-duplex)

● 600Mbps interfaces: 32 single (all-simplex),32 sets (all-duplex)

● 2.4Gbps interfaces: 8 single (all-simplex),8 sets (all-duplex)

ATM-OLT

ATM-OLT

Inter-office transport line Inter-office transport line

150M, 600M(40km/80km)

SDH network SDH network

150M(400m), 600M(2km)

150M, 600M, 2.4G(40km/80km)

150M(400m), 600M, 2.4G(2km)

ATM-SW

ATM-SW

Other ATM- XC

Data communication network

Q3-IF

KEYNW-OpS Network-Operations System NE-OpS Network Element-Operations System

NE-OpS NE-OpS

TECHNICAL REPORTS

· 7March 2001

A redundant configuration is adopted for highreliability, featuring 1+1 MS protection and VPprotection.

VP-OAM functions are provided for alarmtransfer, performance monitor, loopback test andcontinuity characteristics measurement. Re-mote operation, administration and maintenanceis possible from an NE-OpS. By storing opera-tions data in backup memory, the system canrestart itself automatically after a power off orwhen a package is replaced.

In addition, the latest semiconductor-devicetechnology is applied to achieve high integra-tion and low power dissipation.

Fig. 2 ATM-XC device configuration.

Fig. 3 Appearance of the ATM-XC.

The corporation is committed to developing anongoing series of subsystems that will supportthe smooth upgrade of ATM services, which aresure to power many of the burgeoning needs ofthe information oriented society.❑

FAN UNITCLOCK

MUX

IF

IF

IF

IF

MUX

CLOCK

CONT

MUX

IF

IF

IF

IF

MUX

CLOCK

CONT

MUX

IF

IF

IF

IF

MUX

FAN UNITCLOCK

CONT

MUX

IF

IF

IF

IF

MUX

CLOCK

CONT

MUX

IF

IF

IF

IF

MUX

CLOCK

CONT

MUX

IF

IF

IF

IF

MUX

FFTU

ATM

SW

CONT

CONT

KEYCLOCK Clock blockCONT Control and supervisory blockATM-SW ATM switch blockMUX Multiplexing and demultiplexing blockIF Interface blockFFTU Fuse/Filter/Terminal Unit

TECHNICAL REPORTS


Mitsubishi Electric Corporation has developedan ATM access system for the North Americanmarket, applying ATM passive optical network(APON) technology based on interna-tional standards given in the International Tele-communication Union (ITU-T) recommenda-tions.

By running optical fiber lines to corporate of-fices fiber to the business (FTTB) or to ordinaryhouseholds fiber to the home (FTTH) and apply-ing APON technology with this system, it ispossible to replace the existing synchronoustransfer mode (STM) channels serving large num-bers of subscribers and provide fast, high-qual-ity Internet services economically.

Features of the units making up the accesssystem are outlined below:

1. ATM-OLT (product name: ADS2000)● Interfaces: DS-3 (45Mbps), OC-3c 155Mbps,

APON 155Mbps● Slot-free card configuration: Cards can be

mounted in any slot.● Front access optical interfaces● Economical: One APON-155M-IF connects to

*Hiroyuki Ueda is with Communication Systems Business Division.

by Hiroyuki Ueda*

ATM Access System UsingAPON Technology

Fig. 1 ATM Access System configuration

as many as 32 ATM-ONT units at the sametime, with the total 150Mbps bandwidth allo-cated freely to each ONT.

● Highly reliable: A duplex configuration isadopted for the ATM switch, clock and con-troller modules.

Fig. 2 Cabinet appearance

KEYATM Asynchronous Transfer Mode DSU Digital Service UnitFSAN Full Service Access Network ADS ATM Distribution SwitchONT Optical Network Terminal PBX Private Branch ExchangeAPON ATM Passive Optical Network OLT Optical Line TerminalSTM Synchronous Transfer Mode

ATMNetwork

OC-3c (155Mbps)

ATM-OLT(ADS2000)

STMNETWORK

ElementManager

DS-3(45Mbps)

APON (155Mbps)

APON(155Mbps)

OC-3c (155Mbps) OC-3c (155Mbps)

DS-1 CE (1.5Mbps)10/100 Base-T

10/100 Base-T

DS-1 CE (1.5Mbps)

10 Base-T

PBX

LocalAreaNetwork

ATM-DSU

ATM-ONT

ATM-ONT

ATM-ONT

StarCoupler

10 Base-T

TECHNICAL REPORTS

· 9March 2001

● Mounts in the North American specification23-inch-wide cabinet.

● One system/one unit (sub-rack) configuration.

Fig. 3 ADS2000 appearance

Fig. 4 AONT-B200 appearance

2. ATM-ONT (product name: AONT-B200)● Access line interface: APON 155Mbps● User-network interface: One or any two of

the following interfaces;10/100 Base-T, DS1-CE (1.5Mbps circuitemulation), or ATM155Mbps (to be developed)

3. Element Manager (product name: ISEM)● Capable of remote system operation, admin-

istration and maintenance.● Equipped with a Java-based user-friendly

graphical user interface (GUI) for easy, intui-tive operation.❑

TECHNICAL REPORTS


*Keiichi Edahiro is with Communication Systems Business Division.

by Keiichi Edahiro*

New Products SupportIP-over-ATM Network System

Mitsubishi Electric Corporation has developedthree new products for internet protocol (IP)networks based on ATM technology, meetingthe accelerating trend toward the use of IP net-working for data communications traffic. Asillustrated in Fig. 1, the next-generation IPnetwork system, employing IP over ATM, hasan ATM backbone network as the lower layer,with the upper layer consisting of IP transportnetwork edge nodes connecting to ATM routersin the access network, and a network gatewayproviding IP gateway services.

The newly developed systems and their fea-tures are introduced here.

EDGE NODE. The role of the IF-2000 edge nodeis to connect the access network with the corenetwork (see Fig.2).● The IF2000 was developed to realize high

transport capability, incorporating a hardware-based high-speed address search engine. Ableto complete address searches within one cellduration time, it features high throughput not

Fig. 1 Configuration of the IP Network System

only for long-packet streams but also for short-packet streams.

● High security is achieved without a crypto-graphic system by mapping each subscriber’svirtual channel (VC) to the closed user group(CUG) to which it belongs.

● As traffic control technology, not only best-effort service is supported but also threeclasses of IP-level priority control, enablingvarious service quality classes to be offered.

MITSUBISHI NETWORK GATEWAY. The MX-8000network gateway was developed for connectionsbetween different CUGs or between CUGs andthe Internet.● One unit can handle as many as 256 CUGs.● As address conversion methods it supports Bi-

directional NAT, Basic NAT and NAPT. Anycombination of these methods can be appliedto each CUG.

● Large-scale IP flow handling is provided, withas many as 130,000 address conversion tableentries for application to large-lot customers.

IP over ATM

ATM Access NetworkATM Transport Network

IP Transport Network

PC PC PC PC

IPIP IP IP

IP Gate way Services

Global Network(Internet)

IP Layer

ATM Layer

Network Gate Way (MX- 8000)

ATM Backbone Network

Edge Node (IF2000)

ATM Router

Edge Node (IF2000)

ATMXC

ATMXC

ATMOLT

ATMOLT

ATM- ATM-ONT

ATM Router

ATM Access NetworkATM Access Network ATM Transport Network

IP Transport NetworkPC PC PC PC

IPIP IP IP

IP Gateway ServicesIP Layer

Edge Node (IF2000)

ATM Router

Edge Node (IF2000)

ATMXC

ATMXC

ATMOLT

ATMOLT

ATM Router

ATM-ONT

ATM-ONT

ATM-ONT

ATM-ONT

KEYOLT Optical Line Terminal ONT Optical Network Terminal XC Cross Connect

Network Gateway (MX-8000)

TECHNICAL REPORTS

· 11March 2001

● Different packet filtering conditions can beset for each CUG, namely, by IP address, byport number, or by connection destination.

● Maximum packet transfer capability of120Mbps is achieved by means of cut-throughprocessing involving both software and hard-ware.

● The small size of this unit means it can beimplemented on a platform with a PC server,and can also be operated as an all-in-one sys-tem including the operation, administrationand management functions.

ATM ROUTER. The MR25 ATM router, see Fig.3, connects a user’s LAN (10Base-T) to an ATMleased line service (ATM 25Mbps).● Packet transfer control is achieved by identi-

fying each IP flow and mapping to a VC orchannel in packet units.

● Fine control of QoS (quality of service) on ATMis supported, including functions for minimumguaranteed bandwidth per VC, and bandwidth-designated CLP 0/1 cell tagging.

● Bandwidth control of multiple virtual chan-

Fig. 2 IF2000 configuration

nels defined between multiple VCs or withina VC, priority control, and congestionchangeover functions are also provided.

● Shaping is supported per VC, VP, or VC group.

IP networks based on ATM technology promiseto play an increasingly important role in datacommunications traffic. These three new prod-ucts demonstrate the corporation’s ability toanticipate next-generation network needs. ❑

Fig. 3 ATM Router (MR25)

KEYAS Address SearchingM MulticastS ShaperSLT Subscriber Line Terminal O/E Optical/Electrical converterEMS Element Management SystemNW-OpS Network Operations System

CORE-IFSLT-IF

S M

CLOCK CONT BWS

ATM155MbpsIP v 4

E/O E/O

SAS

AS

O/E O/ESLT-IF

CoS

CoS

ATM -SW

AS

AS

M

ATM155MbpsCore Protocol

EMS

NW-OpS

R & D PR O G R E S S R E P O R T S


*Tetsuya Yokotani is with the Information Technology R&D Center.

by Tetsuya Yokotani*

ATM TrafficControl forGuaranteed QoS

Traffic control technology for guaranteeingeach of the offered quality of service (QoS) classesis an important part of ATM networking tech-nologies. This article presents the QoS-relatedrequirements in an ATM network and discussestraffic control for guaranteeing QoS. It thendescribes technology for implementing thiscontrol in an ATM access system.

QoS requirements in an ATM networkQoS in an ATM network is defined in ITU-Trecommendation I.356 and in the ATM Forum“Traffic Management Specification” Ver. 4.0/4.1. [1]

Today there is broad support for both of these speci-fications. Features of the main QoS classes stipu-lated by the ATM Forum are shown in Table 1.

Functions for guaranteeing QoSThe functions for QoS guarantee are shown inFig. 1.

CONNECTION CONTROL IN ADVANCE. Beforesetting up a new connection, the ATM networkfirst determines whether it has the resources tomeet the customer’s requirements, using con-nection admission control (CAC) functions. If

Table 1 QoS classes

CBR (Constant Bit Rate) Delay, cell discard rate, and delayvariation guaranteed

rt-VBR (Real Time Variable Delay, cell discard rate, andBit Rate) delay variation guaranteed

nrt-VBR (Non Real TimeCell discard rate guaranteed

Variable Bit Rate

GFR (Guaranteed Frame Rate) Minimum bit-rate guaranteed, andpacket-level discard control

ABR (Available Bit Rate) Minimum bit-rate guaranteed, andcell-level flow control

UBR (Unspecified Bit Rate) No quality specified

Fig. 1 Deployment of functions for QoS guarantee

CAC

NodeUser

Operator Management element

(b) Control functions during a call

(a) Pre-connection control functions

Node NodeUser

Shaper

UPC Priority control

the necessary resources are available, it sets upthe connection. The algorithm used to judge con-nection admission is not specified in the stan-dards but is system-specific, with much researchgoing into techniques for optimizing this to thesystem characteristics[2]. The two main ap-proaches in designing these algorithms are callednon-parametric and parametric. In the formerapproach, actual traffic is monitored to estimatewhether sufficient resources are available toestablish a new connection. The parametricapproach creates a queue model such as M/D/1,based on the user-requested resources, analyzesits features mathematically and bases the con-nection admission decision on this result.

CONTROL FUNCTIONS DURING A CALL. Thecontrol functions used during a call include usershaping, usage parameter control (UPC) at thenetwork entrance, and cell priority control innodes.

1. Shaping function and UPCThe shaping function is used to control thetraffic sent by the user so that it matches theparameters requested by the user prior to thecall. UPC monitors the incoming traffic to seewhether it conforms to the user-requested pa-rameters. The algorithm used here is called genericcell-rate algorithm (GCRA), and it is speci-fied in both the ATM Forum and ITU-T rec-ommendations.

2. Priority control functionPriority control, like CAC, is not specified in

R&D PROGRESS REPORTS

R & D P R O G R E S S R E P O R T S

· 13March 2001

the standards; but it has long been researchedas a function required by the system in orderto guarantee a diverse range of quality levels. Generally, the function is implemented asshown in Fig. 2, using separate queues perconnection or per QoS class at each outputinterface, and controlling the priority of eachqueue. Among the possible control tech-niques, head of the line (HOL) and weightedround robin (WRR) make it relatively easy toimplement high-speed processing in hard-ware.

Switching function Output interface

Priority control function

Fig. 2 Role of the priority control function

HOL defines various priority levels basedon delay time. A cell can be sent only if thereare no other cells with higher priority at thetime. WRR, on the other hand, allows a mini-mum guaranteed bandwidth to be defined forindividual queues, allocating a portion of avail-able bandwidth to each queue in proportionto its minimum guarantee setting.

Implementation of traffic control in an ATMaccess systemThe traffic control function has been imple-mented as follows in an ATM access system.The access system, as shown in Fig. 3, uses pas-sive optical network (PON) technology to ac-commodate a large number of subscribers at lowcost. The description here of the traffic controltechniques focuses mainly on the optical linetermination (OLT) part.

APPROACH TO QOS GUARANTEE. The OLT ba-sically adopts a priority control method basedon QoS class, in order to achieve effective band-width use while providing a diversity of QoSclasses at low cost. With this method, QoS guar-antee for each connection is based on the traffic

Fig. 3 ATM access system configuration

ONT

ONT

ONT

ONT

OLT

KEYOLT Optical line terminal ONT Optical network terminalPON Passive optical network

Subscriber line interface (ATM, existing lines, LAN, etc.)

Transport system interface (ATM, existing lines)

PON

PON

behavior during the connection setup time (long-term guarantee).

PRIORITY CONTROL METHOD. The priority con-trol method applied to this access system isshown in Fig. 4. The access system is dividedinto a core switch for ATM switching and sub-switches, with the latter separated into priority

1.2G

2.4G

WRR

HOLC1

C2

C3

C4

D1

D2

D3

D4

155Mbps

Shaper

1.2G

1.2G

1.2G

2.4G

2.4G

2.4G

Core switch

Sub-switches

Priority control Priority control

Priority control

150M x 8

150M x 8

Fig. 4 Priority control method

control and low-speed interface functions. Thecore switch is able to obtain a very low cell lossrate thanks to the high-speed (1.2Gbps) multi-plexing effect on input lines and the 50 percentload reduction (2.4Gbps) on output lines.



Fig. 5 shows examples of actual values forthese and also indicates, for the sake of com-parison, the values achieved in the case of othermultiplexing rates and output speeds. These re-sults show that with the method adopted for thissystem (1.2Gbps input: 2.4Gbps output), an ex-tremely low cell discard rate is achieved by buff-ering only a few dozen cells. This enables thequality control points to be concentrated at thesub-switches.

Priority control in the sub-switches, as shownin Fig. 4, makes use of a shaper at each outputinterface for controlling the bandwidth divisionand output traffic in each interface. Each shaperhas a separate queue for each QoS class, with adivision made between classes with stringentdelay requirements (for the time being only theCBR class) and other classes.

HOL scheduling is used for control betweenthese two types of classes. Between classes withno delay requirement (for the time being onlynrt-VBR and UBR classes), WRR is used to guar-antee a minimum bandwidth for each class. Inthis way a long-term minimum bandwidth isguaranteed also for each connection.

SUB-SWITCH DEVELOPMENT. The priority con-trol described above was implemented using LSIchips (advanced switching LSI chips). Each chipaccommodates eight 155Mbps interfaces. Asmany as four shapers can be operated per inter-face. For each shaper there are six queues. Forfuture needs, faster speed can be achieved bybundling four interfaces into one 622Mbps in-terface. For each queue in Fig. 4 a buffer size ofup to 64k cells (for a total of 512k cells) can beprovided. The appearance of the access systemboard is shown in Fig. 6.

RESOURCE ALLOCATION BY CAC. Next we dis-cuss the use of the CAC function in connection

Fig. 5 Cell discard rate in core switch

1.00E-19

1.00E-15

1.00E-11

1.00E-07

1.00E-03

1 2 3 41.00E-19

1.00E-15

1.00E-11

1.00E-07

1.00E-03

1 2 3 4

1.2G 2.4G

1.2G 1.2G

622M 1.2G

622M 622M

Buffers (x32 cells)

Cel

l dis

card

rat

e

Fig. 6 ATM access system

setup. This system adopts a parametric approachneeding no special hardware. The decision onconnection admission takes into account the fol-lowing factors:

1. Number of established connections: A deci-sion is made as to whether the supportednumber of connections are used up.

2. Availability of requested bandwidth: A deci-sion is made as to whether the bandwidthrequested by the user can be obtained fromthe amount allocated in advance in the man-agement element. Specifically, the decisionis made as follows:�PCR < allocated bandwidth (for CBR)�SCR < allocated bandwidth (for VBR) etc.

3. Buffer availability: Even when the requiredbandwidth is available, as above, there willgenerally be delay variation in the input traf-fic. A decision must therefore be made as towhether there is enough buffer capacity toabsorb this variation. With this system, the decision is based ona queue model defined for each queue. For


· 15March 2001

the CBR class, which is processed with thehighest priority in this system, an M/D/1model is used; for other classes, a GI/G/1model is applied. In so doing, an ON/OFFmodel is applied to the cell arrival process toaccount for burstiness. Further, by applying a virtual server tech-nique to the service process, the priority con-trol function described above is accounted for.The techniques described by Yokotani, Ichi-hashi and Yabe[3] are applied to the analysismethods.

EXTENDED FUNCTIONS. Besides the traffic con-trol functions described above, a strict QoS guar-antee is implemented for each connection usingper-connection queuing and shaping. In addition,early packet discard/partial packet discard (EPD/PPD) are applied, which are demonstrably ef-fective in packet-based communication. Theseextended functions are connected to the coreswitch as in Fig. 7 so they can be shared by each

Fig. 7 Implementation of extended functions

Extended functions

Core switch Sub-switches

Same as CBR, so no degradation

- Per-connection bandwidth control- EPD/PPD

output interface. To prevent quality degradationin the existing sub-switches, control is carriedout equivalent to that for CBR traffic. ❑

References[1]The ATM Forum: �Traffic Management Specification,� Version 4.0,

February 1996.

[2]R. Onvural, �Asynchronous Transfer Mode Networks: PerformanceIssues,� 2nd Edition, Artech House, 1995.

[3]T. Yokotani, T. Ichihashi, M. Yabe, �An Ultra Light Weight CACMechanism (ULCAC) for Soft Guarantee in ATM Networks,� IEEE22nd LCN, pp. 432-440, 1997.



*Kazuumi Koguchi is with Communication Systems Development Center and Seiji Kozaki is with InformationTechnology R&D Center.

New LSI ChipsProvide ATMTermination, OAMProcessing andTraffic Control forBroadbandCommunications

ATM transport systems are used for back-bone networks because of their high speed andlarge data-handling capacity. In addition to rawbandwidth, however, they require sophisticatedoperation, administration and maintenance(OAM) functions for quick response to failures,along with advanced traffic control functions.Applying the latest device technology, we havedeveloped LSI chips that realize high speed andthe required advanced functionality while reduc-ing equipment size and power needs.

Specifications of the newly developed LSI chipsare given in Table 1. Here we give an overviewof each chip and describe their main functions.Applied to an ATM cross-connect system andan ATM access system, the chips contribute tothe compact system size and low power con-sumption.

2.4Gbps/622Mbps ATM termination chipWe developed LSI chips that implement ATMinterface functions, featuring throughput of2.4Gbps and compliant with the relevant ITU-Trecommendations and ATM Forum standards.ATM cell-handling functionality is implementedin high-density CMOS LSI chips employing 32-bit parallel processing. By switching modes, asingle chip can function as a 622Mbps through-put ATM interface chip.

The ATM termination LSI chips provide thefollowing functions:1. Section overhead (SOH) generation and ter-

mination2. Pointer generation and termination3. Path overhead (POH) generation and termination4. ATM cell transmission and reception5. Virtual container (VC) path testing6. Alarm handling7. Performance monitoring

The format of transmission frames is based ona synchronous digital hierarchy (SDH). SOH,pointer and POH generation and termination arecarried out as stipulated in the ITU-T recom-mendations, as are the mapping and demappingbetween ATM cells and their frames.

The function for VC path testing can be usedto confirm continuity of VC-carried informationon the SDH layer. The alarm-handling functioncollects alarm data on the lower (physical) layer,transfers alarms to connected equipment, andhandles such processing as the notification ofalarms to the upper (management) layer. Theperformance-monitoring function monitorstransmission quality at the SDH and ATM level,ATM cell count, pointer justification count, andother parameters. In addition there are commu-nication ports for order wire, data communica-tion channels, etc., assigned on the SOH, andports for transmitting and receiving automaticprotection switching (APS) information.

Table 1 Main chip specifications

LSI chip functions2.4G/622Mbps 622/156Mbps 2.4Gbps UPC and AdvancedATM termination OAM processing OAM processing shaping switching

Process 0.35µ CMOS 0.25µ CMOS 0.25µ CMOS 0.35µ CMOS 0.25µ CMOS

Package 520-pin BGA 304-pin QFP 304-pin QFP 208-pin QFP 576-pin BGA

Operation 155.52/77.76/19.44MHz 77.76/19.44MHz 77.76MHz 19.44MHz 77.76MHz

Number of gates 523k 770k 750k 120k 1000k

On-chip RAM 31Kbits 1150Kbits 360Kbits 500Kbits -

Supply voltage 3.3V 3.3V, 2.5V 3.3V, 2.5V 3.3V 3.3V, 2.5V

I/O level LVPECL/LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS

Power dissipation 4.98W(Rx)/3.99W(Tx) 4.2W 3.3W 0.9W 2.55W

by Kazuumi Koguchi & Seiji Kozaki*


· 17March 2001

Table 2 ATM termination LSI functions andstandards

Function Standard

SOH generation/termination ITU-T rec. G.707 to 709Pointer generation/termination ITU-T rec. I.432POH generation/termination ATM Forum af-phy-0133.000,ATM cell transmission/receipt af-phy-0046.000

VC path testing ITU-T rec. 0.181

Alarm handlingITU-T rec. G.783, G.784ITU-T rec. I.432

Performance monitoringITU-T rec. G.826ITU-T rec. I.732

The specifications of each function are givenin Table 2.

LSI CHIP CONFIGURATION. The LSI chips imple-menting ATM termination functions are config-ured as shown in Fig. 1.

In this figure, the flow from upper left to rightis the reception processing of signals on thetransmission line, and that from lower right toleft is the transmission processing of transmis-sion line signals. The I/O interface on the trans-mission-line side is for 16-bit parallel 156Mbpssignals in 2.4G mode, and 8-bit parallel 78Mbpssignals in 622M mode; these signals undergofurther parallel processing and 32-bit parallelinternal processing.

For the path-testing function, either ATM cellsor continuity test signals dropped/inserted in-side the LSI chip can be selected as the signalscontained in the VC area; normally ATM celldata from the equipment side is transmitted. TheI/O interface on the equipment side is for 32-bit

parallel 78Mbps signals in 2.4G mode, and 8-bitparallel 78Mbps signals in 622M mode.

In transmit mode, the clock supply in the re-ceive circuits is disabled, and in receive modethe clock supply in the transmission circuits isdisabled, as a power-saving measure. Parity in-formation is sent with every eight bits of userinformation to check the normalcy of each pro-cessing block, in order to detect failure on theinternal processing path. The chip supports avariety of clock-system designs so as to allowswitching of clock sources in the pointer termi-nation and cell receive processing blocks on thereceiving side, and in the cell transmit process-ing and parallel-to-serial conversion blocks onthe transmitting side.

FEATURES. The main features of the ATM ter-mination LSI chip are summarized below.

1. Compact size, low power consumption andlow cost

ATM termination functions are implemented inhigh-density CMOS LSI chips using 32-bit paral-lel processing.

2. Switched operating modesA 2.4Gbps interface uses two chips (switchingbetween transmit and receive modes); a 622Mbps interface uses a single chip.

3. Incorporates peripheral functionsThe alarm-handling functions, performancemonitoring, path-continuity testing and othermanagement-control functions are consolidatedon chip rather than as the external circuits ofconventional chips.

Fig. 1 Configuration of the ATM termination LSI chip

S/P SOHTRM

PTRTRM

POHTRM

PTST-Rx

CELL-Rx

O/PIF

78M x 32or 78M X 8Data out

156M x 16or 78M x 8Data in

P/S SOHGEN

PTRGEN

POHGEN

PTST-Tx

CELL-Tx

I/PIF

78M x 32or 78M X 8Data in

156M x 16or 78M x 8Data out

KEYS/P Serial-to-parallel conversion P/S Parallel-to-serial conversionSOH TRM Section overhead termination SOH GEN SOH generationPTR TRM Pointer termination PTR GEN Pointer generationPOH TRM Path overhead termination POH GEN Path overhead generationPTST-Rx Path test receiver PTST-Tx Path test transmitterCELL-Rx Cell Receiver CELL-Tx Cell transmitterO/P IF Output interface I/P IF Input interface

Alarm Handling Performance Monitoring



4. Compliant with standardsEach of the functions conforms to ITU-T recom-mendations and ATM Forum standards (see Table2). Where clear-cut standards are lacking, pa-rameters can be set via the CPU interface forflexible support.

OAM processing LSI chipRapid action in response to transmission-line orequipment failures is vital to minimize theirimpact. We developed OAM processing LSI chipsfor 622/156Mbps and 2.4Gbps interfaces, imple-menting operation, administration and mainte-nance (OAM) functions[1] for this purpose.

FUNCTIONAL SPECIFICATIONS. The OAM pro-cessing LSI chip implements the following OAMfunctions:

1. Fault management2. Performance monitoring3. Loopback testing4. Continuity characteristics measurement5. Virtual-path switching6. Continuity check (supported only for the 622/

156Mbps interface)

The fault management function generates theOAM cells (VP/VC-AIS and VP-RDI) that areused to send alarms when transmission-line orsystem trouble occurs. Equipment in the net-work detects these cells to determine the fail-ure status.

The performance-monitoring function mea-sures the service quality of a designated VP/VCby sending OAM cells containing maintenanceinformation back and forth between equipment.

The loopback testing function is used to lo-cate a faulty section by sending test OAM cellsfrom one point on the network and looping themback at various other points to confirm VP/VCcontinuity.

The continuity characteristics measurementfunction measures bit-error rate, cell loss andother factors by exchanging OAM cells contain-ing test signals with equipment and confirmingthe designated VP/VC continuity. VP switchingis used in duplex sections; OAM cells for VPswitching are generated when a failure occursor for normal maintenance, and failure informa-tion or switchover information is notified.

Continuity checking is performed by periodi-cally sending OAM cells for this purpose be-tween equipment to monitor the designated VP/VC continuity and detect broken connections.

The OAM processing LSI chip supports boththe user network interface (UNI) and network

node interface (NNI), and is capable of handlingas many as 4,096 VP/VC connections.

LSI CHIP CONFIGURATION. The configuration ofthe 622/156Mbps OAM-processing LSI chip isshown in Fig. 2. OAM-processing functions forthe transmitting and receiving sides of the trans-mission line are implemented on a single chip.Cell I/O and internal processing are handled as8-bit parallel processing.

Operation is at 77.76MHz for the 622Mbps in-terface and 19.44 MHz for the 156Mbps inter-face modes. Each of the OAM functions consistsof an independent block, and it is possible tooperate only the blocks for the functions beingused, stopping the clock supply to blocks not inuse. In this way, power use can be minimized inequipment that makes only partial use of thefunctions provided.

The order of OAM cell sending and of drop/monitor operations can be set, using the CPUinterface, for flexible adaptation to the functionalneeds of various equipment. Two cell I/O inter-faces are provided at both the sending and re-ceiving sides, supporting external circuits whereadditional functionality is required.

The 2.4Gbps OAM-processing LSI chip oper-ates at 77.76MHz and uses 32-bit parallel pro-cessing of cell I/O and for internal processing.The basic configuration is similar to that of the622/156Mbps chip, with the same power-savingoptions and adaptability to the functional needsof the equipment in which it is used. Cell I/Ointerfaces are limited to one each in order toreduce pin count and power consumption.

FEATURES. The main features of the OAM pro-cessing LSI chips are as follows:

1. A 0.25µ CMOS process is adopted for high den-sity and low power use.

2. 2.4Gbps OAM processing for the transmittingand receiving sides is implemented on a singlechip.

3. The power needs and functions can be adaptedflexibly to the applied system.

Traffic control LSI chips

UPC AND SHAPER LSI CHIP. The usage param-eter control (UPC) functions for monitoring andrestricting cell bandwidth incoming from sub-scribers and the shaping function for reducingcell-delay variation (CDV) have been imple-mented on a single LSI chip.

The GCRA algorithm[2][3] specified by the ITU-T and ATM Forum is adopted as the UPC algo-


· 19March 2001

rithm. In order to support guaranteed frame rate(GFR), an F-GCRA algorithm is also imple-mented for monitoring and control at the indi-vidual frame level.

This chip is able to handle up to 1,024 VP/VCconnections.

ADVANCED SWITCHING LSI CHIP. We developedan ATM switching LSI chip with advanced traf-fic-control functions. The single chip implementsan output buffer-type switch, realizing 2.4Gbpsthroughput. External SDRAM is used as thebuffer memory, providing a buffer capacity of512,000 cells. The main features are as follows:

1. Large-capacity cell buffer2. Supports multiple service classes3. Minimum bandwidth guaranteed by WRR.4. Shaping functions5. Parallel synchronous operation (instantaneous

protection switching)

The devices described point the way to smallerand highly efficient systems for the reliable op-eration of broadband communications, and haveextremely wide potential applications. ❑

References1. ITU-T rec. I.610: B-ISDN Operation and Maintenance Principles and

Functions (1999).

2. ITU-T rec. I.371: Traffic Control and Congestion Control in B-ISDN(1996).

3. ATM Forum: Traffic Management Specification Ver. 4.1 (1999).

Fig. 2 Configuration of the 622/156 Mbps OAM processing LSI chip

CPU interface

Cell input 1 8HEC-EDC check

Cell input 2 8HEC-EDC check

Cell input 3 8

Cell input 4 8

Continuity check

VP protection

CC measurement

Loopback test

Performance monitoring

Transmitter side

Fault management

Fault management

HEC-EDC insert

HEC-EDC insert

Access sequence control

Cell input 1

HEC-EDC check

HEC-EDC check

Continuity check

VP protection

CC measurement

Loopback test

Performance monitoring

HEC-EDC insert

HEC-EDC insert

Access sequence control

8

Cell input 28

Cell input 38

Cell input 48

KEYCC Continuity characteristics



*Shin-ichi Kaneko is with the Information Technology R&D Center.

by Shin-ichi Kaneko*

Devices for ATMFiber OpticsCommunication

New devices developed for ATM optical com-munications are described here. They are anoptical transceiver and a hybrid integrated opti-cal transceiver module with improved compact-ness, power consumption and economy.ATM-PON termination LSI chips were also de-veloped for use on the office side (OLT) and sub-scriber side (ONT), conforming to ITU-Tinternational recommendation G.983.1.

Transceiver for optical access network andoptical trunk networkAn optical transmitter IC that can be used forboth continuous and burst modes, a continuous-mode optical receiver IC, and a burst-mode op-tical receiver IC were developed to realize thecompact size, low-power use and low cost re-quired in an optical access network. These de-vices are applicable to the 52Mbps and 622Mbpsoptical interfaces of the optical system, with thetransmitter and receiver functions implementedon a single chip. Adopting a PECL I/O electricalinterface, the chips operate on a single 3.3Vpower source (the burst-mode receiver IC oper-ates at +5.0V) and consume less than one watttotal for transmitting and receiving.

Specialized ICs were also developed for a2.5Gbps optical interface, consisting of a one-chip transmitter and a two-chip receiver. Bothpower consumption and size are less than halfthat of previous chips. Fig. 1 shows the ITU-TG.957 L-16.3 optical receiver and Table 1 liststhe developed optical interfaces.

Optical transceiver module for ATM-PONONTThe optical modules used in an optical accessnetwork must be compact and low cost. Activeresearch has therefore been directed at devel-oping an optical transceiver module with hybridintegration of a laser diode, a receiver photo-diode, and wavelength division multiplexing(WDM) components on a silicon substrate.

One design issue was how to suppress cross-talk between the transmitter and the receiver

because the receiver should detect very weaksignals whereas the transmitter should outputpowerful signals in the same package. Anotherwas to meet the need for low cost. A descrip-tion of the structure and features of the devel-oped module follows.

STRUCTURE OF THE OPTICAL TRANSCEIVERMODULE. The appearance of the developed opti-cal transceiver module is shown in Fig. 2 and itsstructure in Fig. 3. On a silicon substrate, thismodule integrates a 1.3�m-band laser diode, areceiver photodiode, a polymer-waveguide chip,single-mode fiber (SMF) and multi-mode fiber(MMF), using passive alignment technology tobuild a hybrid integrated optical transceivermodule. A transfer-mold package, which is suit-able for reflow mounting, offers good mass pro-ductivity and low-cost packaging. At the sametime, an MU-type optical adapter was developedfor a standard optical interface, reducing costby eliminating the fiber for connector adapta-tion.

The polymer-waveguide chip was imple-mented for ease of mass production and low cost.

Fig. 1 ITU-T rec. G.957 L-16.3 optical transceiver

Optical transceiver module

MU-type optical adapter

Fig. 2 Module and adapter


· 21March 2001

Fig. 3 Module structure

eniL etartiBecafretnI

snoitacificepsecnatsiD

htgnelevaW)mµ(

secivedlacitpO noitpmusnocrewoP)xam(

)xT(timsnarT )xR(evieceR

tropsnarT

spbM048.15)HDS(

0-I759G-TJmk2

)eciffo-artni(3.1

htiwDLsnelediugevaw

DP W5.0:xR,W5.0:xT

spbM25.551)HDS(

1-I759.GT-UTImk2

)eciffo-artni(3.1

htiwDLsnelediugevaw

DP W5.0:xR,W5.0:xT

1.1-L759.GT-UTImk04

)eciffo-retni(3.1

htiwDLsnelediugevaw

DP W5.0:xR,W5.0:xT

3.1-L759.GT-UTImk04

)eciffo-retni(55.1 DL-PF DP W5.0:xR,W5.0:xT

spbM80.226)HDS(

4-I759.GT-UTImk2

)eciffo-artni(3.1

htiwDLsnelediugevaw

DP W5.0:xR,W5.0:xT

1.4-L759.GT-UTImk04

)eciffo-artni(3.1 *DL-BFD DP W8.0:xR,W6.0:xT

3.4-L759.GT-UTImk08

)eciffo-retni(55.1 *DL-BFD DP W8.0:xR,W6.0:xT

1.4-V196.GT-UTImk08

)eciffo-retni(3.1 *DL-BFD DPA W9.0:xR,W6.0:xT

3.4-V196.GT-UTImk021

)eciffo-retni(55.1 *DL-BFD DPA W9.0:xR,W6.0:xT

3.4-U196.GT-UTImk061

)eciffo-retni(55.1 *DL-BFD

DPAdepodrE:retsooB.pmarebiflacitpO

W9.0:xR,W6.0:xTW5.5:.pmA.tp0

spbM23.8842)HDS(

1.61-L759.GT-UTImk04

)eciffo-retni(3.1 **DL-BFD DPA W0.3:xR,W9.5:xT

3.61-L759.GT-UTImk08

)eciffo-retni(55.1 **DL-BFD DPA W0.3:xR,W9.5:xT

sseccA

spbM25.551)SDP(

1.389.GT-UTI

-MDW

,55.1:xT()3.1:xR

*DL-BFDDP

relpuocrebifMDWW5.0:xR,W5.0:xT

-MDW

,3.1:xT()55.1:xR

htiwDLsnelediugevaw

DPrelpuocrebifMDW

W5.0:xR,W5.0:xT

spbM25.551)SS(

1.1-L759.GT-UTI mk04 3.1MDShtiwDL

snelediugevawDP W5.0:xR,W5.0:xT

* : With isolator, without temperature control device. ** : With isolator and temperature control device.

Table 1 Optical interface specifications

Polymer waveguide chip Opaque resin

Receive photodiode

Preamp IC

Die pad

WDM filter

WDM filter

Electrode pattern

Wire

Silicon substrate with V groove

Laser diode with waveguide lens

Monitor photodiode

SMF

Waveguide MMF



The chip has the WDM filter which reflects1.3�m light and transmits 1.5�m light.

FEATURES OF THE OPTICAL TRANSCEIVER MOD-ULE. As noted above, a key feature of the opti-cal transceiver module is the reduction ofcross-talk between the transmitter and the re-ceiver. Cross-talk is caused by optical and elec-trical coupling between the transmitter andreceiver of the module.

The following measures were taken to preventoptical coupling between the laser diode andphotodiode: ● A high-isolation WDM filter is applied to the

edge of the polymer waveguide chip. ● Multi-mode fiber is inserted between the poly-

mer waveguide chip and photodiode. ● The photodiode is surrounded by opaque resin. ● A WDM filter is formed on the end of the MMF.

These measures succeeded in reducing opti-cal cross-talk to an extremely low level of-61.9dB. The following measures were taken to

Fig. 4 Sensitivity

10-12

10-3

10-4

10-5

10-6

10-7

10-8

10-9

10-10

10-11

-42 -40 -38 -36 -34 -32

Bit

erro

r ra

te

Average strength of received light (dBm)

Only receiver operating

Transmitter and receiver both operating

155Mbps, 223-1(continuous mode)

reduce electrical coupling between the trans-mitter and the receiver of the module: ● The laser diode is electrically isolated from

the die pad with ground potential. ● An electrode pattern is formed on the silicon

substrate between the transmitter and thereceiver and is connected to ground.

● The receiver is kept apart from the transmit-ter by inserting multi-mode fiber between thepolymer waveguide chip and the photo diode.

The effect of these measures was to reduceelectrical cross-talk to the extremely low levelof -83.5dB.

By reducing optical and electrical cross-talkas described above, we were able to achieve ex-cellent receive characteristics. Fig. 4 comparesthe bit-error-rate performance when only thereceiver is operated (simplex) and when bothtransmitter and receiver are operated together(duplex). The minimum sensitivity (error rate10-10) under the duplex operation is -35.5dBm,and a power penalty caused by the cross-talk is


· 23March 2001

Fig. 5 I-L curve

M32R

Status controlPLOAM control

CPU IF

19MbpsLV -TTL

M32R

Opticaltransceivermodulein OLT side

156MbpsLV -PECL

Burst mode bitsynchronizationcircuit

ATM-PON-LSI chipfor OLT

Upstream userinformation

Downstream userinformation

Fig. 6 Configuration of ATM-PON chip for OLT

Opt

ical

fibe

r ou

tput

(m

W)

0.5

3.0

2.5

2.0

1.5

1.0

0 10 20 30 40 50

Laser diode current (mA)

0.1dB. This small penalty indicates that cross-talk is adequately suppressed. Fig. 5 shows theI-L curve of the module. Output optical powerof 2mW is achieved at a laser-diode current of35mA.

The receiver characteristics and optical out-put characteristics of this module both satisfythe specifications for an ONT optical transceivermodule in an ATM-PON system given in ITU-Trec. G.983.1.

ATM-PON termination LSI chipsFinally, two ATM-PON termination LSI chipswere developed in compliance with ITU-T rec.G.983.1, the international standard for optical

network systems. These chips, applicable to theoptical-line terminal (OLT) and optical-networkterminal (ONT), were developed, applyingCMOS gate array LSI with a 0.25�m process.

ATM-PON TERMINATION LSI CHIP FOR OLT.This is mounted on a 156Mbps ATM-PON in-terface board in the OLT. Transmission speed is155.52Mbps both upstream and downstream. Thechip incorporates circuitry for serial-to-paralleland parallel-to-serial conversion supporting thistransmission speed and a burst-mode bit syn-chronization circuit. It can interface directlywith the 155.52Mbps LV-PECL-level signals ofthe optical-transceiver module (see Fig. 6). The



ITU-T rec. G.983.1-specified functions for start/stop control, alarm-handling control and controlof message handling with the ONT are realizedby firmware control, using one Mitsubishi Elec-tric M32R microprocessor each for the transmit-ter control and the receiver control. Thisconfiguration makes it easy to change functionsas specifications change.

ATM-PON TERMINATION LSI CHIP FOR ONT.The ONT installed in subscriber premises mustbe compact and low cost. An LSI chip was there-fore developed implementing ATM-PON func-tions, OAM functions and QoS control functionsfor each of the line cards accommodated by dif-ferent UNI types.

Speed of the transmission system is 155.52Mbpsin both upstream and downstream directions,and direct interfacing is possible with the155.52Mbps LV-PECL-level signals of the opti-cal-transceiver module. This LSI chip featuresthe adoption of firmware processing for statecontrol and for some of the alarm processing,using a simple on-chip control processor. Addi-tional features include OAM cell-processingfunctions such as VP-AIS generation andloopback cell termination and generation; theprovision of ATM-Forum standard Utopia Level1 interfaces to one or two line cards of 155.52Mbps each (19.88MHz, 8-bits parallel); and theability to realize optimum QoS for different line-card UNI by variable settings of the QoS bufferparameters as shown in Fig. 7. ❑

ATMcrossconnectcircuit

CPU IF

156MbpsLV -PECL

UTOPIA

Opticaltransceiver

modulein ONT sideStatus control

PLOAM control

QoS control

ATM-PON-LSIchip for ONT

Upstream userinformation

Downstream user information

Smallmicroprocessor

Fig. 7 Configuration of ATM-PON chip for ONT

vol. 93/mar. 2001 - mitsubishi electric · 2020. 2. 18. · vol. 93/march 2001 mitsubishi electric...

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