vlsiproj1-2
TRANSCRIPT
PROJECT
TWO INPUT CMOS GATES
Name: SYED MUDASSIR REHMAN
Course No: 5590VL
Student ID# 16160367
Email Id: [email protected]
Submission Date: 10/10/2013
NAND GATE
Truth table:
In1 In2 out0 0 10 1 11 0 11 1 0
Schematic:
NAND_Test
Pre Layout simulation:
Layout:
DRC:
Post layout simulation:
CIW
AND GATE
Truth table:
In1 In2 out0 0 00 1 01 0 01 1 1
Schematic
AND_test Schematic:
Pre-Layout Simulation:
Layout:
DRC:
Post-Layout Simulation:
CIW:
NOR GATE
Truth table:
In1 In2 out0 0 10 1 01 0 01 1 0
Schematic:
Nor_test Schematic:
Pre-layout simulation:
Layout:
DRC:
Post-layout Simulation:
CIW:
OR GATE
Truth table:
In1 In2 out0 0 00 1 11 0 11 1 1
Schematic:
Or_test schematic:
Pre-layout Simulation
Layout:
DRC:
Post layout Simulation:
CIW