vlsi testing and verification
DESCRIPTION
VLSI Testing and Verification. Shmuel Wimer Bar Ilan University, School of Engineering. Design for Testability. Testability requires design to be: Controllable : set to 1 and reset to 0 every circuit node Observable : be able to examine the logic value of any circuit node - PowerPoint PPT PresentationTRANSCRIPT
August 2010 1
VLSI Testing and Verification
Shmuel Wimer
Bar Ilan University, School of Engineering
August 2010 2
Design for Testability
• Testability requires design to be:
– Controllable: set to 1 and reset to 0 every circuit node
– Observable: be able to examine the logic value of any circuit
node
• It reduces testing cost
– allows high fault coverage with relatively few test vectors
– Essential to silicon debug since probing every node is impossible
• There are two design for testability (DFT) methods:
– Scan-based design
– Built-in self-test (BIST)
August 2010 3
Scan-Chain Flip-Flop
When scan mode is 0 the D flip-flop behaves in ordinary mode, and input is
being read from data-in. When scan mode is 1 input is taken from scan-in.
Flip
-flo
p
Scan Mode
Data-in
Q
Clock
Scan-in
0
1
All the flip-flops are then serially connected from Q to data-in, a giant shift
register, spanning the whole chip. In scan mode all the inputs of flip-flops
can be set by streaming in their desired values. Similarly, the output of flip-
flops can be streamed out.
August 2010 4
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Clo
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Scan-in
Scan-out
Inpu
ts
Out
puts
Scan-Chain Connections