Arithmatic Core & Digital Electronics NO PRJ

TITLE

ABSTRACT DOMAIN YOP

1

Low-Power

and Area-

Efficient

Carry

Select

Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast

arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and

power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly

reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA

(SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The

proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight

increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area,

power, and their products by hand with logical effort and through custom design and layout in 0.18- m CMOS

process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT

CSLA.

Arithmetic

Core and

Digital

Electronics

2013

2

Area-Time

Efficient

Scaling-

Free

CORDIC

Using

Generalized

Micro-

Rotation

Selection

This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By

suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the

accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to

redefine the elementary angles for reducing the number of CORDIC iterations. A generalized micro-rotation

selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for

identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the

number of iterations depending on the accuracy, area and latency requirements. Compared to the existing

recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E device

Arithmetic

Core and

Digital

Electronics

2012

3

Design and

implementa

tion of

demodulati

on

technique

with

complex

dpll using

cordic

algorithm

CORDIC (Coordinate Rotation Digital Computer) is a simple and efficient algorithm to calculate hyperbolic and

trigonometric functions. It is commonly used when no multiplier hardware is available (e.g., simple

microcontrollers and FPGAs). The only operations it requires are addition, subtraction, bit shift and lookup table.

The pipelined architecture for coordinate rotation algorithm for the computation of loop performance of complex

Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver is designed. The design of

CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture where

latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in the proposed

design can be achieved through optimization in the number of micro rotations. For better loop performance of

first order complex DPLL and to minimize quantization error, the number of iterations are also optimized.

Arithmetic

Core and

Digital

Electronics

2012

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VLSI PROJECTS – 2013

(Network-Security & Cryptographic Sciences, DSP, Arithematic Core & Digital Electronics, Digital

Communication & Information Theory, Digital Image Proccesing)

4

A New

Approach

for High

Performanc

e and

Efficient

Design of

CORDIC

Processor

This paper presents a new approach for the high performance and hardware efficient design of coordinate

rotation digital computer (CORDIC) processor structure. The proposed design approach completely eliminates

the ROM requirement of constant arctangent values. Furthermore, efficient designs of carry look ahead adders

(CLAs), exploiting one input as constant, in the angle adder/subtractor datapath speeds-up the computation while

maintaining regularity. The proposed architecture is implemented in FPGA as well as in 180nm standard cell

library. The proposed implementation has about 39% delay improvement in FPGA and about 34% delay

improvement in standard cell technology as compared to basic structure. About 47% power savings has been

achieved in the proposed structure.

.

Arithmetic

Core and

Digital

Electronics

2012

5

Design of

Plural-

Multiplier

Based on

CORDIC

Algorithm

for FFT

Application

CORDIC plural-multiplier is the key module to affecting the speed and accuracy of FFT processor. Considering

these demands, the problem of CORDIC algorithm is discussed in detail and the according optimization methods

are given in this paper. Then, the hardware pipelining structure of the CORDIC multiplier is put forward.

Comparison results about RTL simulation results with MATLAB calculation indicate that the design is feasible

and practical.

Arithmetic

Core and

Digital

Electronics

2012

6

Hardware

Efficient

Architectur

e for

Generating

Sine/Cosine

Waves

This paper presents a hardware efficient architecture for generating sine and cosine waves based on the CORDIC

(Coordinate Rotation Digital Computer) algorithm. In its original form the CORDIC suffers from major

drawbacks like scale-factor calculation, latency and optimal selection of micro-rotations. The proposed

algorithm overcomes all these drawbacks. We use leading-one bit detection technique to identify the micro-

rotations. The scalefree design of the proposed algorithm is based on Taylor series expansion of the sine and

cosine waves. The 16-bit iterative architecture achieves approximately 4.5% and 6.7% lower slice-delay product

as compared to the other existing designs. The algorithm design and its VLSI implementation are detailed.

Arithmetic

Core and

Digital

Electronics

2012

7

FPGA

Design of a

Fast 32-bit

Floating

Point

Multiplier

Unit

An architecture for a fast 32-bit floating point multiplier compliant with the single precision IEEE 754-2008

standard has been proposed in this paper. This design intends to make the multiplier faster by reducing the delay

caused by the propagation of the carry by implementing adders having the least power delay constant. The

implementation of the multiplier module has been done in a top down approach. The sub-modules have been

written in Verilog HDL and then synthesized and simulated using the Xilinx ISE 12.1 targeted on the Spartan 3E

Arithmetic

Core and

Digital

Electronics

2012

8

Design &

Implementa

tion of

Floating

point ALU

In this paper, the implementation of DSP modules such as a floating point ALU are presented and designed. The

design is based on high performance FPGA "Cyclone TI" and implementation is done after functional and

timing simulation. The simulation tool used is ModelSim. The tool for synthesis and implementation is Quartus

n. The experimental results shows the functional and timing analysis for all the DSP modules carried out using

high performance synthesis software from Altera.

Arithmetic

Core and

Digital

Electronics

2012

9

A FPGA

IEEE-754-

2008

DECIMAL

64

FLOATIN

G-POINT

ADDER/S

UBTRACT

OR

This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design

performs addition and subtraction on 64-bit operands that use the IEEE 754-2008 decimal encoding of DFP

numbers and is based on a fully pipelined circuit. The design presents a novel hardware for pre-signal generation

stage and an enhanced version of previously published leading zero stage. The design can operate at a frequency

of 200 MHZ on a Virtex-5 with a latency of 8 cycles. The presented DFP adder/subtractor supports operations

on the decimal64 format and it is easily extendable for the decimal128 format. To our knowledge, this is the first

hardware FPGA design for adding and subtracting IEEE 754-2008 using decimal64 encoding.

Arithmetic

Core and

Digital

Electronics

2012

10

FPGA

Implementa

tion of Sine

and Cosine

Value

Generators

using

Cordic

Algorithm

for Satellite

Attitude

Determinati

on and

Calculators

Now-a-days various Digital Signal Processing systems are implemented on a platform of programmable signal

processors or on application specific VLSI chips. Coordinate Rotation DIgital Computer (CORDIC) algorithm

has turned out to be such kind of programmable signal processor. In recent times, it has been a widely researched

topic in the field of vector rotated Digital Signal Processing (DSP) applications due to its simplicity. This paper

presents the design of pipelined architecture for coordinate rotation algorithm for the computation of loop

performance of complex Digital Phase Locked Loop (DPLL) in In-phase and quadrature channel receiver. The

design of CORDIC in the vector rotation mode results in high system throughput due to its pipelined architecture

where latency is reduced in each of the pipelined stage. For on-chip application, the area reduction in proposed

design can is achieved through optimization in the number of micro rotations. For better loop performance of

first order complex DPLL and to minimize quantization error, the numbers of iterations are also optimized..

Arithmetic

Core and

Digital

Electronics

2012

11

Area-Time

Efficient

Scaling-

Free

CORDIC

Using

Generalized

Micro-

Rotation

Selection

This paper presents an area-time efficient CORDIC algorithm that completely eliminates the scale-factor. By

suitable selection of the order of approximation of Taylor series the proposed CORDIC circuit meets the

accuracy requirement, and attains the desired range of convergence. Besides we have proposed an algorithm to

redefine the elementary angles for reducing the number of CORDIC iterations. A generalized micro-rotation

selection technique based on high speed most-significant-1-detection obviates the complex search algorithms for

identifying the micro-rotations. The proposed CORDIC processor provides the flexibility to manipulate the

number of iterations depending on the accuracy, area and latency requirements. Compared to the existing

recursive architectures the proposed one has 17% lower slice-delay product on Xilinx Spartan XC2S200E

device.

.

Arithmetic

Core and

Digital

Electronics

2012

12

FPGA

Implementa

tion of a

chaotic

oscillator

using RK4

method

The dual deterministic-stochastic behavior of chaotic systems (CS) makes them extremely interesting in

electronic engineering as CS may replace noise sources in different applications. Consequently it is convenient

to have hardware implementations for both, analog and digital versions. Discrete components, Micro

Controllers, Digital Signal Processors (DSP) and Field Programmable Gate Arrays (FPGAs) are possible

choices. For digital realizations the Ordinary Differential Equations (ODE’s) are replaced by a discrete time

system. Furthermore numerical values are expressed in a numerical representation. It is well known that these

two discretization processes may strongly affect the chaotic behavior of the system. In previous contributions we

considered the use of the Euler’s algorithm in two different numerical representations: (a) integer arithmetics and

(b) single floating point IEEE-754 standard. For applications that require a good agreement between the analog

chaotic system and its digital counterpart, more involved algorithms and/or numerical representations must be

used. Guided by numerical simulations, in this paper we propose an improvement replacing the Euler’s

algorithm by the fourth order Runge Kutta algorithm (RK4). In order to diminish the required hardware a

method based on blocks’ reusing is proposed. The procedure is exemplified on a Lorenz CS. The whole design

was implemented onto a FPGA, using only 12 % of its logic elements, 13% of its embedded multipliers and 34

% of its memory bits.

Arithmetic

Core and

Digital

Electronics

2012

13

An

Efficient

Implementa

tion of

Floating

Point

Multiplier

In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier

targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The

multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more

precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock

cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier

core.

Arithmetic

Core and

Digital

Electronics

2012