vlsi - calculator
DESCRIPTION
This is a Project Report - Design and Implementation of Special purpose circuit that performs Calculator FunctionsTRANSCRIPT
EE 577A
VLSI DESIGN - I
FALL 2013
INSTRUCTOR: PROF. PEDRAM MASOOD
PROJECT REPORT
Submitted by,
HARI PRASANTH GOVINDARAJU KARTHIK RAMASAMY
USC ID: 4628-8849-28 USC ID: 5539-4733-38
OBJECTIVE
The main objective of this project is to design a ‘Special Calculator’ that performs addition subtraction
and signed multiplication using the cells designed in part 1 and in lab assignments.
SPECIFICATION
Vdd = 1.8V
Primary Clock, Clk0
Power is the average power per Clk0 period in the test vector
Area is the rectangular area enclosed
Λ = 0.1 µm
CALCULATOR DESIGN:
The block diagram of the Calculator design is as follows.
This “calculator” can fulfill the following functions:
1. Write data from external source or the final results from the “calculator” into the SRAM cell. There is a test circuit which counts the number of the “1” in the Out[7]-Out[4] of the result of multiplier. If the number of “1” is an odd number, Out[7]-Out[4] will be written into SRAM. If the number of “1” is an even number, data from external source will be written into SRAM.
2. When calculator starts to work, it first reads a data from SRAM into 4-bit D-latch. When this is done, it reads another data from SRAM into the other 4-bit D-latch. The two sets of data comprise two operands (A and B) for the calculator. The dynamic adder, dynamic subtractor and multiplier together fulfill the operation we want.
3. When Initial signal is high, external data are directly written into the SRAM regardless of the result of the test circuit.
MULTIPLE CLOCK SIGNALS DESIGN There are several clock signals in this structure. Clk0 are designed with matching the following restrictions:
Within one Clk0 period, the results of the calculator can be ready at the input data ports of SRAM if the results need to be written into Clk0. Therefore, Clk0 consists of the amount of time for SRAM read and data path delay.
Within one Clk0 period, Addr[5]-Addr[0] may change (different write/read address)
Clk0 has 50% duty cycle. For other clock signals, namely Clk1, Clk2, Clk3, Clk4, are designed with different duty cycles to meet
the functionality. All the clock signals have infinite driving ability.
PERFORMANCE METRICS SPECIAL CALCULATOR
Performance Metrics Clock Frequency 100 MHz Area 232.32 um2 Average Power Consumption 4100 uW Clock Frequency / Power 0.024390 MHz/uW Clock Frequency / Area 0.43044 MHz/um2 Clock Frequency / (Area*Power) 1.0498e-4 MHz/um2-uW
LVS REPORT
@(#)$CDS: LVS version 6.1.4-64b 09/21/2011 03:25 (sjfdl054) $
Command line: /usr/local/cadence/IC610/tools.lnx86/dfII/bin/64bit/LVS
-dir /home/scf-04/hgovinda/cds/LVS -l -s -t /home/scf-
04/hgovinda/cds/LVS/layout /home/scf-04/hgovinda/cds/LVS/schematic
Like matching is enabled.
Net swapping is enabled.
Using terminal names as correspondence points.
Compiling Diva LVS rules...
Net-list summary for /home/scf-04/hgovinda/cds/LVS/layout/netlist
count
2046 nets
48 terminals
2093 pmos
2605 nmos
Net-list summary for /home/scf-
04/hgovinda/cds/LVS/schematic/netlist
count
2046 nets
48 terminals
2093 pmos
2605 nmos
Terminal correspondence points
N2005 N19 A0
N2004 N27 A1
N2003 N26 A2
N2002 N25 A3
N2000 N24 A4
N1998 N23 A5
N2042 N12 C0
N2006 N16 Clk0
N2034 N17 Clk0_b
N2001 N9 Clk3
N2009 N10 Clk3_b
N1999 N7 Clk4
N2035 N6 Clk4_b
N2041 N33 Initial
N2014 N13 Inps1
N2013 N15 Inps2
N2012 N2 Inps3
N2011 N4 Inps4
N2033 N78 Ip1
N2032 N43 Ip2
N2031 N3 Ip3
N2030 N5 Ip4
N2039 N81 M0
N2038 N79 M1
N2037 N46 M2
N2036 N36 M3
N2018 N37 Out0
N2017 N41 Out1
N2016 N35 Out2
N2015 N80 Out3
N2029 N11 Phi
N2040 N18 Precharge
N2028 N40 X1
N2027 N31 X2
N2025 N39 X3
N2024 N30 X4
N2022 N61 Y1
N2021 N29 Y2
N2020 N34 Y3
N2019 N38 Y4
N2010 N8 c0
N2045 N14 clk1
N2044 N32 clk2
N2008 N0 gnd!
N2023 N22 read_en
N2026 N1 vdd!
N2043 N21 wordline_en
N2007 N20 write_en
Devices in the rules but not in the netlist:
cap nfet pfet nmos4 pmos4
The net-lists match.
layout schematic
instances
un-matched 0 0
rewired 0 0
size errors 0 0
pruned 0 0
active 4698 4698
total 4698 4698
nets
un-matched 0 0
merged 0 0
pruned 0 0
active 2046 2046
total 2046 2046
terminals
un-matched 0 0
matched but
different type 0 0
total 48 48
Probe files from /home/scf-04/hgovinda/cds/LVS/schematic
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:
Probe files from /home/scf-04/hgovinda/cds/LVS/layout
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out: