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Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

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Page 1: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Visual Specification of a DSL Processor Debugger

Tamás Mészáros and Tihamér Levendovszky

Budapest University of Technology and Economics

Page 2: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Overview Defining the Dynamic Behavior of Graphical

DSLs Animation Framework

A Case Study Graph transformation debugger

Page 3: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Building DSLs Abstract syntax (rules of the language)

Metamodeling

Concrete syntax (visual appearance) Annotations to metamodel

Textual languages

DSL + processing

Dynamic behavior?

Page 4: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Defining Dynamic Behavior Annotation to metamodel

Textual programming language constructs

DSL Visual Modeling and Transformation System

(VMTS) Animation Framework

Page 5: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

THE VMTS ANIMATION FRAMEWORK

Part I.

Page 6: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Animation Framework Overview

PortPN PortTimer PortViews PortModels

GetDiagramView Default

Selecting

GettingView

Highlighting

Firing

[no fireable transitions]

PortPN:EventGetFireableTransition

[fireable transition]

PortViews:EventGetView

[PortViews:EventGetView_]

PortViews:EventHighlight

[PortTimer:Tick]

[PortTimer:Tick]

PortPN:EventFire

PortViews:UnHighlight

EH

_UI (

…)

PNAnimator

PortModels PortViews PortPN PortTimer

Por

tMo

dels

Po

rtV

iew

s

EH

_PetriN

et (…)

PortP

N

EH

_Tim

er (…)

PortT

imer

Initialize

EH_GT

PortGT

ProcessNextCFEdge

ProcessStartNode

Matching

ApplyCurrentMatch

ApplyInternalCausalities

ApplyInternalCausality

Initialized

PreNextCFEdge

PostNextCFEdge

PreStartNode

PostStartNode

PreDecision

PreEndNode

PreRuleNode

PreInitMatch

PreMatching

PreApplyMultipleMatch

PreApplyCurrentMatch

PreInternalCausalities

PreInternalCausality

PostInternalCausality

PostInternalCausalities

PostApplyCurrentMatch

PostApplyMultipleMatch

PostRuleNode

AgsiCFEdge

InternalCausalityResult

AgsiCFEndNode

TrafoOutputPlaces

AgsiInternalCausality

IAgsiCFNode

AgsiRuleExecutionResults

Animator state machineHigh level animation model

Event handler modelEvent handler

implementation

Animated model

.

Animation engine

apply

gen.

ref.

EN

VIR

ON

ME

NT

.

Domain knowledge and simulation engines

Page 7: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

VMTS Animation Framework Separating animation from model simulation

The domain knowledge is considered black-box

Animation logic is described with an event-driven state machine

Integration with an event-driven approach

The integration is supported with visual modeling techniques

Processing animation models Generating skeleton for event handlers

Generating executable application from animator models

Page 8: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

VMTS Animation Framework Event handler model

Event-driven interface for external components

Elements Events Entites ( event parameters) Ports

EventGetEnabledTransition

EventFireTransition

EventGetEnabledTransition_

EventFireTransition_

DiagramModel

ShapeModel

EH_PetriNet

PortPN

PNModel

Transition

Transition

Transition

Port

Event Entity

EventHandler

Handles

OperatesOn

Page 9: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

VMTS Animation Framework Animator

Event-driven state machine

Port-based interface

States

Transitions Guard expression Action expression

PortPN PortTimer PortViews PortModels

GetDiagramView Default

Selecting

GettingView

Highlighting

Firing

[no enabled transitions]

PortPN:EventGetEnabledTransition

[enabled transition]

PortViews:EventGetView

[PortViews:EventGetView_]

PortViews:EventHighlight

[PortTimer:Tick]

[PortTimer:Tick]

PortPN:EventFire

PortViews:UnHighlight

Page 10: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

VMTS Animation Framework High Level Animation Model

Event handler

Animator

Port

Event route

EH

_UI (

…)

PNAnimator

PortModels PortViews PortPN PortTimerP

ortM

ode

lsP

ort

Vie

ws

EH

_PetriN

et (…)

Po

rtPN

EH

_Tim

er (…)

PortT

imer

EventRoute

Port

EventHandler

Animator

Page 11: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

THE VMTS TRANSFORMATION DEBUGGER

Part II.

Page 12: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Graph rewritingRewriting rule

Host graph

Page 13: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

VMTS model transformation engine Graph rewriting-based approach

Rewriting rules Searching for graph patterns (LHS graph) Replacing matches with a substitue pattern (RHS)

Control sequence Visual Control Flow Language

Rule application Conditional branching Exhaustive rule application Parameter passing between rules

Page 14: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Model transformation debugger Goals

Visualization of input and output models

Animating the Control Flow model

Visualizing the executed rewriting rule

Continuous and step-by-step execution, breakpoints, jumping in the Control Flow

Online editing of input and output models

Page 15: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Model transformation debugger Event handler model

Wrapping the transformation engine

Initialize

EH_GT

PortGT

ProcessNextCFEdge

ProcessStartNode

Matching

ApplyCurrentMatch

ApplyInternalCausalities

ApplyInternalCausality

Initialized

PreNextCFEdge

PostNextCFEdge

PreStartNode

PostStartNode

PreDecision

PreEndNode

PreRuleNode

PreInitMatch

PreMatching

PreApplyMultipleMatch

PreApplyCurrentMatch

PreInternalCausalities

PreInternalCausality

PostInternalCausality

PostInternalCausalities

PostApplyCurrentMatch

PostApplyMultipleMatch

PostRuleNode

AgsiCFEdge

InternalCausalityResult

AgsiCFEndNode

TrafoOutputPlaces

AgsiInternalCausality

IAgsiCFNode

AgsiRuleExecutionResults

Page 16: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Model transformation debugger High-level animation model

Event handlers UI, GT, Timer

Animators GT, Highlight,

hotkey E

H_U

I (…

)

E

SIM_GT

PortModels PortLayout PortPeripher PortViews PortGT PortTimer

EH

_GT

(…)

EH

_Tim

er (…)

Por

tMod

els

Por

tLay

out

Por

tPer

iphe

rP

ortV

iew

s

PortG

TP

ort

SIM_GT

PortPeripherPortViews PortGT

SIM_Shortcut

PortPeripher PortTimer

HighlightGT

Page 17: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Model transformation debugger State machine model (SIM_GT)

1) Init

2) Idle

3) Process start

4) Process edge Breakpoint

5) Process rule node

6) Decision node

7) End node

PortGT PortViews PortModels PortLayout PortTimer

Initializing

ApplyLayout

OpenHostAndCF

GetCFDiagram

GetHostDiagram

GetWindowContent

ProcessingStart

HighlightStartNode

Executing

ShowResults

ApplyCurrentMatch

HighlightMatch

HighlightEdge HighlightDecisionProcessEndNode

HighlightRuleNode

CheckBreakpoint

ApplyBreakpointGetNewCFEdge ProcessEdge

(1)

(2)

(3)

(5)

(4)

(6)(7)

Page 18: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Debugger – in action

Page 19: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Summary

PortPN PortTimer PortViews PortModels

GetDiagramView Default

Selecting

GettingView

Highlighting

Firing

[no fireable transitions]

PortPN:EventGetFireableTransition

[fireable transition]

PortViews:EventGetView

[PortViews:EventGetView_]

PortViews:EventHighlight

[PortTimer:Tick]

[PortTimer:Tick]

PortPN:EventFire

PortViews:UnHighlight

EH

_UI (

…)

PNAnimator

PortModels PortViews PortPN PortTimer

Por

tMo

dels

Po

rtV

iew

s

EH

_PetriN

et (…)

PortP

N

EH

_Tim

er (…)

PortT

imer

Initialize

EH_GT

PortGT

ProcessNextCFEdge

ProcessStartNode

Matching

ApplyCurrentMatch

ApplyInternalCausalities

ApplyInternalCausality

Initialized

PreNextCFEdge

PostNextCFEdge

PreStartNode

PostStartNode

PreDecision

PreEndNode

PreRuleNode

PreInitMatch

PreMatching

PreApplyMultipleMatch

PreApplyCurrentMatch

PreInternalCausalities

PreInternalCausality

PostInternalCausality

PostInternalCausalities

PostApplyCurrentMatch

PostApplyMultipleMatch

PostRuleNode

AgsiCFEdge

InternalCausalityResult

AgsiCFEndNode

TrafoOutputPlaces

AgsiInternalCausality

IAgsiCFNode

AgsiRuleExecutionResults

Animator state machineHigh level animation model

Event handler modelEvent handler

implementation

Animated model

.

Animation engine

apply

gen.

ref.

EN

VIR

ON

ME

NT

.

Domain knowledge and simulation engines

Page 20: Visual Specification of a DSL Processor Debugger Tamás Mészáros and Tihamér Levendovszky Budapest University of Technology and Economics

Thank you for your attention!

http://vmts.aut.bme.hu