virtual memory
DESCRIPTION
Virtual Memory. Outline. Virtual Space Address translation Accelerating translation with a TLB Multilevel page tables Different points of view Suggested reading: 10.1~10.6. TLB: Translation lookaside buffers. 10.1 Physical and Virtual Addressing. Physical Addressing. - PowerPoint PPT PresentationTRANSCRIPT
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Virtual Memory
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Outline
• Virtual Space• Address translation• Accelerating translation
– with a TLB– Multilevel page tables
• Different points of view• Suggested reading: 10.1~10.6
TLB: Translation lookaside buffers
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10.1 Physical and Virtual Addressing
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Physical Addressing
• Attributes of the main memory– Organized as an array of M contiguous byte-
sized cells– Each byte has a unique physical address (PA)
started from 0
• physical addressing – A CPU use physical addresses to access memory
• Examples– Early PCs, DSP, embedded microcontrollers, and
Cray supercomputers
Contiguous: 临近的
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Physical Addressing
Figure 10.1 P693
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Virtual Addressing
• Virtual addressing
– the CPU accesses main memory by a virtual
address (VA)
• The virtual address is converted to the appropriate
physical address
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Virtual Addressing
• Address translation – Converting a virtual address to a physical one– requires close cooperation between the CPU
hardware and the operating system• the memory management unit (MMU)
– Dedicated hardware on the CPU chip to translate virtual addresses on the fly
• A look-up table – Stored in main memory – Contents are managed by the operating system
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8Figure 10.2 P694
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10.2 Address Space
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Address Space
• Address Space
– An ordered set of nonnegative integer
addresses
• Linear Space
– The integers in the address space are
consecutive
• N-bit address space
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Address Space
• K=210(Kilo), M=220(Mega), G=230(Giga), T=240(Tera), P=250(Peta), E=260(Exa)
#virtual address bits (n)
#virtual address (N)
Largest possible virtual address
8
64K
32
256T
64
256 255
16 64K-1
4G 4G-1
48
16E 16E-1
256T-1
Practice Problem 10.1 P695
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Address Space
• Data objects and their attributes
– Bytes vs. addresses
• Each data object can have multiple
independent addresses
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10.3 VM as a Tool for Caching
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Using Main Memory as a Cache P695
DRAMSRAM Disk
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10.3.1 DRAM Cache Organization
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Using Main Memory as a Cache
• DRAM vs. disk is more extreme than SRAM vs. DRAM– Access latencies:
• DRAM ~10X slower than SRAM
• Disk ~100,000X slower than DRAM
– Bottom line: • Design decisions made for DRAM caches driven by
enormous cost of misses
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Design Considerations
• Line size?– Large, since disk better at transferring large
blocks
• Associativity?– High, to minimize miss rate
• Write through or write back?– Write back, since can’t afford to perform small
writes to diskWrite back: defers the memory update as long as possible by writing the updated block to memory only when it is evicted from the cache by the replacement algorithm.
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10.3.2 Page Tables
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Page
• Virtual memory
– Organized as an array of contiguous byte-sized
cells stored on disk conceptually.
– Each byte has a unique virtual address that
serves as an index into the array
– The contents of the array on disk are cached in
main memory
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Page P695
• The data on disk is partitioned into blocks
– Serve as the transfer units between the disk
and the main memory
– virtual pages (VPs)
– physical pages (PPs)
• Also referred to as page frames
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Page Attributes P695
• 1) Unallocated:
– Pages that have not yet been allocated (or
created) by the VM system
– Do not have any data associated with them
– Do not occupy any space on disk.
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Page Attributes
• 2) Cached:
– Allocated pages that are currently cached in
physical memory.
• 3) Uncached:
– Allocated pages that are not cached in physical
memory.
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PageFigure 10.3 P696
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Page Table
• Each allocate page of virtual memory has
entry in page table
• Mapping from virtual pages to physical pages
– From uncached form to cached form
• Page table entry even if page not in memory
– Specifies disk address
• OS retrieves information
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Page Table
Data
243
17
105
•••
0:
1:
N-1:
X
Object Name
Location
•••
D:
J:
X: 1
0
On Disk
“ Cache”Page Table
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Page Table
Memory residentpage table
(physical page or disk address) Physical Memory
Disk Storage(swap file orregular file system file)
Valid
1
1
111
1
10
0
0
Virtual PageNumber
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10.3.3 Page Hits
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Page HitsFigure 10.5 P698
Memory
Address Translation: Hardware converts virtual addresses to physical addresses via an OS-managed lookup table (page table)
CPU
0:1:
N-1:
0:1:
P-1:
Page Table
Disk
VirtualAddresses
PhysicalAddresses
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10.3.4 Page Faults
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Page Faults
• Page table entry indicates virtual address
not in memory
• OS exception handler invoked to move
data from disk into memory
– current process suspends, others can resume
– OS has full control over placement, etc.
Suspend: 悬挂
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Page Faults
• Swapping or paging• Swapped out or paged out (from DRAM to Disk)• Demand paging (Waiting until the last moment to
swap in a page, when a miss occurs)
CPU
Memory
Page Table
Disk
VirtualAddresses
PhysicalAddresses
CPU
Memory
Page Table
Disk
VirtualAddresses
PhysicalAddresses
Before fault After fault
Figure 10.6 P699 Figure 10.7 P699
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Servicing a Page Fault
• Processor Signals Controller– Read block of
length P starting at disk address X and store starting at memory address Y
diskDiskdiskDisk
Memory-I/O busMemory-I/O bus
ProcessorProcessor
CacheCache
MemoryMemoryI/O
controller
I/Ocontroller
Reg
(1) Initiate Block Read
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Servicing a Page Fault
• Read Occurs– Direct Memory
Access (DMA)– Under control
of I/O controller
diskDiskdiskDisk
Memory-I/O busMemory-I/O bus
ProcessorProcessor
CacheCache
MemoryMemoryI/O
controller
I/Ocontroller
Reg
(2) DMA Transfer
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Servicing a Page Fault
• I / O Controller Signals Completion– Interrupt
processor– OS resumes
suspended process
diskDiskdiskDisk
Memory-I/O busMemory-I/O bus
ProcessorProcessor
CacheCache
MemoryMemoryI/O
controller
I/Ocontroller
Reg (3) Read Done
Resumes: 再继续 , 重新开始
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10.3.5 Allocating Pages
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Allocating Pages P700
• The operating system allocates a new page of virtual memory, for example, as a result of calling malloc.
Figure 10.8 P700
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10.3.6 Locality to the Rescue Again
Rescue: 解救
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Locality P700
• The principle of locality promises that at any point in time they will tend to work on a smaller set of active pages, known as working set or resident set.
• Initial overhead where the working set is paged into memory, subsequent references to the working set result in hits, with no additional disk traffic.
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Locality-2 P700
• If the working set size exceeds the size of physical memory, then the program can produce an unfortunate situation known as thrashing, where the pages are swapped in and out continuously.
Thrash: 鞭打
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10.4 VM as a Tool for Memory Management
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A Tool for Memory Management
• Separate virtual address space
– Each process has its own virtual address space
• Simplify linking, sharing, loading, and
memory allocation
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A Tool for Memory Management
Virtual Address Space for Process 1:
Physical Address Space (DRAM)
VP 1
VP 2
PP 2
Address Translation0
0
N-1
0
N-1M-1
VP 1
VP 2
PP 7
PP 10
(e.g., read/only library code)
...
...
Virtual Address Space for Process 2:
Figure 10.9 P701
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10.4.1 Simplifying Linking
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A Tool for Memory Management
kernel virtual memory
Memory mapped region for shared libraries
runtime heap (via malloc)
program text (.text)
initialized data (.data)
uninitialized data (.bss)
stack
forbidden
%esp
memory invisible to user code
the “brk” ptr
Linux/x86
process
memory
image
Figure 10.10 P702
0xc00000000xbfffffff
0x40000000
0x08048000
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10.4.2 Simplifying Sharing
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Simplifying Sharing
• In some instances, it is desirable for processes to
share code and data.
– The same operating system kernel code
– Make calls to routines in the standard C library
• The operating system can arrange for multiple
process to share a single copy of this code by
mapping the appropriate virtual pages in different
processes to the same physical pages
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10.4.3 Simplifying Memory Allocation
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Simplifying Memory Allocation
• A simple mechanism for allocating
additional memory to user processes.
• Page table work.
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10.4.4 Simplifying Loading
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Simplifying Loading
• Load executable and shared object files
into memory.
• Memory mapping……mmap
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10.5 VM as a Tool for Memory Protection
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A Tool for Memory Protection
• Page table entry contains access rights
information
– hardware enforces this protection (trap into OS
if violation occurs)
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A Tool for Memory Protection
Page Tables
Process i:
Physical AddrRead? Write?
PP 9Yes No
PP 4Yes Yes
XXXXXXX No No
VP 0:
VP 1:
VP 2:•••
•••
•••
Process j:
0:1:
N-1:
Memory
Physical AddrRead? Write?
PP 6Yes Yes
PP 9Yes No
XXXXXXX No No•••
•••
•••
VP 0:
VP 1:
VP 2:
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A Tool for Memory Protection
Figure 10.11 P704
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10.6 Address Translation
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Address Translation
Processor
HardwareAddr TransMechanism
faulthandler
MainMemory
Secondary memorya
a'
page fault
physical addressOS performsthis transfer(only if miss)
virtual address part of the on-chipmemory mgmt unit (MMU)
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Address Translation Figure 10.12 P705
• Parameters– P = 2p = page size (bytes). – N = 2n = Virtual address limit– M = 2m = Physical address limit
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Address Translation P705
virtual page number page offset virtual address
physical page number page offset physical address
0p–1
address translation
pm–1
n–1 0p–1p
Notice that the page offset bits don't change as a result of translation
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Address Translation via Page Table
virtual page number (VPN) page offset
virtual address
physical page number (PPN) page offset
physical address
0p–1pm–1
n–1 0p–1p
page table base register(PTBR)
if valid=0then pagenot in memory
valid physical page number (PPN)access
VPN acts astable index
Figure 10.13 P705
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Page HitsFigure 10.14 (a) P706
VA: virtual address. PTEA: page table entry address.
PTE: page table entry. PA: physical address.
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Page FaultsFigure 10.14 (b) P706
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10.6.1 Integrating Caches and VM
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Integrating Caches and VM
CPU Trans-lation
Cache MainMemory
VA PA miss
hit
data
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Integrating Caches and VM
• Most Caches “Physically Addressed”– Accessed by physical addresses– Allows multiple processes to have blocks in
cache at same time– Allows multiple processes to share pages– Cache doesn’t need to be concerned with
protection issues• Access rights checked as part of address
translation
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Integrating Caches and VM
• Perform Address Translation Before Cache Lookup– But this could involve a memory access itself
(of the PTE)– Of course, page table entries can also become
cached
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66Figure 10.15 P708
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10.6.2 Speeding up Address Translation with a TLB
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Speeding up Translation with a TLB
• “ Translation Lookaside Buffer” (TLB)– Small hardware cache in MMU– Maps virtual page numbers to physical page
numbers
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69Figure 10.17 (a) P709
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Speeding up Translation with a TLB
Figure 10.16 P708
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Speeding up Translation with a TLB
virtual addressvirtual page number page offset
physical address
n–1 0p–1p
valid physical page numbertag
valid tag data
data=
cache hit
tag byte offsetindex
=
TLB hit
TLB
Cache
. ..
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• TLB– 16 entries– 4-way associative
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPN
TLBITLBT
Set Tag PPN Valid Tag PPN Valid Tag PPN Valid Tag PPN Valid
0 03 – 0 09 0D 1 00 – 0 07 02 1
1 03 2D 1 02 – 0 04 – 0 0A – 0
2 02 – 0 08 – 0 06 – 0 03 – 0
3 07 – 0 03 0D 1 0A 34 1 02 – 0
Simple Memory System TLB
Figure 10.21 (a) P712
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Address Translation Example P714
Virtual Address 0x03D413 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPN
00101011110000
VPN: 0x0f TLBI: 0x03 TLBT: 0x03 TLB Hit? yes Page Fault?
No
PPN: 0x0D VPO: 0x14 PA: 0x354
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
001010101100
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Simple Memory System Cache
• Cache– 16 lines– 4-byte line size– Direct mapped
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Simple Memory System Cache
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
Idx Tag Valid
B0 B1 B2 B3 Idx Tag Valid
B0 B1 B2 B3
0 19 1 99 11 23 11 8 24 1 3A 00 51 89
1 15 0 – – – – 9 2D 0 – – – –
2 1B 1 00 02 04 08 A 2D 1 93 15 DA 3B
3 36 0 – – – – B 0B 0 – – – –
4 32 1 43 6D 8F 09 C 12 0 – – – –
5 0D 1 36 72 F0 1D D 16 1 04 96 34 15
6 31 0 – – – – E 13 1 83 77 1B D3
7 16 1 11 C2 DF 03 F 14 0 – – – –
Figure 10.21 (c) P713
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Address Translation Example P714
PA: 0x354
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
001010101100
Offset: 0x0 CI: 0x05 CT: 0x0D Hit? Yes Byte: 0x36
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10.6.3 Multi Level Page Tables
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Multi-Level Page Tables
• Given:– 4KB (212) page size– 32-bit address space– 4-byte PTE
• Problem:– Would need a 4 MB page table!
• 220 *4 bytes
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Multi-Level Page Tables
• Common solution
– multi-level page tables
– e.g., 2-level table (P6)
• Level 1 table: 1024 entries,
each of which points to a
Level 2 page table.
• Level 2 table: 1024
entries, each of which
points to a page
Level 1
Table
...
Level 2
Tables
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Multi-Level Page Tables
Figure 10.18 P710
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Multi-Level Page Tables
Figure 10.19 P711
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10.6.4 Putting it Together: End-to-End Address Translation
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Simple Memory System Example
• Addressing– 14-bit virtual addresses– 12-bit physical address– Page size = 64 bits
13 12 11 10 9 8 7 6 5 4 3 2 1 0
11 10 9 8 7 6 5 4 3 2 1 0
VPO
PPOPPN
VPN
(Virtual Page Number) (Virtual Page Offset)
(Physical Page Number) (Physical Page Offset)
Figure 10.20 P712
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Simple Memory System Page Table
• Only show first 16 entries
VPN PPN Valid VPN PPN Valid
00 28 1 08 13 1
01 – 0 09 17 1
02 33 1 0A 09 1
03 02 1 0B – 0
04 – 0 0C – 0
05 16 1 0D 2D 1
06 – 0 0E 11 1
07 – 0 0F 0D 1
Figure 10.21 P712 (b)
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Address Translation Example P714
Virtual Address 0x03D413 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPN
00101011110000
VPN: 0x0f Page Fault? No
PPN: 0x0D VPO: 0x14 PA: 0x354
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
001010101100