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Virtex Proto Board

originallyplanned to follow

my last piece with anarticle about how to de-

sign with multipliers. Well, toshorten the story, the software I in-tended to use in designing some of themultiplier examples didn’t work.

The longer version of the story isthat, because I was working on aproject, I needed to upgrade my FPGAdesign software to the latest andgreatest version. Of course, because itruns under Windows, this doesn’talways work the wayyou think it will. Suchwas the case with thenew installation, so Idecided to downgradeto the original version.Unfortunately, itdoesn’t work at allnow. At this point, Ineeded to uninstallboth versions by re-moving all traces of.dlls, executables, envi-ronment variables, andregistry entries, or justresort to reinstalling

I

Windows. I’m sure you’ve been thereat one time or another. Somedaythey’ll bring out these design toolsunder Linux. At least I can dream.

My design environment underWindows is a mess, but the Linuxenvironment on my laptop still workswell, enabling me to write this ar-ticle. This month, I’ll talk about theVirtex prototyping board I’m using forthe project that got me in trouble—the Virtual Workbench 300 (VW-300)from the Virtual Computer Corpora-tion (VCC).

THE BOARDThe board is a prototyping board

for the Xilinx Virtex series FPGA.Virtex is Xilinx’s high-end FPGA,boasting densities of up to one milliongates (more in the Virtex-E). Remindme to write a piece about how tocompute realistic gate densities inFPGAs that actually mean something.

Virtex has some nice architecturalfeatures that make it suitable for largesystem-on-a-chip designs that include32-bit processor cores, peripherals,and high-performance digital signalprocessing. There are several types ofmemory from SelectRAM that can beused for small register files (i.e.,BlockRAM), which are large 4-Kb

Although Ingohad originallyplanned to followup his last articleabout multipliers,he ran into a littleproblem. OK, soit was a big prob-lem. But, that’s toour benefit.

LEARNINGTHE ROPESIngo Cyliax

Photo 1— Look at all this neat stuff on such a small board.

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RAM modules available on-chip.BlockRAMs are highly flexible be-cause they can be configured as eithersingle- or dual-ported memory witheither 1 or 16-bit wide ports. Otherthan that, they are of the look-uptable-based CLB architecture, withplenty of routing resources to connectthem with fast carry support betweenadjacent CLBs.

The I/O on Virtex chips is perhapsthe best feature. There are severalbanks of I/O, each bank powered byits own I/O power supply and inputreference voltage. With the appropri-ate power supplies, various signalingstandards can be implemented. Table1 shows the supported types.

Of course, the inputs are also 5-Vtolerant if it’s selected and have pro-grammable pull up/pull down andweak keepers.

To make interfacing even easier,Virtex has several delay locked loops(DLL). These can be used to matchinternal clock signals to externalclocks in order to reduce the effects ofon/off chip latencies at high clockrates.

NO RE-FLOW OVEN?Virtex FPGAs are available in BGA

packages. BGA packages are the pack-age of choice for large chips thesedays. Of course, like many new pack-age styles, they are harder to mountwhen prototyping or building one-offs.BGAs have small solder balls on thebottom of the chip that match up

Table 1—Here is a list of all the I/O interfaces that can be supported by Virtex. Each bank’s VIO and VREF powersupplies can be wired to various voltages to help implement these.

Standard Input Ref. Output Source TerminationVoltage Voltage Voltage

LVTTL N/A 3.3 N/ALVCMOS N/A 2.5 N/APCI N/A 3.3 N/AGTL 0.8 N/A 1.2GTL+ 1.0 N/A 1.5HSTL Class I 0.75 1.5 1.5HSTL Class III 0.75 1.5 1.5HSTL Class IV 0.75 1.5 1.5SSTL3 Class I/II 1.5 3.3 1.5SSTL2 Class I/II 1.125 2.5 1.125CTT 1.5 3.3 1.5AGP 1.32 3.3 N/A

with small solder pads on the PCB.The BGAs are placed on the PCB andthen need to be heated in an oven forthe solder balls to melt and bond withthe solder pads. Of course everyonehas a re-flow oven these days.

Because I don’t have a re-flow ovenhandy and didn’t have enough time totrack down a facility that couldhandle mounting these packages, Ihad to buy a prototype board for thisproject. The project, incidentally, wasdemonstrating a 32-bit processor coreI developed for my day job. I needed aVirtex board with a large enough chipand some external memory pre-wired,along with a prototyping area for allthe extra stuff.

After searching Optimagic’s website, which is great for FPGA re-sources, I found that the VW-300 fitthe bill, so I ordered one.

Besides the Virtex chip, the VW-300 has a lot of memory, a clock, andconnector resources. In addition, thereare LEDs, switches, push buttons, 8-digit alphanumeric LED display, andother neat stuff all on an 5.5″ × 5.5″board (see Photo 1).

There are three memories on theVW-300. A 256K × 8-bit flash memoryis used to store startup configurationfor the FPGA. From the factory, it hasa demo that scrolls continual advertis-ing over the alphanumeric display. It’snice to have something running soyou can make sure everything is OK(after you’ve taken it out of the boxand built a power supply). The flash

memory can be reprogrammed byremoving it from its socket (it’sPLCC footprint flash memory) andprogramming in a programmer. ACPLD is used to interface the flashmemory to the Virtex part to performXilinx’s SelectMAP partialreconfiguration protocol. Because theCPLD is flash memory-based, I sup-pose it could be reprogrammed toperform other functions.

BURST MODEBesides the flash memory, the

VW-300 also has a 256K × 18-bitsynchronous burst mode fast staticRAM (SBRAM). This is a memorymodule normally used for off-chip L2processor cache and supports burst

mode operations. The cycle time ofthe memory installed is 6 ns (166MHz), which means it can transfer ata peak rate of over 332 MBps. Becausethe SRAM is fast but not too large, an80-ns 1M x 16 x 4 SDRAM is alsoincluded onboard.

The SRAM and DRAM memoriesare devices attached to the FPGA. Byitself, the Virtex does nothing specialwith the memories. You would haveto design in a SRAM or DRAM con-troller into the design loaded on theFPGA in order to use the memory. Inthis project, you can use the SDRAMas traditional program and datamemory, and the SRAM as fast buffermemory or cache memory. The Xilinxweb site has cores that can be used tocontrol burst mode SRAM andSDRAM in a Virtex design.

Because the Virtex also has on-chipmemory block and small look-uptable-based register files, you can usea full spectrum of memory hierar-chy—from small single- and dual-ported register files (SelectRAM)running at sub-nanosecond accesstimes, to larger memory block(BLOCKRAM) running at less than 5-ns access times. To get to off-chipmemory, you have to figure the la-tency it takes to get in and out of thechip and protocol issues, in additionto the access times of the memory.

For example, to access SBRAM youhave to send the address and wait forthe data to burst out of the memorysequentially. Although the peak burst

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buffers, which cancause fights if notproperly designed,you can actuallyoverheat the chip atnormal operatingtemperatures. Atemperature sensorcan be used to de-tect these condi-tions and shutdown

the chip if the temperature exceedssafe levels. I suppose a boring applica-tion of a temperature sensor might beto drive a variable speed fan to coolthe chip optimally.

If you’re building systems on achip, you might want to use serialcommunication channels to talk withother computers or a terminal. Thisboard includes a TTL to RS-232 leveladapter and a DE-9 connector to per-form this. For example, this projectuses an RS-232 port for a backgrounddebugger type interface.

Building a UART in FPGA is nothard. I used to teach students in un-dergraduate hardware labs to do this.I’ll cover designing UARTs in a laterarticle.

If you like switches and lights, ithas those as well. There is an 8-posi-tion DIP switch and eight surface-mount LEDs you can read and light upwith the FPGA. There are also fourpushbutton switches. However, theneatest peripheral on this board is theInfineon IPD2133 8-character 5 × 7dot matrixaphanumeric display.

To the FPGA, thedisplay looks like asmall SRAM device.There is an addressbus and a data bus.The simplest way touse it is to addressone of the eight dig-its (address 0–7) andwrite a 7-bit ASCIIcode to it. The chipconverts the ASCIIcode using an inter-nal character ROMand displays it on the5 × 7 array for thatdigit. Not bad. Figure2 shows a block

rate is fast at 166 MHz, the total accesstime to get four words is at least fivecycles. Figure 1 shows timing diagramsfor SBRAM access. In contrast,BlockRAM works as true random ac-cess memory, not in burst mode. In anycase, with this board you have all theoptions covered.

MORE OPTIONSThe VW-300 also has several clock-

ing options. It has two Dallas Semicon-ductor DS1073 econo-oscillators (100MHz and 66 MHz). These can be set upto divide the oscillator frequency bytwo, which is the default. In addition tothese oscillators, the board has a Cy-press ICD2053B adjustable oscillator,which can be programmed using a serialprotocol either from the FPGA or exter-nally. By default, this oscillator runs at16 MHz. As if this isn’t enough, thereis also an extra oscillator site whereyou can install your own oscillatormodule.

Another neat feature is the tempera-ture sensor module. This is a Max1617die temperature sensor. The Virtexprovides a diode-based die temperatureoutput that works with this sensormodule. The module converts the tem-perature reading and lets you read thetemperature through a SMBUS inter-face, either by the FPGA or externally.

Measuring the die temperature isuseful for several reasons. BecauseFPGAs are user programmable, comput-ing power consumption (and powerdissipation) is complex. During systemtesting, you can use the die temperature,and by knowing the ambient air tem-perature as well as heat transfer coeffi-cients for the package and current airhumidity, you can estimate the powerconsumption and power dissipation.

Also, because this type of Virtex hasso many flip-flops and internal tristate

CLK

*W

*E

SA

D(An) D(An+1) D(An+2) D(An+4)DQ

An

diagram of the internal display.You can use this display to show a

hexadecimal representation of inter-nal registers, assuming you add logicto your design to use the display. Youcan also use it to provide a smallscrolling text console for your project.

Besides onboard peripherals, thereare a variety of headers and connec-tors that can be used to interface ex-ternal modules, devices, and logicanalyzer inputs to the Virtex on thisboard. In particular, there are severalmezzanine connectors for third partyCODEC modules from Insight, aswell as A/D and D/A Omnibus mod-ules from Innovative Integration. Allof the I/Os are documented in theuser manual, and pin configurationfiles for the FPGA can be downloadedfrom VCC’s web site.

There are several configurationsthat are supported on this board forthe Virtex chip. I already mentionedthe flash PROM for doing SelectMAPconfiguration, and there are jumpersand headers for serial PROM, JTAG,Xchecker, and MultiLINX configura-tion. The manual, schematics, anddatasheet for some of the componentsare available on the web site. Afteryou have registered for your board,everything you’d expect from aprototyping board opens up to you.

UPON ARRIVALAfter the board arrived, it became

obvious that I was missing some-

Figure 1 —Here you can see the timing diagrams for SBRAM access.

Photo 2 —After the voltages were adjusted and everything was hooked up, I wasready to try it out.

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thing. It turns out thatthe Virtex chip is a 2.5-V core logic device.That means all of theinternal logic on thischip operates from a2.5-V power supply.Virtex-E FPGA coreactually runs at 1.8 V.Furthermore, most ofthe memories and pe-ripherals work at 3.3 Vand some, like the RS-232 converter, run froma 5-V supply. However,there are no onboardregulators. VCC does have a matchingpower supply available for this boardthat takes care of it all.

Building power supplies isn’trocket science (for the most part), so Ifigured it shouldn’t be a big deal. Es-pecially, because voltage regulatorsdon’t come in BGA packages, and Ican solder these parts myself. Takinga quick survey however, I discoveredthat 3.3-V regulator ICs are readilyavailable and 2.5-V regulators areharder to come by. I settled on usingLinear Technologies’ LT-1587. Thesedevices are available in varied fixedvoltages, as well as an adjustable ver-sion. I chose the adjustable versionthat is available in three terminal TO-220 packages and quickly cobbled up apower supply on a perforated circuitboard that matches the schematics in

Figure 3. Photo 2 shows what thislooks like.

Because the VIN/VOUT differentialhas to be between 1.5 and 5.75 V, Ichose a small 5-V switcher that Iscrounged up from an old Macintosh.After carefully adjusting the two volt-ages (3.3 and 2.5 V), I hooked up ev-erything you see in Photo 2 and triedit for the first time. It was nice to seethe demo design come up the firsttime. The compiled project wasdownloaded through an Xcheckercable and everything came up as ex-pected with the board.

Although I’m typically a strongadvocate of building your own stuff,it’s nice to be able to use off-the-shelfprototyping boards. Usually when Ibuild my own boards, I spend a sig-nificant amount of time debugging

my aspect of the design. Inthis case, it was definitely atimesaver, especially becauseit will probably take severalattempts to fine-tune anyBGA-based home assemblytechniques. I did figure outthat my kitchen stoveachieves re-flow temperaturesin “clean” mode. Apparentlythe normal thermostaticcontrol is disabled in thismode, and the oven runs upto its maximum temperature.At this point, however, I’mhesitant to try a re-flow witha $300 FPGA in my kitchenoven. If I take on such a taskin the future, I’ll be sure tolet you know whether or notI’m successful. I

OSC

Chal: RAMDecode

div 32 div 7

div 3

RowDrivers

div 128

Chal:RAM

D LatchROMword

decode

Chal:decode

Chal:decode

ROM

ODCRAM

Data bus

LT1584

LT1584

3.3v

220µF

5v

5v

125

125

(124.3)

220µF

(203.8)

10µF

2.5v

10µF

VOUT = VREF (1+ R2/R1) + Ladj R2VREF = 1.25 VLadj. = 55µA Circuit Cellar, the Magazine for Computer Applications.

Reprinted by permission. For subscription information,call (860) 875-2199, subscribe@circuitcellar.com orwww.circuitcellar.com/subscribe.htm.

Figure 2 —The internal display has an address bus and data bus and provides you with manyoptions for use.

SOURCESVirtual Workbench 300 (VW-300)Virtual Computer Corporation(818) 342-8294Fax: (818) 342-0240www.vcc.com

OptiMagic’s Programmable LogicJump StationOptimagic(831) 687-0415Fax: (408) 701-7007www.optimagic.com

Figure 3 —Here you can see a schematic of the power supply Iquickly threw together.

Ingo Cyliax is the Sr.Hardware Engineer atDerivation SystemsInc. (DSI) where hedesigns and buildsembedded systems andhardware components.DSI is the leader informally synthesizedFPGA cores and spe-cializes in embeddedJava technology. Ingohas been writing onvarious topics rangingfrom real-time operat-ing systems to nuts

and bolts hardware issues for severalyears.