-- (this is a VHDL comment) -- import std_logic from the IEEE librarylibrary IEEE;use IEEE.std_logic_1164.all; -- this is the entityentity ANDGATE is port ( I1 : in std_logic; I2 : in std_logic; O : out std_logic);end entity ANDGATE; -- this is the architecturearchitecture RTL of ANDGATE isbegin O <= I1 and I2;end architecture RTL;

D-type flip-flops

The D-type flip-flop samples an incoming signal at the rising (or falling) edge of a clock. This example has an asynchronous, active-high reset, and samples at the rising clock edge.

DFF : process(RST, CLK)begin if RST = '1' then Q <= '0'; elsif rising_edge(CLK) then Q <= D; end if;end process DFF;

Another common way to write edge-triggered behavior in VHDL is with the 'event' signal attribute. A single apostrophe has to be written between the signal name and the name of the attribute.

DFF : process(RST, CLK)begin if RST = '1' then Q <= '0'; elsif CLK'event and CLK = '1' then Q <= D; end if;end process DFF;

Example: a counter

The following example is an up-counter with asynchronous reset, parallel load and configurable width. It demonstrates the use of the 'unsigned' type, type conversions between 'unsigned' and 'std_logic_vector' and VHDL generics. The generics are very close to arguments or templates in other traditional programming languages like C++.

library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all; -- for the unsigned type entity COUNTER is generic ( WIDTH : in natural := 32); port ( RST : in std_logic; CLK : in std_logic; LOAD : in std_logic; DATA : in std_logic_vector(WIDTH-1 downto 0); Q : out std_logic_vector(WIDTH-1 downto 0));end entity COUNTER; architecture RTL of COUNTER is signal CNT : unsigned(WIDTH-1 downto 0);begin process(RST, CLK) is begin if RST = '1' then CNT <= (others => '0'); elsif rising_edge(CLK) then if LOAD = '1' then CNT <= unsigned(DATA); -- type is converted to unsigned else CNT <= CNT + 1; end if; end if; end process; Q <= std_logic_vector(CNT); -- type is converted back to std_logic_vectorend architecture RTL;

In electronics, a hardware description language or HDL is a specialized computer language used to program the structure, design and operation of electronic circuits, and most commonly, digital logic circuits.A hardware description language enables a precise, formal description of an electronic circuit that allows for the automated analysis, simulation, and simulated testing of an electronic circuit. It also allows for the compilation of an HDL program into a lower level specification of physical electronic components, such as the set of masks used to create an

integrated circuit.A hardware description language looks much like a programming language such as C; it is a textual description consisting of expressions, statements and control structures. One important difference between most programming languages and HDLs is that HDLs explicitly include the notion of time.HDLs form an integral part of electronic design automation systems, especially for complex circuits, such as microprocessors

VHDL Operators Highest precedence first, left to right within same precedence group, use parenthesis to control order. Unary operators take an operand on the right. "result same" means the result is the same as the right operand. Binary operators take an operand on the left and right. "result same" means the result is the same as the left operand.** exponentiation, numeric ** integer, result numericabs absolute value, abs numeric, result numericnot complement, not logic or boolean, result same

* multiplication, numeric * numeric, result numeric/ division, numeric / numeric, result numericmod modulo, integer mod integer, result integerrem remainder, integer rem integer, result integer

+ unary plus, + numeric, result numeric- unary minus, - numeric, result numeric

+ addition, numeric + numeric, result numeric- subtraction, numeric - numeric, result numeric& concatenation, array or element & array or element,result array

sll shift left logical, logical array sll integer, result samesrl shift right logical, logical array srl integer, result samesla shift left arithmetic, logical array sla integer, result samesra shift right arithmetic, logical array sra integer, result samerol rotate left, logical array rol integer, result sameror rotate right, logical array ror integer, result same

= test for equality, result is boolean/= test for inequality, result is boolean< test for less than, result is boolean<= test for less than or equal, result is boolean> test for greater than, result is boolean>= test for greater than or equal, result is boolean

and logical and, logical array or boolean, result is sameor logical or, logical array or boolean, result is samenand logical complement of and, logical array or boolean, result is same

nor logical complement of or, logical array or boolean, result is samexor logical exclusive or, logical array or boolean, result is samexnor logical complement of exclusive or, logical array or boolean, result is same