Islamic University – Gaza Engineering Faculty

Department of Computer Engineering

ECOM 4011: VHDL Discussion

CH# 4

CONCURRENT SIGNAL ASSIGNMENT

STATEMENTS OF VHDL

Eng. Ahmed K. Aldali

October,2014

Y = crtl(1).ctrl(0).(x1&x1) + crtl(1).ctrl(0)'.(x0&x0)

+ crtl(1)'.ctrl(0).(x0&x1) + crtl(1)'.ctrl(0)'.(x1&x0)