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EEC 032 DIGITAL SYSTEM DESIGN USING VHDL UNIT I: Introduction to VHDL, reserve words, structures, modeling, objects, data type and operators, sequential statements and processes, sequential modeling and attributes, conditional assignment, concatenation and case, array loops and assert statements, subprograms. UNIT II: Digital System Design Automation– Abstraction Levels, System level design flow, RTL design flow, VHDL. RTL Design with VHDL – Basic structures of VHDL, Combinational circuits, Sequential circuits, Writing Test benches, Synthesis issues, VHDL Essential Terminologies VHDL Constructs for Structures and Hierarchy Descriptions – Basic Components, Component Instantiations, Iterative networks, Binding Alternatives, Association methods, generic Parameters, Design Configuration UNIT III: Concurrent Constructs for RT level Descriptions – Concurrent Signal Assignments, Guarded signal assignment Sequential Constructs for RT level Descriptions – Process Statement, Sequential WAIT statement, VHDL Subprograms, VHDL library Structure, Packaging Utilities and Components, Sequential Statements. VHDL language Utilities - Type Declarations and Usage, VHDL Operators, Operator and Subprogram overloading, Other TYPES and TYPE – related issues, Predefined Attributes UNIT IV: VHDL Signal Model – Characterizing hardware languages, Signal Assignments, Concurrent and Sequential Assignments, Multiple Concurrent Drivers Standard Resolution UNIT V: Hardware Cores and Models - Synthesis rules and styles, Memory and Queue Structures, Arithmetic Cores, Components with Separate Control and Data parts. Core Design Test and Testability - Issues Related to Design Test, Simple Test benches. TEXT BOOKS & REFERENCE BOOKS: 1. Z. Navabi, “VHDL-Modular Design and Synthesis of cores and Systems”, TMH – 3rd Edition. 2. R.D.M. Hunter, T. T. Johnson, “Introduction to VHDL” Spriger Publication, 2010. 3. C. H. Roth, “Digital System Design using VHDL”, PWS Publishing 4. Douglas Perry, “VHDL- Programming by examples”, MGH

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Page 1: vhdl syllabus

EEC 032 DIGITAL SYSTEM DESIGN USING VHDL

UNIT I:

Introduction to VHDL, reserve words, structures, modeling, objects, data type and operators, sequentialstatements and processes, sequential modeling and attributes, conditional assignment, concatenation andcase, array loops and assert statements, subprograms.

UNIT II:

Digital System Design Automation– Abstraction Levels, System level design flow, RTL design flow,VHDL. RTL Design with VHDL – Basic structures of VHDL, Combinational circuits, Sequentialcircuits, Writing Test benches, Synthesis issues, VHDL Essential Terminologies VHDL Constructs forStructures and Hierarchy Descriptions – Basic Components, Component Instantiations, Iterativenetworks, Binding Alternatives, Association methods, generic Parameters, Design Configuration

UNIT III:

Concurrent Constructs for RT level Descriptions – Concurrent Signal Assignments, Guarded signalassignment Sequential Constructs for RT level Descriptions – Process Statement, Sequential WAITstatement, VHDL Subprograms, VHDL library Structure, Packaging Utilities and Components,Sequential Statements. VHDL language Utilities - Type Declarations and Usage, VHDL Operators,Operator and Subprogram overloading, Other TYPES and TYPE – related issues, Predefined Attributes

UNIT IV:

VHDL Signal Model – Characterizing hardware languages, Signal Assignments, Concurrent andSequential Assignments, Multiple Concurrent Drivers Standard Resolution

UNIT V:

Hardware Cores and Models - Synthesis rules and styles, Memory and Queue Structures, ArithmeticCores, Components with Separate Control and Data parts. Core Design Test and Testability - IssuesRelated to Design Test, Simple Test benches.

TEXT BOOKS & REFERENCE BOOKS:

1. Z. Navabi, “VHDL-Modular Design and Synthesis of cores and Systems”, TMH – 3rd Edition.

2. R.D.M. Hunter, T. T. Johnson, “Introduction to VHDL” Spriger Publication, 2010.

3. C. H. Roth, “Digital System Design using VHDL”, PWS Publishing

4. Douglas Perry, “VHDL- Programming by examples”, MGH

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