VHDL Project II:VHDL Project II:Array MultiplierArray Multiplier

Matthew MurachMatthew Murach

Slides Available at: www.pages.drexel.edu/~

mjm46

Today’s AgendaToday’s Agenda

Finish up the processing element Finish up the processing element design design

Work on array multiplier Work on array multiplier design/layoutdesign/layout

Today’s quiz will be given in the last Today’s quiz will be given in the last 30 minutes of the lab period. The 30 minutes of the lab period. The quiz is timed and all quizzes will be quiz is timed and all quizzes will be collected at 11:00 am. collected at 11:00 am.

Recall from last time…Recall from last time… The array multiplier that we are The array multiplier that we are

designing involves the use of processing designing involves the use of processing elements (PE) to breakdown the task of elements (PE) to breakdown the task of multiplying an n-bit vector by a n-bit multiplying an n-bit vector by a n-bit vector. vector.

Using a serial approach much like the Using a serial approach much like the adder project the operation should take adder project the operation should take roughly roughly ~~n operations (slight larger)n operations (slight larger)

To design a high performance multiplier To design a high performance multiplier we can perform some operations in we can perform some operations in parallel rather then in serial.parallel rather then in serial.

Array Multiplier Layout 4x4Array Multiplier Layout 4x4

A(0)A(1)A(2)A(3)

B(0)

B(1)

B(2)

B(3)

F(0)

F(1)

F(2)

F(3)F(6) F(4)F(7) F(5)

Sample Run Sample Run Say we Say we

have,have,

10101010

xx10010011

00000000

++10101010

10110100

1st bit of answer

1010x1001 0101+0000 0101

1010x1001 0010+0000 0010

2nd bit of answer3rd bit of answer

1010x1001 0001+1010 1011

The rest of the answer

1011010 = 90 Verify!

Partial Sum

For-if generation For-if generation constructs constructs

Elements can be easily duplicated in a design Elements can be easily duplicated in a design using for-if-generate notation.using for-if-generate notation.

The syntax for this arrangement is shown The syntax for this arrangement is shown belowbelow

Gen_name_0 : For i in 0 to N-1 generateGen_name_0 : For i in 0 to N-1 generate

gen_name_1 : if(condition) generategen_name_1 : if(condition) generate

cell : component_name port map (stuff);cell : component_name port map (stuff);

end generate gen_name;end generate gen_name;

gen_name_2 : if (condition) generategen_name_2 : if (condition) generate

cell : component_name port map (stuff);cell : component_name port map (stuff);

end generate gen_name_2;end generate gen_name_2;

End generate gen_name_0;End generate gen_name_0;

Note that generate statements go Note that generate statements go afterafter the the first begin.first begin.

Example Super BufferExample Super Buffer-- Example of Cell Generation-- Example of Cell GenerationLibrary IEEE;Library IEEE;Use ieee.std_logic_1164.all;Use ieee.std_logic_1164.all;Entity of sbuf isEntity of sbuf isPort( A :Port( A : in std_logic in std_logic

Z :Z : out std_logic);out std_logic);End sbuf;End sbuf;Architecture Behav of Buffer isArchitecture Behav of Buffer isComponent PEComponent PEPort(A : in std_logic;Port(A : in std_logic;

B : out std_logic);B : out std_logic);End component;End component;-- Signal Declarations-- Signal DeclarationsSignal x : std_logic_vector(4 downto 0);Signal x : std_logic_vector(4 downto 0); BeginBegin-- Port Map section -- Port Map section GI : for i in 0 to 5 GenerateGI : for i in 0 to 5 Generate

G1 : if (I = 0) generateG1 : if (I = 0) generate -- 1-- 1stst generate generateCell : PE port map(A, x(i));Cell : PE port map(A, x(i));End generate G1;End generate G1;G2 : if (I < 5 and I > 0) generateG2 : if (I < 5 and I > 0) generate -- 2-- 2ndnd generategenerateCell : PE port map( x(I-1),x(I));Cell : PE port map( x(I-1),x(I));End generate G2;End generate G2;G3 : if (I = 5) generate G3 : if (I = 5) generate Cell : PE port map (x(I-1),Z); -- 3Cell : PE port map (x(I-1),Z); -- 3rdrd generate generateEnd generate G3;End generate G3;

End generate GI;End generate GI;End Behav;End Behav;

-- Example of cellEntity of PE isPort(A : in std_logic; B : out std_logic);End PE;Architecture Behav of PE isBeginProcess(A)BeginB <= not A;End process;End Behav;

What in the world does this synthesize to ?

See the Next Slide for Details

Synthesis ResultsSynthesis Results

• Red circle denotes region G1• Yellow circles denote region G2• Green circle denotes region G3• Green arrows indicate A• Red arrows indicate -A

Cell:3Cell:2Cell:1Cell:0 Cell:5Cell:4A Z

X(0) X(1) X(2) X(3) X(4)

I=0 I=2 I=3 I=4 I=5I=1

For I in 0 to 5 generate

Array Multiplier Layout 4x4Array Multiplier Layout 4x4

A(0)A(1)A(2)A(3)

B(0)

B(1)

B(2)

B(3)

F(0)

F(1)

F(2)

F(3)F(6) F(4)F(7) F(5)

Array MultiplierArray MultiplierArchitecture behav of Array_Mult isArchitecture behav of Array_Mult is

-- Define Signals Here-- Define Signals Here

-- Define your PE component-- Define your PE component

BeginBegin

-- Declare boundary conditions using for-generate-- Declare boundary conditions using for-generate

GI : for i in 0 to N-1 GenerateGI : for i in 0 to N-1 Generate

GJ : for j in 0 to N-1 GenerateGJ : for j in 0 to N-1 Generate

-- Subclasses of networks inside multiplier-- Subclasses of networks inside multiplier

-- Top or middle nodes -- Top or middle nodes

G1 : if (i < N-1) and (j < N-1) and (j > 0) G1 : if (i < N-1) and (j < N-1) and (j > 0) GenerateGenerate

cell : PE port map cell : PE port map (x(i,j),y(i,j),c(i,j),p(i,j),(x(i,j),y(i,j),c(i,j),p(i,j),

x(i+1,j),y(i,j+1),c(i,j+1),p(i+1,j-x(i+1,j),y(i,j+1),c(i,j+1),p(i+1,j-1));1));

End Generate G1;End Generate G1;

-- Fill in the other four sections here-- Fill in the other four sections here

End Generate GJ;End Generate GJ;

End Generate GI;End Generate GI;

End behav;End behav;

Project Guidelines Project Guidelines Teams: It is suggested that you should work Teams: It is suggested that you should work

in groups of two on this assignment. in groups of two on this assignment. Reports should be 2~3 pages in length and Reports should be 2~3 pages in length and

have all the source code included. Email or have all the source code included. Email or Paper submittal is acceptable. E-mail is the Paper submittal is acceptable. E-mail is the preferred submission method preferred submission method

Reports submitted should detail the Reports submitted should detail the methodology used to obtain the final work.methodology used to obtain the final work.

All code submitted should be well All code submitted should be well commented and should follow good coding commented and should follow good coding guidelines.guidelines.

The deadline for this project April 27th The deadline for this project April 27th Tuesday @ 11:59:59 pmTuesday @ 11:59:59 pm