very high performance logic

Digital Integrated Circuits © Prentice Hall 1995High Speed

VERY HIGH PERFORMANCE

LOGIC


Note

Slides on High-Speed Bipolarand Superconduction not yetavailable


GaAs Design

Increased Mobility at Low Electrical Field

Higher Performance


GaAs Material Properties

• Max electron velocity = 2 x Silicon = 2 107 cm/sec

• Hole mobility GaAs (= 400) < Si (489 cm2V/sec)Excludes complementary logic

• Electron mobility GaAs (4000-9000) >> Si (500-1200)

• Maximum Field (max velocity) GaAs (0.3 V/m) < Si (1 V/m)Should operate at low voltages

• Shottky Barrier Height GaAs (0.6-0.8V) > Si (0.4-0.6 V)

• Bandgap Energy GaAs (1.43 eV) > Si (1.11 eV)Radiation hard

• Resistivity GaAs (1.109/sq) >> Si (1.105 /sq)Semi-insulating


GaAs Material Problems

• Brittle Material 3 to 4 inch wafers

• High Defect DensityLow Yield (100 to 1000 times smaller vs. Si)

• QSS and Qox largeNO MOS transistors!

• Hole mobility lowNo complementary gates


Favored Device: MESFET

Semi-Insulating GaAs

S

G

D

n n+n+

L

T

channel

depletion region

1017cm-3

= 1000-2000 /sq

Schottky Diode


MESFET Operation

if(VG == 0): transistor ON — part of channel depleted

if (VG ): depletion layer conductivity

if (VG ): depletion layer conductivity

if (VG == VP): pinchoff, no conductance

DEPLETION TRANSISTOR

Enhancement transistors also availableVP (enhancement): 0 V— 0.2 VVP (depletion): -0.7 V — -2 V

Large variations of VP over die (100 — 200 mV)!


I-V Characteristic

0 0.5 1.0 1.5 2.0VDS (V)

-0.05

0.15

0.35

0 0.2 0.4 0.6 0.8VGS (V)

-0.1

0.1

0.3

0.5

I D (

mA

)

I D (

mA

)

VGS=0.7V

0.6V

0.5V

0.4V

0.3V

ID

IG

(a) ID-VDS characteristic(b) ID-VGS characteristic (VDS = 0.5 V)IG is the current flowing into the gate.


Curtice Model


GaAs MESFET Model

.model enh njf

+ vto=0.23 beta=250u lambda=0.2 alpha=6.5 ucrit=0 gamds=0 ldel=-0.4u wdel=-0.15u

+ rsh=210 n=1.16 is=0.5m level=3 sat=0 acm=1 capop=1

.model dp njf

+ vto=-0.825 beta=190u lambda=0.065 alpha=3.5 ucrit=0 gamds=0 ldel=-0.4u wdel=-0.15u

+ rsh=210 n=1.18 is=10m level=3 sat=0 acm=1 capop=1


Buffered FET Logic (BFL)

Out

In1 In2

VDD VDD

VSS

Ws

0.6Ws kWs

kWs

Level Shifting Output StageInput Stage

Inv


Voltage Transfer Characteristic

-2.0 -1.0 0.0 1.0Vin (V)

-2.0

0.0

2.0

4.0

V

Vout

Vinv


Direct-Coupled Fet Logic (DCFL)

Out

In1 In2

VDD

Max Input Voltage : +/- 0.7 V

Strict Control of Threshold Voltage Required (+/- 0.1 V)

Asymmetrical Response

Sensitive to Fanout


Performance versus Power


Source-Coupled FET Logic (SCFL)

RD

Out-In2

-

RD

In1+ In1

-

In2+

VSS

Out+

Output Stage

ISS ISFISF


Logic Families - Comparison


High Electron Mobility Transistor (HEMT)High Electron Mobility Transistor (HEMT)

Undoped semi-insulating GaAs

GATE

SOURCE DRAIN

n+ GaAs

n+AlGaAs

0-500 Å

350-500 Å

20-80 Å

Two-dimensionalelectron gas

Undoped AlGaAs

Mobility in Undoped GaAs > 8500 cm2/Vsec (4500 cm2Vsec in Doped GaAs)

Up to 50,000 cm2/Vsec at Liquid Nitrogen Temperature


JJ Logic Families

IBIAS IBIAS IBIAS

RL

IAIB

IBIAS IBIASIBIAS

RLRL

RL

RL

VA

VB

IBIAS

reset phase

(a) Current injection gate

(b) Magnetically coupled gate

(c) bias current waveform


MVTL Gate Layout

In1

In2

J1 J2

J3

RD Out

Rbias

Vbias

M

Ri

Rin1

Rin2


MVTL Transient ResponseV

olt

x 1

0-3

-12Seconds x 10

-0.40

-0.20

-0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.00

0.00 200.00

Vbias

Vout

Vin1

very high performance logic

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