1112 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013

Very Fast Dynamics of Threshold VoltageDrifts in GaN-Based MIS-HEMTs

Peter Lagger, Member, IEEE, Alexander Schiffmann, Gregor Pobegen, Dionyz Pogany, and Clemens Ostermaier

Abstract— The very fast dynamics of threshold voltage drift(�Vth) of GaN-based metal-insulator-semiconductor-HEMTsinduced by forward gate bias stress is investigated with asimple oscilloscope based setup. We show that the logarithmicrecovery time dependence of �Vth, previously found for recoverytimes ranging from 10 ms up to 1 ms, extend even to the μsregime. Further, we observed an accumulation of �Vth becauseof repetitive stress pulses of 100 ns. Consequences for deviceoperation and reliability are discussed.

Index Terms— AlGaN/GaN, forward gate bias stress, high elec-tron mobility transistor (HEMT), metal-insulator-semiconductor(MIS), MOS, reliability, threshold voltage drift, trapping.

I. INTRODUCTION

IN GaN-based high electron mobility transistors (HEMTs)a thin barrier layer is used to induce a 2-D electron gas

(2DEG) in the GaN channel directly below the barrier layer.The insulating properties of this barrier layer are insufficient.Particularly for power applications, the use of a gate dielectricis needed to suppress parasitic gate leakage currents [1].Threshold voltage instabilities, however, limit the stability andreliability of these devices [2]–[5]. Therefore, the propertiesof the interface between the dielectric and the III-N barrierlayer have to be understood. The observed �Vth instabilities(i.e., drifts and hysteresis in I–V and C–V curves) areusually associated with defect states at this particular interfaceand their density is mostly investigated using photo assistedC–V [6], admittance [7], [8], or deep-level transient spec-troscopy like measurement methods [9], which are mea-suring the response of charges to a small-signal ac biasexcitation under fixed dc bias. These methods do not linkthe fast ac response with apparently existing large signaldrift phenomena within one methodic framework. Further,they are mostly based on simplifying assumptions, as e.g.,that the relaxation processes in metal-insulator-semiconductor-HEMTs (MIS-HEMTs) are governed only by capture/emissionprocesses where the trap energy levels and the charac-teristic time constants (e.g., because of carrier emission)are directly linked [10]. Recently, based on the measure-ment of the transients of the threshold voltage drift �Vthin response to positive gate bias stress pulses, we have

Manuscript received June 21, 2013; accepted June 28, 2013. Date ofpublication August 6, 2013; date of current version August 21, 2013. Thereview of this letter was arranged by Editor T. Egawa.

P. Lagger is with the Vienna University of Technology, Wien 1040, Austriaand also with Infineon Technologies Austria, Villach 9500, Austria (e-mail:peter.lagger@infineon.com).

A. Schiffmann and C. Ostermaier are with Infineon Technologies Austria,Villach 9500, Austria.

G. Pobegen is with Kompetenzzentrum Automobil- und IndustrieelektronikGmbH, Villach 9524, Austria.

D. Pogany is with the Vienna University of Technology, Wien 1040, Austria.Color versions of one or more of the figures in this letter are available

online at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/LED.2013.2272095

shown that �Vth in GaN-based MIS-HEMTs is caused bya broad distribution of characteristic relaxation time con-stants over several decades of stress and recovery [5].The methodology is similar to that known from well-established bias temperature instability (BTI) stress-recoveryanalysis in CMOS devices [11]. In contrast to many otherstudies, we do not rely on any assumptions about the relaxationprocesses and the measurement data can be evaluated in astraightforward manner. The threshold voltage drift stronglydepends on the applied positive gate stress bias and time,where the time dependence of �Vth recovery is to first-order logarithmic. This means that the amount of recoveryof �Vth per decade is constant. It has been shown that this isvalid for recovery times in the range of 10 ms to 1 ms [5].The logarithmic distribution of time constants suggests thateven larger �Vth may exist for shorter recovery times, butit requires an experimental proof. It is apparent that theseinstabilities are a major limitation for normally OFF devices.But, up to now it was unclear whether they are also relevant forthe stability and reliability of normally ON devices, where pos-itive voltage overshoot spikes can occur during switching thedevices to the ON state depending on the parasitic componentsin a certain application, e.g., resistances and inductances. Inthis letter, we show that the broad distribution of recovery timeconstants is extended even to the μs regime using a simplemeasurement setup based on an oscilloscope. This allows usto measure the recovery of �Vth with a delay of < 1 μs usingstress pulses with 100 ns duration. The characterization of suchfast relaxation processes is usually a subject of the ac-bias-based analysis methods that is mentioned. We demonstratethat �Vth accumulates under short repetitive stress spikes with100-ns duration. The dynamics of �Vth on this time scaleis thus relevant with respect to the ac-bias-based analysismethods that is mentioned, as the cycle period is either ofthe same order of magnitude or larger.

II. EXPERIMENTAL SETUP

The sample devices are fabricated on a GaN-on-Si substrateusing state of the art processing technologies. The barrier layerof the HEMT structure consists of a 18 nm Al0.20Ga0.8Nlayer. The gate dielectric is a 15 nm silicon oxide, which isnot specifically optimized for threshold voltage drift stability.The mobility is 1820 cm2/V·s, the 2DEG concentration is7.2 · 1012 cm−2, and the nominal threshold voltage is −3.5 V.The gate length is 2 μm, gate width 5 mm, source-to-gatespacing 2 μm, and gate-to-drain spacing 16 μm. In Fig. 1,typical output and transfer characteristics of these devices areshown. The drain leakage current in OFF state is < 100 pA/mm(VG ≤ −4.2 V, VD = 10 V). The inset of Fig. 1(b) showsthat the gate leakage current is well < 10 pA/mm for all stressbiases, which are used in this letter. This indicates that there isno significant trapping in the bulk of the oxide during forwardbias stress. The measurement setup is schematically shownin Fig. 2(a). In Fig. 2(b), the waveform of a 100-ns stress

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LAGGER et al.: VERY FAST DYNAMICS OF THRESHOLD VOLTAGE DRIFTS 1113

Fig. 1. (a) Output characteristics ID(VD) for VG ranging from 4.5 to 2 V instep of 0.5 V. (b) Transfer characteristic ID(VG). Inset: gate leakage currentwith source and drain grounded.

Fig. 2. (a) Experimental setup consists of a pulse generator, an oscilloscope,a dc bias source, and a resistor RS = 10 �. (b) Input impedance of the DSO.

Fig. 3. Example for a typical stress-recovery cycle. (a) VD(t) responsefor a saw-tooth VG(t) input signal, which in combination gives the VD(VG)characteristic. (b) Typical VD(t) response for a stress pulse VG(t) switchedfrom VG,stress (3 V, 100 ns) to VG,meas (−3 V, 100 ns). VD,DUMMY(t) isrecorded as a reference and to exclude systematic influences because of themeasurement.

pulse is shown. A digital storage oscilloscope (DSO) is used tocapture the transient responses. The device under test (DUT)is connected with a dc-bias source in series with a resistorRS. The voltage drop across the resistor is proportional tothe drain current ID. A pulse generator is used to modulatethe drain current ID by the gate input bias VG along theload line defined by the resistor RS, where the drain biasVD is directly correlated with the drain current ID. In Fig. 3,an example of a full stress-recovery cycle is shown: 1) theVD(VG) characteristic of the DUT is measured by applyinga sawtooth voltage signal at the gate to bias the device fromOFF state (VG,off) to ON state (VG,on); 2) a gate bias pointVG,meas in the linear region of the VD(VG) characteristic ischosen and in a postprocessing sequence the drain voltagesignal VD(t) is directly converted to the equivalent thresholdvoltage drift �Vth [5]; 3) a dummy measurement withoutstress (VD,DUMMY) is performed to ensure the stability of thesetup and the device during measurement conditions (VG =VG,meas) and to exclude parasitic effects (e.g., selfheating);and 4) a stress pulse with a stress bias VG,stress and pulselength tstress [e.g., 3 V, 100 μs in Fig. 3(b)] is applied and thetransients of VD(t) are recorded at VG,meas. The measurementdelay is the time, which is needed to establish a stableVD(t) signal. It is limited by impedance mismatch of thetest devices and parasitic elements in the signal path to some100 ns. We state that we selectively investigate traps at thedielectric/III-N interface underneath the gate electrode because

Fig. 4. Recovery of �Vth over a logarithmic time scale for a stress biasVG,stress of 3 V and logarithmically distributed stress times from 100 ns to100 s. The measurements were performed on different devices using differentsampling rates. Data segments are distinguished by color.

of the following reasons. These traps affect solely the thresholdvoltage and are charged via the barrier during forward gatebias stress with a homogenous electric field distribution. Trapsat the dielectric/III-N interface, however, do not significantlydegrade the mobility because of the spatial separation from theactive channel region (typically 20-nm distance) [12]. Further,the 2DEG shields the buffer potential and thus a contributionof buffer traps to the drift is very unlikely. Our argumentationis further supported by the observation of a pure parallel shiftof the transfer characteristics following forward gate bias stresswith no degradation of ID,max [5]. Transient measurements atVG,meas = 0 V confirmed that the drain/source access regionsare unaffected by forward gate bias stress (i.e., no currentcollapse).

III. EXPERIMENTAL RESULTS AND DISCUSSION

In Fig. 4, the recovery traces of �Vth after stress pulseswith a fixed stress bias VG,stress of 3 V and logarithmicallydistributed stress times tstress from 100 ns to 100 s are shown.The maximum detectable �Vth is limited to 0.6 V becauseof the finite width of the transition region between OFF andON state of the device (Fig. 3). The recovery traces giveinsights into the relaxation dynamic in the submillisecondregime and reveal a logarithmic dependence in time indi-cating abroad distribution of characteristic relaxation timeconstants, in accordance with previous observations for largerstress/recovery times [5]. The result suggests that in the wholerange from μs to ms the same class of defect states isactivated. We speculate that the stress-recovery processes aregoverned by capture and emission processes at the oxide/III-N interface as the observed signature is similar to the BTIphenomenon known from Si-based MOS devices [11], [13],[14]. Hypotheses to explain the logarithmic stress/recoverydynamics include a broad distribution of defect capture crosssections and activation energies, tunneling distances to bordertraps, and distribution of local transport properties of AlGaNdislocation states [5]. Newest researches on BTI state thatconfigurational changes of oxide multistable defects [15] withno direct link between the trap energy level and the relaxationprocesses have to be considered for a proper description ofthe phenomenon [13]. A detailed discussion will be madein [16]. Furthermore, our results do not show any sign ofan onset of the recovery that would give the total numberof charges activated by a certain stress pulse. The curvesstill tend to rise toward smaller recovery times not showing aturning point. We remark that standard measurements clearlyunderestimate �Vth because of a long measurement delay. It is

1114 IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 9, SEPTEMBER 2013

Fig. 5. Envelope of the threshold voltage drift �Vth induced by periodicallyrepeated stress spikes (5 V, 100 ns). The red and green data points correspondto the points in the insets. The left inset schematically shows the VG(t) patternduring the first stress-recovery cycle. The time on x-coordinate refers to theend of the first stress pulse. The values of �Vth for each stress-recoverycycle are extracted after each stress spike, according to the dots in the leftinset. The right inset shows the recovery traces of �Vth on a linear timescale. The fluctuations are due to aliasing and coupling effects with the 50-Hzpower line.

also important to notice that even for the 100-ns long stresspulses used in this example a significant drift of the devicethreshold voltage is observed. Every data segment in the curvesin Fig. 4 is recorded using different devices and samplingrates, which indicates that the device to device variation isnegligible and that the behavior is universal. Only the recoverytraces for 100-ns stress time (i.e., three segments) are recordedconsecutively on a single device after the device was fullyrecovered within a recovery time of < 100 s. The full recoveryis identified by direct comparison of VD(t) with the referencevalue VD,DUMMY. This indicates that there are no additionaltraps created during consecutive stress-recovery cycles, but thesame traps are filled and emptied during each cycle. It can bespeculated whether the traps are created during the first cycleor whether they are due to preexisting states. The concaveshape of the lower recovery curves further show that therecovery rate (i.e., the number of electrons emitted per decadeof recovery) declines toward full recovery.

Further, we present a research of �Vth drift because ofthe cumulative effect [5], [11], [13] of repetitive stress pulses(spikes). In Fig. 5, such a scenario is emulated for a cycle timeof 100.1 μs. In this case, the time between the consecutivepulses is not sufficient for a full recovery of the thresholdvoltage. The cycle time used for the experiment is lowerthan for typical applications, which means that for typicaloperating frequencies the effect is expected to be even stronger,because of reduced recovery time between the pulses. Theobserved threshold voltage degradation is in the order of some100 mV already after a few milliseconds, with a logarithmictrend of the envelope of the �Vth curve (inset of Fig. 5 forthe pulse envelope definition). The difference between thetwo trend lines is also ∼100 mV (sampling rate 100 kSa/s).This value is of concern for the short-term stability of thedevice, whereas the overall accumulation is of concern forthe long-term reliability. Further, the observed �Vth recoverytraces are on a time scale comparable with the oscillationtime of high frequency (HF)-C–V measurements. Consideringthe accumulation because of repetitive spikes together withrecovery effects in the μs regime, this clearly indicates that aHF-C–V measurement is influenced by a combination of drifteffects because of the applied dc bias during the integrationtime of each single measurement point and fast relaxationprocesses (e.g., trapping) following the superimposed ac signal

To our understanding, this makes it difficult to interpret theresult of such a measurement. This is in a clear contrast toour method, where we are able to investigate the underlyingrelaxation processes on a very broad time scale in a systematicmanner within one methodic framework. Our method offersan accurate control of all bias and timing parameters, whereasfor example in a HF-C–V setup the integration time cannotbe controlled arbitrarily.

IV. CONCLUSION

We have shown that the logarithmic time dependence of�Vth stress and recovery is extended even to the μs regimeusing a simple oscilloscope based setup. Considering our pre-vious findings [5], this shows that the relaxation time constantsrelated to the oxide/III-N system are broadly distributed in theμs to ms range. Significant Vth changes are observed evenfor gate bias pulses as short as 100 ns. Further, we havestudied the cumulative �Vth degradation induced by repetitive100 ns stress pulses (spikes). In conclusion, our work giveswell improved estimates on the reliability limiting degradationmechanism because of stress spikes and sets a profound basisfor further investigations toward this topic.

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