Journal of Crystal Growth 201/202 (1999) 778}781

Vertical transport properties through pseudo-metallic InAsthin "lms grown on GaAs (1 1 1)A substrates

Hiroshi Yamaguchi*, Yoshiro Hirayama

NTT Basic Research Laboratories, Atsugi-shi, Kanagawa 243-01, Japan

Abstract

The electron transport properties in the growth direction of novel (Al)GaAs/InAs/GaAs structures are examined. Boththe InAs/n-GaAs and n-GaAs/InAs heterojunctions formed on (1 1 1)A surfaces showed rectifying characteristics assimilar to those of Schottky junctions, demonstrating the possibility of using heterojunctions as a substitution forconventional metal}semiconductor junctions. We have fabricated pseudo-metallic InAs-base transistors in which InAs"lm is used instead of the metal layer that is used in metal-base transistors. The operation of thermionic-injectionhot-electron transistors at room temperature is con"rmed. ( 1999 Published by Elsevier Science B.V. All rights reserved.

PACS: 73.40.Kp; 73.61.Ey

Precise interface control in highly mismatchedheteroepitaxy of semiconductor materials has longbeen hindered by the formation of three-dimen-sional islands governed by the Stranski}Krastanovmechanism, at least for growth on conventionallyused (0 0 1) oriented substrates. It was recently pro-posed that non-(0 0 1) surfaces can be used to over-come this di$culty and (1 1 1)A surfaces were usedto demonstrate the possibility of two-dimensionalgrowth for the heteroepitaxial system ofInAs/GaAs [1]. The interfaces of both GaAs/InAsand InAs/GaAs have been con"rmed to be atomi-cally #at, and the Hall measurements forGaAs/InAs/GaAs structures clari"ed that theFermi level at these interfaces is pinned in the

*Corresponding author. Tel.: #81-462-403311; fax: #81-462-702353; e-mail: hiroshi@will.bri.ntt.co.jp.

conduction band, probably due to the interfacestates caused by the dislocation network con"nedat the interfaces [2]. InAs/GaAs and GaAs/InAs heterojunctions formed on (1 1 1)A surfacesare, therefore, expected to show vertical transportproperties similar to those of metal}semiconductorjunctions. These interface properties are impor-tant for device applications because both polaritiesof Schottky junctions (surface-anode typeby InAs/GaAs, and substrate-anode type byGaAs/InAs) can be fabricated only by theheteroepitaxy of semiconductor materials. In thispaper, we propose using these heterojunctionsas a substitute for the conventional metal}semiconductor (M}S) junctions, thereby avoidingdi$culties experienced in growing high-qualityM}S heterostructures in the fabrication ofnovel high-speed devices such as metal-base tran-sistors.

0022-0248/99/$ } see front matter ( 1999 Published by Elsevier Science B.V. All rights reserved.PII: S 0 0 2 2 - 0 2 4 8 ( 9 8 ) 0 1 4 6 7 - 5

Fig. 1. (a) Fabricated GaAs/InAs/GaAs structures for I}< characterization. (b) Fabricated structure of AlGaAs/InAs/GaAs pseudo-metallic InAs base transistor.

Fig. 2. Plots of current}voltage characteristics across the GaAs/InAs and InAs/GaAs heterointerfaces at room temperature (a) with they-axis of the logarithmic current scale and (b) with the y-axis of the logarithmic scale of normalized current I/(1!e~qV@kT). The positivevoltage corresponds to the current #ow from InAs to GaAs for both interfaces. The data for the InAs/GaAs were scaled by two orders ofmagnitude relative to the data for GaAs/InAs.

To study the basic vertical transport propertiesacross the InAs/n-GaAs and n-GaAs/InAs inter-faces with thin InAs embedded layers, we investi-gated the I}< characteristics at room temperature.Fig. 1(a) shows the device structure used in thischaracterization. The top n-GaAs layer was selec-tively etched by NH

4OH solution and non-alloy

ohmic contacts were formed by the deposition ofTiAu onto the InAs thin "lms. The electron concen-tration in the n~-GaAs layer similarly grown ona semi-insulating GaAs substrate was determined

to be 2]1017 cm~3 by Hall measurements, in con-trast to the Si concentration of 4]1017 cm~3

which indicates large carrier compensation by theacceptor-site Si atoms [3]. The electron concentra-tion in the n`-GaAs layer was higher than1]1018 cm~3, which is also highly compensated.The InAs thickness was 15 nm.

Fig. 2(a) shows the I}< characteristics of thesample with a 15-nm InAs "lm. Clear rectifyingcharacteristics are evident for both interfaces.When we replot the forward-bias normalized

H. Yamaguchi, Y. Hirayama / Journal of Crystal Growth 201/202 (1999) 778}781 779

currents, I/(1!e~qV@kT), as a function of the ap-plied voltage [4], there are three voltage regionscorresponding to the di!erent current-limiting pro-cesses (A}C in Fig. 2(b)). When the voltage is lowerthan 0.3 V (region A), the I}< curve is nearly sym-metrical for both positive and negative voltages,governed by the leakage currents. Above 0.4 V (re-gion B), the thermionic-emission over theInAs/GaAs barrier dominates the processes. Theideality factor in this region was 1.7 for theInAs/GaAs interface and 3.3 for the GaAs/InAsinterface, showing that interface degradation atGaAs/InAs is larger than that at InAs/GaAs. Athigher voltages, the current saturates due to theseries resistance (region C). This current saturationis more signi"cant in the GaAs/InAs interface, be-cause of the lateral current #ow along the InAs base"lm. The base doping and the optimization of thedevice design are expected to reduce the series res-istance.

The barrier heights of these InAs/GaAs andGaAs/InAs Schottky junctions are evaluated fromthe temperature dependence of the saturation cur-rent (i.e. the y-intercept of extrapolated I}< curvesin the thermionic-emission region B). The activa-tion energy, i.e. the evaluated barrier height, is0.62 eV for the InAs/GaAs interface and 0.54 eVfor GaAs/InAs interface. These values should becompared with the reported values of metal}semiconductor Schottky junctions, which rangefrom 0.6 to 1.0 eV [4]. The simulation using self-consistent calculations for undoped GaAs/InAs/GaAs structures [2] demonstrated that the inter-face Fermi level is pinned at 0.15 eV above thebottom of the conduction band. This predictsa barrier height of 0.76 eV using the reportedvalues for a valence band discontinuity of 0.17 eVand band gaps of 0.35 and 1.43 eV for InAsand GaAs, respectively [5]. The lower experimentalvalues of barrier heights for our devices can beattributed to the electric dipole formed at theinterfaces [5], to the intermixing of In and Gaacross the interface, or to residual strain at theinterface. The nonparabolicity in the conductionband dispersion, which was neglected in the evalu-ation of the Fermi level position in the self-consis-tent calculation [2], might be responsible for thesmall discrepancy.

These results show that both the InAs/n-GaAsand n-GaAs/InAs junctions have reasonable rec-tifying characteristics. We, therefore, tried to usethis novel InAs/GaAs heterojunction in place of theSchottky junction in metal-base transistors [6].We refer to this novel hot-electron transistor asa pseudo-metallic InAs base transistor because theInAs plays the same role as the metal "lm in metal-base transistors. This kind of thermionic-injectionhot-electron transistor has the advantage that theemitter-base resistance can be lowered unlike thatof the tunneling hot-electron transistors [6].

If the n-GaAs/InAs/n-GaAs structure is used forthe transistor, the ideal barrier at the base/collectorinterface has the same height as that at the emit-ter/base interface. In reality, however, the former ishigher than the latter, leading to the injected car-riers to be frequently trapped in the base region,because the electrons are re#ected by the base/collector interfaces. This di$culty was avoided byusing the n-AlGaAs graded layer as the emitter inorder to inject more hot electrons into the collector

Fig. 3. (a) Schematic diagram of the conduction band of a fab-ricated pseudo-metallic InAs base transistor. (b) Common emit-ter characteristics at room temperature of the fabricatedpseudo-metallic InAs base transistors. Current gain b was 1.1 ata collector voltage of 2.5 V.

780 H. Yamaguchi, Y. Hirayama / Journal of Crystal Growth 201/202 (1999) 778}781

regions. The fabricated device structure is shown inFig. 1(b). The Al composition gradually changedfrom 0.7 to 0. Fig. 3 shows the typical emitter-common transistor characteristics obtained atroom temperature. The highest current gain b was1.1, obtained with an InAs thickness of 15 nm andat a collector voltage of 2.5 V. This operationof GaAs-based thermionic-injection hot-electrontransistors at room-temperature clearly demon-strates the potential device applications of highlymismatched heterostructures grown on (1 1 1)Asubstrates.

References

[1] H. Yamaguchi, M.R. Fahy, B.A. Joyce, Appl. Phys. Lett. 69(1996) 776.

[2] H. Yamaguchi, Y. Hirayama, Jpn. J. Appl. Phys. 37 (1998)1599.

[3] M. Shigeta, Y. Okano, H. Seto, H. Katahama, S. Nishine,K. Kobayashi, I. Fujimoto, J. Crystal Growth 111 (1991)284.

[4] H.E. Rhoderick, R.H. Williams, Metal}SemiconductorContacts, Oxford University Press, London, 1988.

[5] J. Terso!, Phys. Rev. B 30 (1984) 4874.[6] S.M. Sze (Ed.), High-Speed Semiconductor Devices, Wiley,

New York, 1990, and references therein.

H. Yamaguchi, Y. Hirayama / Journal of Crystal Growth 201/202 (1999) 778}781 781