Verilog/SystemVerilog Training

• Lecture 1: 21Jan16

Hardware Description Language • Verilog Background

– Verilog created at Gateway Design Automation in 1983/1984

– Cadence Design Systems purchased Gateway in 1989 • Originally intended for simulation, synthesis support added

later

– Cadence transferred Verilog to public domain • Verilog becomes IEEE Standard 1364-1995 and is known as

Verilog-95

– Extensions to Verilog-95 submitted to IEEE • IEEE Standard 1364-2001, a.k.a. Verilog-2001

– Minor corrected submitted to IEEE in 2005 • IEEE Standard 1364-2005, a.k.a. Verilog-2005

Keywords • The Verilog Language Reference Manual (LRM) specifies a

syntax that precisely describes the allowed constructs. – Verilog is case sensitive

• All keywords are lowercase • Never use Verilog keywords as unique names, even if case is different

– Verilog is composed of approximately 100 keywords

and always assign attribute begin buf bufif0 bufif1 case cmos deassign default defparam disable else endattribute end endcase endfunction endgenerate endprimitive endmodule endtable endtask event for force forever fork function generate genvar highz0 highz1 if initial inout input integer join large medium module nand negedge nor not notif0 notif1 nmos or output parameter pmos posedge primitive pulldown pullup pull0 pull1 rcmos reg release repeat rnmos rpmos rtran rtranif0 rtranif1 scalared small specify specparam strong0 strong1 supply0 supply1 table task tran tranif0 tranif1 time tri triand trior trireg tri0 tri1 vectored wait wand weak0 weak1 while wire wor

Identifiers • Identifiers:

– User defined words for variables , function names, module names, block names, and instance names • Identifiers must start with an alphabetic character or

underscore – System tasks and functions start with $

• Variables may contain alphanumeric characters, underscore, and $

• Can be up to 1024 characters long

• Case sensitive

• The “_” is also allowed within numbers for ease of reading

– Declarations, assignments, and statements end with a semicolon

Comments

• Two types of comments:

– One line comments

• Start with // and end at end of line (eol)

– Multi-line comments:

• Start with /* and end with */

• Blank spaces are ignored • Cannot appear within keyword text, a user defined

operator, or number

• A “\” is used for line multi-line continuation character

1’s and 2’s Complement

• 1’s Complement

– For binary, simply change all 1’s to 0’s and all 0’s to 1’s (invert).

• 2’s Complement

– For binary, leave all least significant 0’s and the first 1 unchanged and invert all other higher significant digits.

– Or for binary, take the 1’s complement and add 1

Binary subtraction • 1’s complement

• Given X = 101_0100 and Y = 100_0011

X – Y: X = 101_0100 1’s Complement of Y = + 011_1100 Sum = 1001_0000 End around carry = +0000_0001 Answer = 001_0001

Y - X: Y = 100_0011 1’s Complement of X = + 010_1011 Sum = 110_1110 No end carry, therefore the answer is -(1’s complement of 110_1110) = -001_0001

Binary subtraction

• 2’s complement • Given X = 101_0100 and Y = 100_0011

X – Y: X = 101_0100 2’s Complement of Y = + 011_1101 Sum = 1001_0001 Discard end carry 27 = -1000_0000 Answer = 001_0001

Y - X: Y = 100_0011 2’s Complement of X = + 010_1100 Sum = 110_1111 No end carry, therefore the answer is -(2’s complement of 110_1111) = -001_0001

Signed Binary Numbers

Changing a positive number to a negative is easily done by taking the 2’s complement of the positive.

Signed and Unsigned Numbers – No int/unint types to dictate if number is signed or

unsigned integer • Available in SystemVerilog

Number Value

32’hDEAD_BEEF Deadbeef

-32’hDEAD_BEEF 21524111 (2’s complement of deadbeef) D E A D B E E F 1101_1110_1010_1101__1011_1110_1110_1111 0010_0001_0101_0010__0100_0001_0001_0000 1’s comp. 1 add one 0010_0001_0101_0010__0100_0001_0001_0001 2 1 5 2 4 1 1 1

14’h1234 1234

-14h’1234 1DCC (2’s complement of 1234) 1 2 3 4 0001_0010_0011_0100 1110_1101_1100_1011 1’s complement 1 add one 0001_1101_1100_1100 1 D C C

Signed and Unsigned Numbers • Integer was only signed value in Verilog 1995 • Verilog 2001 added the ‘s construct

3’sh2 = 2 -3’sh4 = -4 – Decimal numbers are always signed

• Casting operators $signed and $unsigned (Verilog 2001) – Type casting with $unsigned will make operation unsigned and left

fills with 0’s if required – Type casting to with $signed makes the operand signed and sign

extend with 1’s if required.

• Excellent paper by Dr. Tumbush: http://www.uccs.edu/~gtumbush/published_papers/Tumbush%20DVCon%2005.pdf

– He emphasizes that VER-318 synthesis warnings should be investigated fully.

Operators – Bitwise/reduction are unary:

& 4’b1001 = 0

& 4’bx101 = x

| 4’b1001 = 1

| 4’bx101 = x

– Logical Operators: 2’b00 && 2’b11 = 2’b00

2’b00 || 2’b11 = 2’b11

– Shift 4’sb1001 >> 1 = 0100

4’sb1001 >>> 1 = 1100

4’b1001 >>> 1 = 0100

– Relational 4'b01x0 == 4'b01x0 produces an x

4'b01x0 === 4'b01x0 produces a 1

Shift Operator

• Left shift – Multiplies given number by powers of 2

• Given: 8’b0000_1011 (‘d11)

< 1 : 8’b0001_0110 (‘d22)

< 2 : 8’b0010_1100 (‘d44)

• Right shift – Divides number by powers of 2

• Useful for multiply, divide, shift registers, address paging, etc.

Multiply ‘b1001 (‘d9) with ‘b1100(‘d12)

1001_0000

0110_1100 0001

Step 4

1001_0000

0110_1100 0000

Step 4

0100_100

0110_1100 0001

Step 4

0100_1000

0010_0100 0001

Step 3

0100_1000

0010_0100 0011

Step 3

0010_0100

0010_0100 0011

Step 3

0010_0100

0000_0000 0011

Step 2

0010_0100

0000_0000 0110

Step 2

0001_0010

0000_0000 0110

Step 1

0001_0010

0000_0000 1100

Step 1

0000_1001

0000_0000 1100

Initialization

1001 1100 0000 0000 1001 1001 1101100

Operator Precedence • Binary Operator Precedence

(A + B)/C is not the same as A + B/C

a & &b is not the same as a && b

correct syntax and required by LRM: a & (&b)

a | |b is not the same as a || b

correct syntax and required by LRM: a | (|b)

Integers – Sized or unsized

• Unsized is 32 bits

– x/X: Uninitialized variables or nets with conflicting drivers – z/Z: High impedance – The underscore character “_” is used for improved readability – The character “?” is alternative for z in the context of numbers

• The “?” character is also used as “don’t care” in casex and casez statements

Format Prefix Legal Characters

Binary ‘b 01xXzZ_?

Octal ‘o 0-7xXzZ_?

Decimal ‘d 0-9_

Hexadecimal ‘h 0-9a-fA-FxXzZ_?

Integer Stored as (underscores added for readability)

1 0000_0000_0000_0000_0000_0000_0000_0001 (left fills w/ zeros)

8’hAA 1010_1010

‘hF 0000_0000_0000_0000_0000_0000_0000_1111

6’hCA 00_1010

6’hA 00_1010

8’hx xxxx_xxxx (left fills with x)

Real Numbers

– Fixed or scientific notation • < value >.< value > • < mantissa >E< exponent > or < significand>e< exponent > *

– Cannot contain “Z” or “X” – Real numbers are rounded off to nearest integer

when assigned to integer – Negative numbers specified by leading minus sign

• Represented in 2’s complement format

– real: • Double precision floating point (typically 64 bit)

* IEEE floating point std. committee discourages the use of the term mantissa for scientific or floating point notation

Gate Level Modeling

• Basic Gates – or, nor, and, nand

– xor, xnor, not, buf

• Three state gates – bufif0, bufif1, notif0, notif1

• Syntax – GATE (drive_strength) # (delays) instance_name1(output, input_1,

input_2,..., input_N)

Gate Level Modeling

• Three-State Gates

– High impedance is symbolized by z in Verilog

• If checking for high impedance (or unknown),

use === or !==

– The gates are instantiated with the statement: • gateName optionalUniqueName(output, input, control)

buffer when control = 1 z when control = 0

inv when control = 1 z when control = 0

buffer when control = 0 z when control = 0

inv when control = 0 z when control = 0

Gate Level Modeling

• Switch level Primitives

– pmos, nmos, cmos, rnmos, rpmos, rcmos

– tranif0, tranif1, tran, rtranif0, rtranif1, rtran

– pullup, pulldown

Gate Level Modeling

• Strengths

– Two type of strengths:

• drive: used for nets (except trireg), gates, and User Defined Primitives (UDPs) – supply, strong, pull, large, weak, medium, small, highz

• charge: used only for trireg nets – large, medium, small

Strength Value Display tasks value

supply 7 Su

strong 6 St

pull 5 Pu

large 4 La

weak 3 We

medium 2 Me

small 1 Sm

highz 0 HiZ

//Drive Example: and (strong1, weak0) and1(o, i1, i2); // Charge Example: // trireg retains last value when driven by z trireg (medium) x;

Gate Level Modeling • Gate Delays

– Recall that all physical circuits exhibit a propagation delay between the transition of a input a resulting transition on the output

– Adding gate delays, allows user to model propagation delays

– Ignored by synthesis tools

• Hint: Don’t rely on gate delays

– Tools “back annotate” delays

after synthesis and place/route

// HDL Example 3.2 module simpleCircuit(A, B, C, D, E); output D, E; input A, B, C; wire w1;

// Single delay for all transistions and #5 G1(w1, A, B, C);

// Rise and fall delay and #(1,2) G2(w1, A, B, C);

// Rise, fall, and turn off delay bufif1 #(1,3,2) G3(x, y);

// One Delay: min, typ, max or #(1:2:3) G3(D, w1, E);

// Three delays: min, typ, max for PVT bufif1 #(1:2:3,4:5:6,7:8:9) G6(D, w1, E); endmodule

// Continuous Assignment – no delay assign y = ~a; // Continuous Assignment – LHS delay assign #5 y = ~a; // Illegal Continuous Assignment – RHS delay Assign y = #5 ~a;

Data Types • Value Set

0: logic zero, false 1: logic one, true x: unknown, contention z: high impedance, undriven

• Nets – wire, tri: interconnecting wire – wor, trior: Wired OR – wand, triand: Wired AND – tri0, tri1: Net pull up/down when not driven – supply0, supply1: Constant logic value of supply strength – trireg: Retains last value when driven by z

• Verilog wire: – “wire” is combinational and evaluates continuously – Cannot store a value – Default initialization value of z – Nets with drivers assume output value of driver (default of x) – No properties (delay, etc.) associated with wires

• Just interconnect between elements

• Syntax wire [msb:lsb] wire_variable_list;

wire a, b, c; assign a = b; wire x = c;

Data Types

• Registers – Declare reg for all data objects on the left hand

side of expressions in initial and always procedures, or functions

– Used for latches, flip flops, and memories

– Data is stored as unsigned

– reg is sequential and evaluates on event

• Syntax: reg [msb:lsb] reg_variable_list;

Data Types

• Vectors – Range is specified as: [msb_exp: lsb_exp] – Example: wire[31:0] a;

• 32 bits with MSB as 31 and LSB as 0 • big endian • a is all wires • a[31] specifies the MSB • a[0] specifies LSB • a[15:8] is eight wires, bits 15 through 8 of a

– reg signed [7:0] • Vector for -128 to 127 (2’s complement)

– Keyword “vectored” specifies a vector that can only be modified as an indivisible entity

– Keyword “scalared” allows access to bits and parts (default)

Data Types • Arrays

– reg[31:0] mema[0:4095] • 4096 words of 32 bits per word

• mema[2] is third word

• mema[2][31] is the MSB of the third word

31:0

31:0

31:0

31:0

….

31:0

31:0

31:0

mema[0]

mema[1]

mema[2]

mema[3]

….

mema[4093]

mema[4094

mema[4095]

Data Types

• Memories

– reg[7:0] vid_mem[1:4][7:0][5:0]

• 3D array organized as bytes

• Initialized with $readmemh or $readmemb

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

[7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0]

5:0

7:0

1:4

Strings

• Treated as sequence of eight bit ASCII values – No special termination character

• One eight bit ASCII value hold one character • Strings can be manipulated using standard

operators • To store a string, declare a register large enough

to hold all characters reg [8*15:0] myString ;

• The null string (“”) is equivalent to the value zero (0)

String Tasks Function Description

len() Returns string length

putc() Assign one character of string

getc() Returns a character

toupper() Returns the string uppercase

tolower() Returns the string lowercase

compare() Returns the string compare

icompare() Returns the caseless string compare

substr() Returns the sub0string of main string

Function Description

atoi() Returns integer value of the decimal represenation in ASCII string

atohex() Returns hex value of the hex representation in ASCII string

atooct() Returns octal value of the octal representation in ASCII string

atobin() Returns binary value of the binary representation in ASCII string

atoreal() Returns real value of the real representation in ASCII string

itoa() Stores the ASCII decimal representation of i into str (inverse of atoi)

hextoa() Stores the ASCII hex representation of i into str (inverse of atohex)

octtoa() Stores the ASCII octal representation of i into str (inverse of atooct)

bintoa() Stores the ASCII binary representation of i into str (inverse of atobin)

realtoa() Stores the ASCII real representation of i into str (inverse of atoreal)