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Verilog Projects

For Advanced VLSI Design Laboratory

By

S. Maheswaran

Rahul Rithe

Bharath Srikanth Jami

CONTENTS

1. Adder with Accumulator ............................................................................... 3

2. Synchronous Presettable Binary Counter.................................................... 10

3. Non-restoring Cellular Array Divider (Fast Divider) .................................... 16

4. Bubble-Sorting ............................................................................................ 25

5. Universal Shift Register .............................................................................. 32

Verilog Implementation of Adder with Accumulator

Objective: To model and analyze an Adder with Accumulator Specifications:

1. Word-size : 4-bit 2. Accumulator size : 4-bit

Design: This circuit performs the operation of adding two 4-bit numbers (one from user and one from the accumulator), and the result is stored back into the accumulator. Any carry-generated is stored in carry-flag. The block-level schematic diagram of the circuit is shown below:

A four-bit adder is implemented using carry-lookahead fast-adder. The Accumulator is realized with a bank of four D Flip-flops with parallel loading ability in order to load and clear the accumulator whenever necessary.

ADDER

Carry

Input

ACCUMULATOR

Parallel Load

(Reset)

Circuit Diagram: D-Flipflop :

Entire Circuit:

Verilog Implementation: /************************ D Flip Flop ****************************/ module dff(d,q,clk); input d,clk; output q; wire w1,w2,w3,w4,qbar; nand n1(w4,d,w3); nand n2(w3,w4,clk,w2); nand n3(w2,clk,w1); nand n4(w1,w4,w2); nand n5(q,w2,qbar); nand n6(qbar,q,w3); endmodule /************************ Multiplexer ****************************/ module mux(in1,in2,s,out); input in1,in2,s; output out; wire sbar,w1,w2; not n1(sbar,s); and a1(w1,sbar,in1); and a2(w2,s,in2); or o1(out,w1,w2); endmodule /************************ Accumulator ****************************/ module accumulator(in,out,clk); input [3:0]in; input clk; output [3:0]out; dff d1(in[0],out[0],clk); dff d2(in[1],out[1],clk); dff d3(in[2],out[2],clk); dff d4(in[3],out[3],clk); endmodule /************************ Four bit Adder ****************************/ module fourbitadd(a,b,sum,c_in,c_out); // i/o declarations input [3:0] a,b; input c_in; output [3:0]sum; output c_out; wire [3:0] p,g,c; assign p[0]=a[0]|b[0]; assign p[1]=a[1]|b[1]; assign p[2]=a[2]|b[2]; assign p[3]=a[3]|b[3]; assign g[0]=a[0]&b[0]; assign g[1]=a[1]&b[1]; assign g[2]=a[2]&b[2]; assign g[3]=a[3]&b[3];

assign c[0]= g[0]|(p[0]&c_in); assign c[1]= g[1]|(p[1]&g[0])|(p[1]&p[0]&c_in); assign c[2]= g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&c_in); assign c[3]= g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&c_in); assign sum[0]=a[0]^b[0]^c_in; assign sum[1]=a[1]^b[1]^c[0]; assign sum[2]=a[2]^b[2]^c[1]; assign sum[3]=a[3]^b[3]^c[2]; assign c_out=c[3]; endmodule /************************ Entire Circuit ****************************/ module integrate(data,in,add_sub,load,clk,out,carry); input [3:0]data,in; input add_sub,load,clk; output [3:0]out; output carry; wire [3:0]s,w; wire c_out; mux m1(data[0],s[0],load,w[0]); mux m2(data[1],s[1],load,w[1]); mux m3(data[2],s[2],load,w[2]); mux m4(data[3],s[3],load,w[3]); accumulator acc(w,out,clk); fourbitadd fas(in,out,s,add_sub,c_out); dff d1(c_out,carry,clk); endmodule /************************ Stimulus ****************************/ module stimulus; reg [3:0]in,data; reg clk,add_sub,load; wire [3:0]out; wire carry; integrate i(data,in,add_sub,load,clk,out,carry); initial begin clk=0; add_sub=0; load=0; data=4'b0000; in=4'b0000; #3 load=1; #4 in=4'b0010; #4 in=4'b1000; #4 in=4'b0100; #4 in=4'b0101; #4 in=4'b0110; #4 load=0; data=4'b0010; #4 load=1; #0 in=4'b0010; #4 in=4'b1000; #4 in=4'b0100;

#4 in=4'b0101; #4 in=4'b0110; end always #2 clk=~clk; initial begin $monitor($time, "in=%d.........out=%d......carry=%d.....c_in=%d....add=%d....",in,out,carry,add_sub,add_sub); #100 $finish; end endmodule Design Analysis:

1. IC Diagram :

2. Circuitry of Module ‘Integrate’

Result:

Optimization:

Step Maximum Dynamic

Power (mW)

Maximum Leakage Power

(nW)

Total Area Data Arrival Time (ns)

0 5.99 120.06 14785.29 7.04 1 (with max

delay set to 5ns) 6.90 170.71 16787.16 5.00

2 (with max delay set to 3ns)

13.35 368.29 29577.29 4.14

Verilog Implementation of a Synchronous Presettable Binary Counter

Objective: To design and analyze a Synchronous Presettable Binary Counter. Specifications:

1. Modulo-16 (4-bit) counter, subsequently cascaded to 8-bit counter 2. Parallel loading 3. Up/Down counting

Circuit Diagram:

Verilog Implementation: `timescale 1ns / 10ps /**************************** D-Flipflop ****************************/ module dff(d,q,clk); input d,clk; output q; wire w1,w2,w3,w4,qbar; nand n1(w4,d,w3); nand n2(w3,w4,clk,w2); nand n3(w2,clk,w1); nand n4(w1,w4,w2); nand n5(q,w2,qbar); nand n6(qbar,q,w3); endmodule /**************************** Multiplexer ****************************/ module mux(in1,in2,s,out); input in1,in2,s; output out; wire sbar,w1,w2; not n1(sbar,s); and a1(w1,sbar,in1); and a2(w2,s,in2); or o1(out,w1,w2); endmodule /**************************** One bit Adder ****************************/ module onebitadder(in1,in2,c_in,sum,c_out); input in1,in2,c_in; output sum,c_out; wire w1,w2,w3; xor x1(w1,in1,in2); and a1(w2,w1,c_in); and a2(w3,in1,in2); or o1(c_out,w2,w3); xor x2(sum,w1,c_in); endmodule /**************************** Four bit adder ****************************/ module fourbitaddsub(in1,in2,out,c_in,c_out,add_sub); input [3:0]in1,in2; output [3:0]out; input c_in,add_sub; output c_out; wire w1,w2,w3,w4; wire [2:0]c;

xor x1(w1,in1[0],add_sub); xor x2(w2,in1[1],add_sub); xor x3(w3,in1[2],add_sub); xor x4(w4,in1[3],add_sub); onebitadder a1(w1,in2[0],c_in,out[0],c[0]); onebitadder a2(w2,in2[1],c[0],out[1],c[1]); onebitadder a3(w3,in2[2],c[1],out[2],c[2]); onebitadder a4(w4,in2[3],c[2],out[3],c_out); endmodule /******************************* IC ******************************/ module integrate(data,in,up_down,carry_count,load,clk,out,carry_out); input [3:0]data,in; input up_down,carry_count,load,clk; inout [3:0]out; output carry_out; wire [3:0]s,w; mux m1(data[0],s[0],load,w[0]); mux m2(data[1],s[1],load,w[1]); mux m3(data[2],s[2],load,w[2]); mux m4(data[3],s[3],load,w[3]); dff d1(w[0],out[0],clk); dff d2(w[1],out[1],clk); dff d3(w[2],out[2],clk); dff d4(w[3],out[3],clk); fourbitaddsub fas(in,out,s,carry_count,carry_out,up_down); endmodule module cascade(data,in,up_down,carry_count,load,clk,out,carry_out); input [7:0]data,in; input up_down,carry_count,load,clk; inout [7:0]out; output carry_out; wire carry; wire [3:0]w1,w2,w3,w4,w5,w6; assign w1=data[3:0]; assign w2=data[7:4]; assign w3=in[3:0]; assign w4=in[7:4]; integrate i1(w1,w3,up_down,carry_count,load,clk,w5,carry); integrate i2(w2,w4,up_down,carry,load,clk,w6,carry_out); assign out[3:0]=w5; assign out[7:4]=w6; endmodule

/**************************** Stimulus ****************************/ module stimulus; reg [7:0]data,in; reg up_down,carry_count,load,clk; wire [7:0]out; wire carry_out; cascade i(data,in,up_down,carry_count,load,clk,out,carry_out); initial begin clk=1'b0; load=1'b0; up_down=1'b0; carry_count=1'b0; data=8'b00000000; in=8'b00000001; #4 load=1'b1; #15 load=1'b0; data=8'b10011011; #3 load=1'b1; #25 up_down=1'b1; carry_count=1'b1; #20 load=1'b0; data=8'b10100001; end always #3 clk=~clk; initial begin $recordfile("up_down_count.trn"); $recordvars; #100 $finish; end endmodule

Design Analysis:

Result:

Optimization:


Power (mW)


(nW)


0 3.15 133.69 15800.61 7.85 1 (with max

delay set to 4ns) 5.97 369.60 29839.95 4.00


7.43 433.97 34081.89 3.50

Verilog Implementation of Divider Objective: To design, implement and analyze a Divider. Specifications:

1. Numbers (all signed) a. Dividend – 16bit b. Divisor – 8bit c. Quotient – 8bit d. Remainder – 8bit

Design: A Non-Restoring Cellular Array divider (fast divider) is implemented. Here the entire operation takes place asynchronously without the need of a clock. In normal Restoring division, subtraction takes place until there is a sign changes and then again another addition is done in order to revert back the sign. This is not the case in non-restoring division. Here the only operation required is either addition or subtraction. Successively right-shifted versions of the divisor are subtracted from or added to the dividend, resulting in partial remainders. The sign of the partial remainder determines the quotient bit and, further, determines whether to add or subtract the shifted divisor in the next cycle. Signed division is implemented by initially converting all the numbers into positive numbers and then converting the Quotient and Remainder appropriately. Circuit Diagram: Basic Module:

Fast Divider:

Implementation: module addsub(in1, in2, cin, ctrl, sum, cout); input in1, in2, cin, ctrl; output sum, cout; wire pxord, w1, w2, w3; xor x1(pxord, in2, ctrl); xor x2(w1, in1, pxord); xor x3(sum, w1, cin); and x4(w2, w1, cin); and x5(w3, in1, pxord); or x6(cout, w2, w3); endmodule module fourbitadd(a,b,c_in,sum,c_out); // i/o declarations input [3:0] a,b; input c_in; output [3:0]sum; output c_out; wire [3:0] p,g,c; assign p[0]=a[0]|b[0]; assign p[1]=a[1]|b[1];

assign p[2]=a[2]|b[2]; assign p[3]=a[3]|b[3]; assign g[0]=a[0]&b[0]; assign g[1]=a[1]&b[1]; assign g[2]=a[2]&b[2]; assign g[3]=a[3]&b[3]; assign c[0]= g[0]|(p[0]&c_in); assign c[1]= g[1]|(p[1]&g[0])|(p[1]&p[0]&c_in); assign c[2]= g[2]|(p[2]&g[1])|(p[2]&p[1]&g[0])|(p[2]&p[1]&p[0]&c_in); assign c[3]= g[3]|(p[3]&g[2])|(p[3]&p[2]&g[1])|(p[3]&p[2]&p[1]&g[0])|(p[3]&p[2]&p[1]&p[0]&c_in); assign sum[0]=a[0]^b[0]^c_in; assign sum[1]=a[1]^b[1]^c[0]; assign sum[2]=a[2]^b[2]^c[1]; assign sum[3]=a[3]^b[3]^c[2]; assign c_out=c[3]; endmodule module eightbitadd(a,b,c_in,sum); input [7:0]a,b; input c_in; output [7:0]sum; wire cout,cout1; fourbitadd f1(a[3:0],b[3:0],c_in,sum[3:0],cout); fourbitadd f2(a[7:4],b[7:4],cout,sum[7:4],cout1); endmodule module sixteenbitadd(a,b,c_in,sum); input [15:0]a,b; input c_in; output [15:0]sum; wire cout1,cout2,cout3,cout4; fourbitadd f1(a[3:0],b[3:0],c_in,sum[3:0],cout1); fourbitadd f2(a[7:4],b[7:4],cout1,sum[7:4],cout2); fourbitadd f3(a[11:8],b[11:8],cout2,sum[11:8],cout3); fourbitadd f4(a[15:12],b[15:12],cout3,sum[15:12],cout4); endmodule module twoscomplement(in, ctrl, out); input [7:0] in; input ctrl; output [7:0] out; wire [7:0] inbar; xor h0(inbar[0],in[0],ctrl); xor h1(inbar[1],in[1],ctrl); xor h2(inbar[2],in[2],ctrl); xor h3(inbar[3],in[3],ctrl); xor h4(inbar[4],in[4],ctrl); xor h5(inbar[5],in[5],ctrl); xor h6(inbar[6],in[6],ctrl); xor h7(inbar[7],in[7],ctrl); eightbitadd fortwos(inbar,8'b0,ctrl,out); endmodule module div(dnd,div,correctq,correctr,ctrlq); input [15:0] dnd;

input [7:0] div; output [7:0] correctq; output [7:0] correctr; output ctrlq; wire [15:0] dndbar; wire [7:0] s,r; wire [8:0] q; wire [7:0] d,divbar; wire [15:0] a; wire c12, c13, c14, c15, c16, c17, c18, c19; wire c22, c23, c24, c25, c26, c27, c28, c29; wire c32, c33, c34, c35, c36, c37, c38, c39; wire c42, c43, c44, c45, c46, c47, c48, c49; wire c52, c53, c54, c55, c56, c57, c58, c59; wire c62, c63, c64, c65, c66, c67, c68, c69; wire c72, c73, c74, c75, c76, c77, c78, c79; wire c82, c83, c84, c85, c86, c87, c88, c89; wire c92, c93, c94, c95, c96, c97, c98, c99; wire s11, s12, s13, s14, s15, s16, s17, s18, s19; wire s21, s22, s23, s24, s25, s26, s27, s28, s29; wire s31, s32, s33, s34, s35, s36, s37, s38, s39; wire s41, s42, s43, s44, s45, s46, s47, s48, s49; wire s51, s52, s53, s54, s55, s56, s57, s58, s59; wire s61, s62, s63, s64, s65, s66, s67, s68, s69; wire s71, s72, s73, s74, s75, s76, s77, s78, s79; wire s81, s82, s83, s84, s85, s86, s87, s88, s89; wire s91, s92, s93, s94, s95, s96, s97, s98, s99; wire [7:0]dbar; wire sign; wire div7bar, ctrlr; xor x1(dndbar[0],dnd[0],dnd[15]); xor x2(dndbar[1],dnd[1],dnd[15]); xor x3(dndbar[2],dnd[2],dnd[15]); xor x4(dndbar[3],dnd[3],dnd[15]); xor x5(dndbar[4],dnd[4],dnd[15]); xor x6(dndbar[5],dnd[5],dnd[15]); xor x7(dndbar[6],dnd[6],dnd[15]); xor x8(dndbar[7],dnd[7],dnd[15]); xor x9(dndbar[8],dnd[8],dnd[15]); xor x10(dndbar[9],dnd[9],dnd[15]); xor x11(dndbar[10],dnd[10],dnd[15]); xor x12(dndbar[11],dnd[11],dnd[15]); xor x13(dndbar[12],dnd[12],dnd[15]); xor x14(dndbar[13],dnd[13],dnd[15]); xor x15(dndbar[14],dnd[14],dnd[15]); xor x16(dndbar[15],dnd[15],dnd[15]); sixteenbitadd sixadd(dndbar,16'b0,dnd[15],a); xor y1(divbar[0],div[0],div[7]); xor y2(divbar[1],div[1],div[7]); xor y3(divbar[2],div[2],div[7]); xor y4(divbar[3],div[3],div[7]); xor y5(divbar[4],div[4],div[7]); xor y6(divbar[5],div[5],div[7]);

xor y7(divbar[6],div[6],div[7]); xor y8(divbar[7],div[7],div[7]); eightbitadd eba(divbar,8'b0,div[7],d); addsub a11(1'b1, 1'b1, c12, 1'b1, s11, q[8]); addsub a12(a[15], d[7], c13, 1'b1, s12, c12); addsub a13(a[14], d[6], c14, 1'b1, s13, c13); addsub a14(a[13], d[5], c15, 1'b1, s14, c14); addsub a15(a[12], d[4], c16, 1'b1, s15, c15); addsub a16(a[11], d[3], c17, 1'b1, s16, c16); addsub a17(a[10], d[2], c18, 1'b1, s17, c17); addsub a18(a[9], d[1], c19, 1'b1, s18, c18); addsub a19(a[8], d[0], 1'b1, 1'b1, s19, c19); addsub a21(s12, 1'b0, c22, q[8], s21, q[7]); addsub a22(s13, d[7], c23, q[8], s22, c22); addsub a23(s14, d[6], c24, q[8], s23, c23); addsub a24(s15, d[5], c25, q[8], s24, c24); addsub a25(s16, d[4], c26, q[8], s25, c25); addsub a26(s17, d[3], c27, q[8], s26, c26); addsub a27(s18, d[2], c28, q[8], s27, c27); addsub a28(s19, d[1], c29, q[8], s28, c28); addsub a29(a[7], d[0], q[8], q[8], s29, c29); addsub a31(s22, 1'b0, c32, q[7], s31, q[6]); addsub a32(s23, d[7], c33, q[7], s32, c32); addsub a33(s24, d[6], c34, q[7], s33, c33); addsub a34(s25, d[5], c35, q[7], s34, c34); addsub a35(s26, d[4], c36, q[7], s35, c35); addsub a36(s27, d[3], c37, q[7], s36, c36); addsub a37(s28, d[2], c38, q[7], s37, c37); addsub a38(s29, d[1], c39, q[7], s38, c38); addsub a39(a[6], d[0], q[7], q[7], s39, c39); addsub a41(s32, 1'b0, c42, q[6], s41, q[5]); addsub a42(s33, d[7], c43, q[6], s42, c42); addsub a43(s34, d[6], c44, q[6], s43, c43); addsub a44(s35, d[5], c45, q[6], s44, c44); addsub a45(s36, d[4], c46, q[6], s45, c45); addsub a46(s37, d[3], c47, q[6], s46, c46); addsub a47(s38, d[2], c48, q[6], s47, c47); addsub a48(s39, d[1], c49, q[6], s48, c48); addsub a49(a[5], d[0], q[6], q[6], s49, c49); addsub a51(s42, 1'b0, c52, q[5], s51, q[4]); addsub a52(s43, d[7], c53, q[5], s52, c52); addsub a53(s44, d[6], c54, q[5], s53, c53); addsub a54(s45, d[5], c55, q[5], s54, c54); addsub a55(s46, d[4], c56, q[5], s55, c55); addsub a56(s47, d[3], c57, q[5], s56, c56); addsub a57(s48, d[2], c58, q[5], s57, c57); addsub a58(s49, d[1], c59, q[5], s58, c58); addsub a59(a[4], d[0], q[5], q[5], s59, c59); addsub a61(s52, 1'b0, c62, q[4], s61, q[3]); addsub a62(s53, d[7], c63, q[4], s62, c62);

addsub a63(s54, d[6], c64, q[4], s63, c63); addsub a64(s55, d[5], c65, q[4], s64, c64); addsub a65(s56, d[4], c66, q[4], s65, c65); addsub a66(s57, d[3], c67, q[4], s66, c66); addsub a67(s58, d[2], c68, q[4], s67, c67); addsub a68(s59, d[1], c69, q[4], s68, c68); addsub a69(a[3], d[0], q[4], q[4], s69, c69); addsub a71(s62, 1'b0, c72, q[3], s71, q[2]); addsub a72(s63, d[7], c73, q[3], s72, c72); addsub a73(s64, d[6], c74, q[3], s73, c73); addsub a74(s65, d[5], c75, q[3], s74, c74); addsub a75(s66, d[4], c76, q[3], s75, c75); addsub a76(s67, d[3], c77, q[3], s76, c76); addsub a77(s68, d[2], c78, q[3], s77, c77); addsub a78(s69, d[1], c79, q[3], s78, c78); addsub a79(a[2], d[0], q[3], q[3], s79, c79); addsub a81(s72, 1'b0, c82, q[2], s81, q[1]); addsub a82(s73, d[7], c83, q[2], s82, c82); addsub a83(s74, d[6], c84, q[2], s83, c83); addsub a84(s75, d[5], c85, q[2], s84, c84); addsub a85(s76, d[4], c86, q[2], s85, c85); addsub a86(s77, d[3], c87, q[2], s86, c86); addsub a87(s78, d[2], c88, q[2], s87, c87); addsub a88(s79, d[1], c89, q[2], s88, c88); addsub a89(a[1], d[0], q[2], q[2], s89, c89); addsub a91(s82, 1'b0, c92, q[1], s91, q[0]); addsub a92(s83, d[7], c93, q[1], s92, c92); addsub a93(s84, d[6], c94, q[1], s93, c93); addsub a94(s85, d[5], c95, q[1], s94, c94); addsub a95(s86, d[4], c96, q[1], s95, c95); addsub a96(s87, d[3], c97, q[1], s96, c96); addsub a97(s88, d[2], c98, q[1], s97, c97); addsub a98(s89, d[1], c99, q[1], s98, c98); addsub a99(a[0], d[0], q[1], q[1], s99, c99); assign s[7] = s92; assign s[6] = s93; assign s[5] = s94; assign s[4] = s95; assign s[3] = s96; assign s[2] = s97; assign s[1] = s98; assign s[0] = s99; and g1(dbar[7],d[7],s[7]); and g2(dbar[6],d[6],s[7]); and g3(dbar[5],d[5],s[7]); and g4(dbar[4],d[4],s[7]); and g5(dbar[3],d[3],s[7]); and g6(dbar[2],d[2],s[7]); and g7(dbar[1],d[1],s[7]); and g8(dbar[0],d[0],s[7]);

eightbitadd add(dbar,s,1'b0, r); xor n1(ctrlq, div[7], dnd[15]); twoscomplement twos1(q[7:0], ctrlq, correctq); twoscomplement twos2(r, dnd[15], correctr); endmodule module stim; reg [15:0] a; reg [7:0] d; wire [7:0] q; wire [7:0] r; wire ctrlq; div ddd(a,d,q,r,ctrlq); initial begin $recordfile("div.trn"); $recordvars; $monitor($time, " a=%d and d=%d ctrlq=%b, seems to give q=%d with r=%d ",a,d,ctrlq,q,r); a = -16'd167; d = -16'd16; #100 a = -16'd45; d = 16'd111; #300 $finish; end always begin #1 a = a+10; end endmodule

Design Analysis:

Result: Timing Diagram:

(i) Positive by Positive value

(ii) Positive by Negative value

(iii)Negative by Positive value

(iv) Negative by Negative value

Optimization:

Step Maximum Dynamic Power

(mW)


(uW)


1 (with max delay set to

40ns)

78.0364 1.5144 0.1864 39.99


30ns)

108.8170 2.2705 0.248 29.98


120.4353 2.8741 0.296 19.99

Verilog Implementation of Sorting Objective: To model and analyze a Bubble-sorting hardware implemented using Verilog Specifications:

1. 8-bit number 2. 8 numbers

Design: Sorting is performed using Bubble sort algorithm. Eight registers of 8-bit each are used for storing and performing sorting. They are initially parallel loaded with the numbers to be sorted. A 5-bit counter is started and four most significant bits of it are fed to the control unit. The control unit generates the control signals which are used to select the two adjacent registers to be compared and then swapping is performed if required. As the next registers are compared, second round of comparison starts in the registers in order to save time. According to the Algorithm, 25 clock cycles are used to complete the sorting procedure.

Circuit Diagram:

Verilog Implementation: module dff(d,q,clk,ld,data); input d,clk,ld,data; output q; wire w1,w2,w3,w4,qbar,dout; mux m(data,d,ld,dout); nand n1(w4,dout,w3); nand n2(w3,w4,clk,w2); nand n3(w2,clk,w1); nand n4(w1,w4,w2); nand n5(q,w2,qbar); nand n6(qbar,q,w3); endmodule module jkff(j,k,ld,in,q,qbar,clk); input j,k,clk,ld,in; output qbar; output q; wire w1,w2,w3,w4,w5,w6,w7,w8,w9; wire kbar,d,ldbar,din; and a1(w1,j,qbar); not n1(kbar,k); and a2(w2,kbar,q); or o1(d,w1,w2); and a3(w3,in,ld); not n2(ldbar,ld); and a4(w4,ldbar,d); or o2(din,w3,w4); nand nd1(w9,w7,w8); nand nd2(w8,w9,clk); nand nd3(w5,w8,w7,clk); nand nd4(w7,w5,din); nand nd5(q,qbar,w8); nand nd6(qbar,q,w5); endmodule module counter(count, ld, in, clk); input clk, ld; input [5:0] in; output [4:0] count; wire qAbar, qBbar, qCbar, qDbar, qEbar,qFbar,q,w1,w2,w3,w4; and a1(w1,q,count[0]); and a2(w2,w1,count[1]); and a3(w3,w2,count[2]); and a4(w4,w3,count[3]); jkff A(w4, w4, ld, in[5], count[4], qAbar, clk); jkff B(w3, w3, ld, in[4], count[3], qBbar, clk); jkff C(w2, w2, ld, in[3], count[2], qCbar, clk); jkff D(w1, w1, ld, in[2], count[1], qDbar, clk); jkff E(q, q, ld, in[1], count[0], qEbar, clk); jkff F(1'b1, 1'b1, ld, in[0], q, qFbar, clk); endmodule module control(count, c1, c2, c3, c4, c5, c6, c7); input [4:0] count; output c1, c2, c3, c4, c5, c6, c7;

wire A, B, C, D, E; assign A = count[3]; assign B = count[2]; assign C = count[1]; assign D = count[0]; assign c1 = ~D; assign c2 = D; assign c3 = ((~A)&B&(~D))|(A&(~B)&(~D))|(C&(~D)); assign c4 = (A&(~C)&D)|(B&D)|((~A)&C&D); assign c5 = (A&(~B)&(~C)&(~D))|((~A)&B&(~D)); assign c6 = B&D; assign c7 = (~A)&(B)&C&(~D); //initial // $monitor($time, " count=%d, c1=%b, c2=%b, c3=%b, c4=%b, c5=%b, c6=%b, c7=%b",count,c1,c2,c3,c4,c5,c6,c7); endmodule module mux(in1,in2,s,out); input in1,in2,s; output out; wire sbar,w1,w2; not n1(sbar,s); and a1(w1,sbar,in1); and a2(w2,s,in2); or o1(out,w1,w2); endmodule module eightbitreg(in,clk,out,ld,data); input [7:0]in,data; input clk,ld; output [7:0]out; dff d1(in[0],out[0],clk,ld,data[0]); dff d2(in[1],out[1],clk,ld,data[1]); dff d3(in[2],out[2],clk,ld,data[2]); dff d4(in[3],out[3],clk,ld,data[3]); dff d5(in[4],out[4],clk,ld,data[4]); dff d6(in[5],out[5],clk,ld,data[5]); dff d7(in[6],out[6],clk,ld,data[6]); dff d8(in[7],out[7],clk,ld,data[7]); endmodule module comparator(a,b,a_gr_b,a_eq_b,a_ls_b,en); input [7:0]a,b; input en; output a_gr_b,a_eq_b,a_ls_b; wire x1, x2, x3,x4, x5, x6, x7, x8; assign x1 = ~(a[7]^b[7]); assign x2 = ~(a[6]^b[6]); assign x3 = ~(a[5]^b[5]); assign x4 = ~(a[4]^b[4]); assign x5 = ~(a[3]^b[3]); assign x6 = ~(a[2]^b[2]); assign x7 = ~(a[1]^b[1]); assign x8 = ~(a[0]^b[0]); assign a_gr_b=(a[7]&(~b[7])|(x1&a[6]&(~b[6]))|(x1&x2&a[5]&(~b[5]))|(x1&x2&x3&a

[4]&(~b[4]))|(x1&x2&x3&x4&a[3]&(~b[3]))|(x1&x2&x3&x4&x5&a[2]&(~b[2]))|(x1&x2&x3&x4&x5&x6&a[1]&(~b[1]))|(x1&x2&x3&x4&x5&x6&x7&a[0]&(~b[0])))&en; endmodule module four_to_one_mux(in1,in2,in3,in4,out,s1,s2); input in1,in2,in3,in4,s1,s2; output out; assign out = (s1?(s2?in4:in3):(s2?in2:in1)); endmodule module eightbitmux(in1,in2,in3,in4,s1,s2,out); input [7:0] in1,in2,in3,in4; output [7:0] out; input s1,s2; four_to_one_mux m1(in1[0],in2[0],in3[0],in4[0],out[0],s1,s2); four_to_one_mux m2(in1[1],in2[1],in3[1],in4[1],out[1],s1,s2); four_to_one_mux m3(in1[2],in2[2],in3[2],in4[2],out[2],s1,s2); four_to_one_mux m4(in1[3],in2[3],in3[3],in4[3],out[3],s1,s2); four_to_one_mux m5(in1[4],in2[4],in3[4],in4[4],out[4],s1,s2); four_to_one_mux m6(in1[5],in2[5],in3[5],in4[5],out[5],s1,s2); four_to_one_mux m7(in1[6],in2[6],in3[6],in4[6],out[6],s1,s2); four_to_one_mux m8(in1[7],in2[7],in3[7],in4[7],out[7],s1,s2); endmodule module eightbit_2to1_mux(in1,in2,out,s); input [7:0] in1,in2; input s; output [7:0] out; mux m1(in1[0],in2[0],s,out[0]); mux m2(in1[1],in2[1],s,out[1]); mux m3(in1[2],in2[2],s,out[2]); mux m4(in1[3],in2[3],s,out[3]); mux m5(in1[4],in2[4],s,out[4]); mux m6(in1[5],in2[5],s,out[5]); mux m7(in1[6],in2[6],s,out[6]); mux m8(in1[7],in2[7],s,out[7]); endmodule module IC(ld,clk,r1,r2,r3,r4,r5,r6,r7,r8,out1,out2,out3,out4,out5,out6,out7,out8); input [7:0] r1,r2,r3,r4,r5,r6,r7,r8; input ld,clk; output [7:0] out1,out2,out3,out4,out5,out6,out7,out8; wire [7:0] in1,in2,in3,in4,in5,in6,in7,in8; wire c1,c2,c3,c4,c5,c6,c7; wire r1_gr_r2,r2_gr_r3,r3_gr_r4,r4_gr_r5,r5_gr_r6,r6_gr_r7,r7_gr_r8; wire r1_eq_r2,r2_eq_r3,r3_eq_r4,r4_eq_r5,r5_eq_r6,r6_eq_r7,r7_eq_r8; wire r1_ls_r2,r2_ls_r3,r3_ls_r4,r4_ls_r5,r5_ls_r6,r6_ls_r7,r7_ls_r8; wire swap2,swap3,swap4,swap5,swap6,swap7; wire [4:0]count; eightbitreg reg1(in1,clk,out1,~ld,r1); eightbitreg reg2(in2,clk,out2,~ld,r2); eightbitreg reg3(in3,clk,out3,~ld,r3);

eightbitreg reg4(in4,clk,out4,~ld,r4); eightbitreg reg5(in5,clk,out5,~ld,r5); eightbitreg reg6(in6,clk,out6,~ld,r6); eightbitreg reg7(in7,clk,out7,~ld,r7); eightbitreg reg8(in8,clk,out8,~ld,r8); eightbit_2to1_mux m1(out1,out2,in1,r1_gr_r2); eightbitmux m2(out2,out1,out2,out3,c2,swap2,in2); eightbitmux m3(out3,out2,out3,out4,c3,swap3,in3); eightbitmux m4(out4,out3,out4,out5,c4,swap4,in4); eightbitmux m5(out5,out4,out5,out6,c5,swap5,in5); eightbitmux m6(out6,out5,out6,out7,c6,swap6,in6); eightbitmux m7(out7,out6,out7,out8,c7,swap7,in7); eightbit_2to1_mux m8(out8,out7,in8,r7_gr_r8); or o2(swap2,r1_gr_r2,r2_gr_r3); or o3(swap3,r2_gr_r3,r3_gr_r4); or o4(swap4,r3_gr_r4,r4_gr_r5); or o5(swap5,r4_gr_r5,r5_gr_r6); or o6(swap6,r5_gr_r6,r6_gr_r7); or o7(swap7,r6_gr_r7,r7_gr_r8); comparator cmp1(out1,out2,r1_gr_r2,r1_eq_r2,r1_ls_r2,c1); comparator cmp2(out2,out3,r2_gr_r3,r2_eq_r3,r2_ls_r3,c2); comparator cmp3(out3,out4,r3_gr_r4,r3_eq_r4,r3_ls_r4,c3); comparator cmp4(out4,out5,r4_gr_r5,r4_eq_r5,r4_ls_r5,c4); comparator cmp5(out5,out6,r5_gr_r6,r5_eq_r6,r5_ls_r6,c5); comparator cmp6(out6,out7,r6_gr_r7,r6_eq_r7,r6_ls_r7,c6); comparator cmp7(out7,out8,r7_gr_r8,r7_eq_r8,r7_ls_r8,c7); control ctrl(count,c1,c2,c3,c4,c5,c6,c7); counter ctr(count,ld,6'b0,clk); endmodule module stimulus; reg clk,ld; reg [7:0] r1,r2,r3,r4,r5,r6,r7,r8; wire [7:0] out1,out2,out3,out4,out5,out6,out7,out8; IC sort(ld,clk,r1,r2,r3,r4,r5,r6,r7,r8,out1,out2,out3,out4,out5,out6,out7,out8); initial $monitor($time," ld=%b, clk=%b, out1=%d, out2=%d, out3=%d out4=%d out5=%d out6=%d out7=%d out8=%d.......",ld,clk,out1,out2,out3,out4,out5,out6,out7,out8); initial begin clk = 0; ld = 1'b1; r1=8'd19; r2=8'd83; r3=8'd5; r4=8'd22; r5=8'd52; r6=8'd0; r7=8'd6;

r8=8'd6; #3 ld = 1'b0; end initial begin $recordfile("sort_fast.trn"); $recordvars; end always #2 clk = ~clk; initial #228 $finish; endmodule Design Analysis:

Result:

Optimization:


Power (mW)


(uW)


0 40.45 2.83445 327223.16 35.10 1 (with max delay set to

30ns)

41.21 2.94784 332157.12 29.86


25ns)

43.06 3.494 355727.62 24.99

Verilog Implementation of IC74194 (Universal Shift Register)

Objective: To implement the IC74194 using verilog and to analyse the performance of the IC realized. Specifications: Facilities required for:

1. Parallel Loading 2. Shift Left 3. Shift Right 4. Shift Left serial input 5. Shift Right serial input

Connection Diagram:

16

15

14

13

12

11

10

IC 73194

CLR

A

C

D

B

Shift Right Serial Input

GND

Shift Left Serial Input

S0

S1

CLOCK

QA

QB

QC

QD

VCC

Truth Table:

Mode Description S1 S0 0 0 No operation 0 1 Shift Right 1 0 Shift Left 1 1 Parallel Load

Circuit Diagram of the IC:

Implementation: module DFF(D, clk, Q, Qbar); input D; input clk; output Q,Qbar; wire w1,w2,w3,w4; nand N1(w1, w2, w4); nand N2(w2, w1, clk); nand N3(w3, clk, w2, w4); nand N4(w4, D, w3); nand N5(Q, w2, Qbar); nand N6(Qbar, Q, w3); endmodule

module decoder(s0, s1, c0, c1, c2, c3); input s0, s1; output c0, c1, c2, c3; wire s0not, s1not; nor n1(c0, s0, s1); not g1(s0not, s0); and g2(c1, s0not, s1); not g3(s1not, s1); and g4(c2, s1not, s0); and a1(c3, s0, s1); endmodule module basicpart(c0, c1, c2, c3, inp0, inp1, inp2, clk, out); input c0, c1, c2, c3, inp1, inp2, inp0, clk; output out; wire outbar; wire w1, w2, w3, w0, wall; and a0(w0, inp0, c3); and a1(w1, inp1, c1); and a2(w2, inp2, c2); and a3(w3, out, c0); or o1(wall, w0, w1, w2, w3); DFF dff1(wall, clk, out, outbar); endmodule module fourbitshiftregister(D0, D1, D2, D3, DSR, DSL, S0, S1, CP, Q0, Q1, Q2, Q3); input D0, D1, D2, D3, DSR, DSL, S0, S1, CP; output Q0, Q1, Q2, Q3; wire c0, c1, c2, c3; decoder dec1(S0, S1, c0, c1, c2, c3); basicpart stage1(c0, c1, c2, c3, D0, Q1, DSR, CP, Q0); basicpart stage2(c0, c1, c2, c3, D1, Q2, Q0, CP, Q1); basicpart stage3(c0, c1, c2, c3, D2, Q3, Q1, CP, Q2); basicpart stage4(c0, c1, c2, c3, D3, DSL, Q2, CP, Q3); endmodule module eightbitshiftregister(D0, D1, D2, D3, D4, D5, D6, D7, DSR, DSL, S0, S1, CP, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); input D0, D1, D2, D3, D4, D5, D6, D7, S0, S1; input DSL, DSR, CP; output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; fourbitshiftregister reg1(D0, D1, D2, D3, DSR, Q4, S0, S1, CP, Q0, Q1, Q2, Q3); fourbitshiftregister reg2(D4, D5, D6, D7, Q3, DSL, S0, S1, CP, Q4, Q5, Q6, Q7); endmodule module stimulus; reg D0, D1, D2, D3, D4, D5, D6, D7, DSR, DSL, S0, S1, CP; wire Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7; eightbitshiftregister ebsr(D0, D1, D2, D3, D4, D5, D6, D7, DSR, DSL, S0, S1, CP, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7); initial begin $recordfile("univshift.trn"); $recordvars();

#20 $finish; end initial begin D0 = 1; D1 = 0; D2 = 1; D3 = 0; D4 = 0; D5 = 1; D6 = 1; D7 = 0; DSL = 0; DSR = 0; CP = 0; S0 = 1; S1 = 1; end initial begin #7 D0 = 0; D1 = 0; D2 = 1; D3 = 0; D4 = 1; D5 = 1; D6 = 1; D7 = 0; DSL = 0; DSR = 0; S0 = 1; S1 = 1; end always #3 CP = ~CP; endmodule Design Analysis:

Result:

(i) For s0=0,s1=1; s0=1,s1=0 and s0=0, s1=0

(ii) For s0 = 1 and s1 = 1

Optimization:


Power (mW)


(nW)


0 4.61 253.63 24495 14.08 1 (with max delay set to

10ns)

4.05 270.4 25434.76 9.82


4.72 311.0 26042.22 6.11

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