verilog laboratory manual

Department of Electronics and Communication Engineering GITAM Institute of Technology, GITAM University, Visakhapatnam

Prepared By G.V.K.Sharma, Department of ECE, GITAM Institute of Technology, GITAM University

4/4 B.E ECE Ist Semester

VERILOG Laboratory Manual

Prepared by G.V.K.Sharma

Associate Professor, Department of ECE,

GITAM Institute of Technology, GITAM University



Lab- I 1. Study of VLSI Design Styles

a. Suggested Reading i) Section 1.8 in “CMOS Digital Integrated Circuits by Kang and Leblicini” TMH Publications

b. Suggested Reading ii) Seciton 3.6 and 3.7 in “Fundamentals of Digital Logic with Verilog

Design by Stephen Brown and Vranesic” TMH Publications

2. Demostration of VLSI Design Flow and Usage of Xilinx Project Navigator/Modelsim 3. Synthesis and Simulation of Sample Verilog Models (1-bit Half Adder, 2X4 Decoder etc.)

Verilog Model illustrating various Basic Gates module gates(a, b, y1, y2, y3, y4 ,y5); input a, b; output y1, y2, y3, y4, y5; assign y1 = a&b; // AND Gate assign y21 = a|b; // OR Gate assign y3 = a^b; // XOR Gate assign y4 = ~(a&b); // NAND Gate assign y5 = ~(a|b; // NOR Gate endmodule Verilog Model of a Half Adder (Dataflow) module hadder(a, b, s, c); input a,b; output s,c; assign s = a^b; assign c = a&b; endmodule



Verilog Model of a 2X4 Decoder (Behavioral) module dec24(ip, op); input [1:0] ip; output [0:3] op; reg [0:3] op; always@(ip) begin case(ip) 2’b00 : op = 4’b1000; 2’b01 : op = 4’b0100; 2’b10 : op = 4’b0010; 2’b11 : op = 4’b0001; default: op = 4’b0000; endcase end endmodule Verilog Model of a Tristate Buffer module tristate(a, en, y); input [3:0] a; input en; output [3:0] y; assign y = en ? a :4’bz; endmodule 1) Student Exercise: Develop the Verilog model of a 1-bit full adder



Lab -II Modeling Combinational Logic in Verilog 4 X 1 Multiplexer Verilog Model (Dataflow) module mux41(i0, i1, i2, i3, s1, s0, op); input i0, i1, i2, i3, s1, s0; output op; assign op = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) | (s1 & ~s0 & i2) |(s1 & s0 & i3); end module Verilog Model (Behavioral) module mux41(ip, sel, op) input [0:3] ip; input [1:0] sel; output op; reg op; always @(ip or sel) begin case(sel) 2’b00 : op = i[0]; 2’b01 : op = i[1]; 2’b10 : op = i[2]; 2’b11 : op = i[3]; default: op = 1’b0; endcase end endmodule



1 X 4 Demultiplexer Verilog Model (Dataflow) module demux14(ip , s1, s0, op0, op1, op2, op3); input ip, s1, s0; output op0, op1, op2, op3; assign op0 = ~s1 & ~s0 & ip; assign op1 = ~s1 & s0 & ip; assign op2 = s1 & ~s0 & ip; assign op3 = s1 & s0 & ip; endmodule Verilog Model (Behavioral) module demux14(ip , sel, op); input ip, input [1:0] sel; output [0:3] op; reg [0:3] op; always @(ip or sel) begin case(sel) 2’b00 : op = {ip, 1’b0, 1’b0, 1’b0}; 2’b01 : op = {1’b0, ip, 1’b0, 1’b0}; 2’b10 : op = {1’b0, 1’b0, ip, 1’b0}; 2’b11 : op = {1’b0, 1’b0, 1’b0, ip}; default: op = {1’b0, 1’b0, 1’b0, 1’b0}; endcase end endmodule



4 X 2 Encoder Verilog Model (Dataflow) module enc42(ip, op) input [3:0] ip; output [1:0] op; assign op[0] = ip[1] | ip[3]; assign op[1] = ip[2] | ip[3]; end module Verilog Model (Behavioral) module enc42(ip, op) input [3:0] ip; output [1:0] op; reg [1:0] op; always @(ip) begin case(ip) 4’b0001: op = 2’b00; 4’b0010: op = 2’b01; 4’b0100: op = 2’b10; 4’b1000: op = 2’b11; default: op = 2’b00; endcase end endmodule



4 X 2 Priority Encoder Verilog Model (Dataflow) module penc42(w,y,z) input [3:0] w; output [1:0] y; output zout; wire i0, i1, i2, i3; assign i0 = ~w[3]&~w[2]&~w[1]&w[0]; assign i1 = ~w[3]&~w[2]&w[1]; assign i2 = ~w[3]&w[2]; assign i3 = w3; assign y[0] = i1 |i3; assign y[1] = i2 | i3; assign zout = i1 | i2 | i3 | i4; endmodule Verilog Model (Behavioral) module penc42(w,y) input [3:0] w; output [1:0] y; reg [1:0 y; always @(w) begin if(w[3]) y = 2’b11; else if(w[2]) y = 2’b10;

else if(w[1]) y = 2’b01;

else y = 2’b00; end endmodule Student Exercises

1. 2 X 4 Decoder (Dataflow & Behavioral Models) 2. BCD – to – 7 Segment Display Code Converter 3. 4-Bit Binary to Gray Code Converter 4. 4-Bit Gray to Binary Code Converter 5. BCD to Excess 3 Code Converter 6. 8 X 3 Encoder & Decoder (using Dataflow and Behavioral Models) 7. 8-Bit Parity Generator



Verilog Model of a Priority Encoder using casez statement module penc42(w,y) input [3:0] w; output reg [1:0] y; always @(w) begin casez(w) 4’b1???: y = 2’b11; 4’b01??: y = 2’b11;

4’b001?: y = 2’b11; 4’b0001: y = 2’b11; default: y = 2’b00;

endcase end endmodule Verilog Model of a 7-Segment Display Decoder module sevenseg(input [3:0] data, output reg [6:0] segments); parameter BLANK = 7’b000_0000; parameter ZERO = 7’b111_1110;

parameter ONE = 7’b011_0000; parameter TWO = 7’b110_1101; parameter THREE = 7’b111_1001; parameter FOUR = 7’b011_0011; parameter FIVE = 7’b101_1011; parameter SIX = 7’b101_1111; parameter SEVEN = 7’b111_0000; parameter EIGHT = 7’b111_1111; parameter NINE = 7’b111_1011;

always @(*) case(data) 0: segments = ZEROS; 1: segments = ONE; 2: segments = TWO; 3: segments = THREE; 4: segments = FOUR; 5: segments = FIVE; 6: segments = SIX; 7: segments = SEVEN; 8: segments = EIGHT; 9: segments = NINE; default: segments = BLANK; endcase endmodule



Lab-III Modeling Combinational Logic in Verilog (Structural Modeling) Model a 4 X 1 Multiplexer using 2 X 1 Multiplexers module mux21(i0, i1, s, op); input i0,i1,s; output op; assign op = s ? i1 : i0; endmodule module mux41(ip, sel, op); input [0:3] ip; input [1:0] sel; output op; wire i1, i2; mux21 m1(ip[0], ip[1],sel[0], i1); mux21 m2(ip[2], ip[3],sel[0], i2); mux21 m3(i1, i2,sel[1], op); endmodule Model a 16 X 1 Multiplexer using 4 X 1 Multiplexers module mux161(ip, sel, op); input [0:15] ip; input [3:0] sel; output op; wire [0:3] s; mux41 m11 (ip[0:3], sel[1:0], s[0]); mux41 m12 (ip[4:7], sel[1:0], s[1]); mux41 m13 (ip[8:11], sel[1:0], s[2]); mux41 m14 (ip[12:15], sel[1:0], s[3]); mux41 m15 (s, sel[3:2], op); endmodule



Model a 4-bit Full Adder/Substractor using 1-bit Full Adders Verilog Model of a 1-bit Full Adder module fadd1(a,b,cin,sum,cout); input a,b,cin; output sum,cout; assign sum = a^b^cin; assign cout = (a&b)|(b&cin)|(cin&a); endmodule Verilog Model of a 4-Bit Fulladder using 1-bit Fulladders module fadd4(a,b,cin,sum,cout); input [3:0] a,b; input cin; output [3:0] sum; output cout; wire c1,c2,c3; fadd1 f1(a[0], b[0], cin, sum[0], c1); fadd1 f2(a[1], b[1], c1, sum[1], c2); fadd1 f3(a[2], b[2], c2, sum[2], c3); fadd1 f4(a[3], b[3], c3, sum[3], cout); endmodule Verilog Model of a 4-Bit Substractors using 1-bit Fulladders module fadd4(a,b,m,sum,cout); input [3:0] a,b; input m; output [3:0] sum; output cout; wire c1,c2,c3; wire [3:0] bxor; assign bxor = b ^ {m,m,m,m}; fadd1 f1(a[0], bxor[0], m, sum[0], c1); fadd1 f2(a[1], bxor[1], c1, sum[1], c2); fadd1 f3(a[2], bxor[2], c2, sum[2], c3); fadd1 f4(a[3], bxor[3], c3, sum[3], cout); endmodule



Model a 4 X 16 Decoder using 2 X 4 Decoders module dec24(w,y,en); input [1:0] w; input en; output [0:3] y; reg [0:3] y; always @(w or en) begin case({en,w}) 3’b100 : y = 4’b1000; 3’b101 : y = 4’b0100; 3’b110 : y = 4’b0010; 3’b111 : y = 4’b0001; default : y = 4’b0000; endcase end endmodule module dec416(w,y,en) input [3:0] w; input en; output [0:15] y; wire [0:3] m; dec24 dec1 (w[3:2], m[0:3], en); dec24 dec2 (w[1:0], y[0:3], m[0]); dec24 dec3 (w[1:0], y[4:7], m[1]); dec24 dec4 (w[1:0], m[8:11], m[2]); dec24 dec5 (w[1:0], m[12:15], m[3]); endmodule Model a 5-bit comparator using 1-bit comparator module comp1(ai, bi, apgt, bpgt, agt, bgt); input ai, bi, apgt, bpgt; output agt, bgt; reg agt, bgt; always @(*) begin if(apgt!=bpgt) begin agt = apgt; bgt = bpgt; end else begin agt = ai; bgt = bi; end end endmodule



Verilog Model of a 5-bit Comparator using 1-bit Comparators module comp5(a,b,agt,bgt); input [4:0] a,b; output agt,bgt; wire [4:1] acarry, bcarry; comp1 c1(a[4], b[4], 1’b1, 1’b1, acarry[4], bcarry[4]); comp1 c2(a[3], b[3], acarry[4], bcarry[4], acarry[3], bcarry[3]); comp1 c3(a[2], b[2], acarry[3], bcarry[3], acarry[2], bcarry[2]); comp1 c4(a[1], b[1], acarry[2], bcarry[2], acarry[1], bcarry[1]); comp1 c5(a[0], b[0], acarry[1], bcarry[1], agt, bgt); endmodule Student Exercise 1. Realize a 4-bit X 4-bit Array multiplier with 1-bit HAs and 1-bitFAs using Structural Modeling



Lab-IV Modeling Sequential Logic in Verilog Verilog Model of a Gated D-Latch module dlatch(d, clk, q); input d, clk; output q; reg q; always@(d or clk) begin if(clk) q = d; end endmodule Verilog Model of a D Flip-Flop module dff(d, clk, q); input d, clk; output q; reg q; always@(posedge clk) q = d; endmodule Verilog Model of a D Flip-Flop with asynchronous reset module dff(d, clk, rst, q); input d, clk, rst; output q; reg q; always@(posedge clk or negedge rst) begin if(!rst) q=0; else q = d; end endmodule



Verilog Model of a D Flip-Flop with Synchronous Reset module dff(d, clk, rst, q); input d, clk, rst; output q; reg q; always@(posedge clk) begin if(!rst) q=0; else q = d; end endmodule Verilog Model of an 8-Bit Register with asynchronous reset module regn(d, load, rst, clk, q); input [7:0] d; input load, rst, clk; output [7:0] q; reg [7:0] q; always @(negedge rst or posedge clk) begin if(!rst) q = 8’d0; else if(load) q = d; end endmodule Verilog Model of a 4-Bit Ripple Counter (Structural Model) using JK Flip Flop module jkff(j, k, rst, clk, q); input j, k, rst, clk; output q; reg state; assign q = state; always @(negedge rst or posedge clk) begin if(!rst) state = 1’b0; else if(j=1’b1 & k=1’b0) state = 1’b1; else if(j=1’b0& k=1’b1) state = 1’b0; else if(j=1’b1 & k=1’b1) state = ~state; end endmodule



module ripcount(rst, clk, q); input rst, clk; inout [3:0] q; jkff f1(1’b1, 1’b1, rst, clk, q[0]); jkff f2(1’b1, 1’b1, rst, q[0], q[1]); jkff f3(1’b1, 1’b1, rst, q[1], q[2]); jkff f4(1’b1, 1’b1, rst, q[2], q[3]); endmodule Verilog Model of a 4-bit Synchronous Counter with synchronous reset (Behavioral Model) module syncount(rst, cen, clk, q); input rst, cen, clk; output reg [3:0] q; always @(posedge clk) begin if(rst) q =4’b000; else if(cen) q = q+4’d1; end endmodule Verilog Model of a 4-bit Synchronous Counter using DFFs (Structural Model) module syncount(rst, cen, clk, q); input rst, cen, clk; output reg [3:0] q; wire d[3:0]; assign d[3] = q[3] ^ (q[2] & q[1] & q[0]); assign d[2] = q[2] ^ (q[1] & q[0]); assign d[1] = q[1] ^ q[0]; assign d[0] = ~q[0]; dff d1 (d[3], clk, rst, q[3]); dff d2 (d[2], clk, rst, q[2]); dff d3 (d[1], clk, rst, q[1]); dff d4 (d[0], clk, rst, q[0]); endmodule Student Exercises

1. Develop the Verilog Model of a MOD-12 Synchronous Counter using D Flip Flops and appropriate dataflow statements

2. Develop the Verilog Model of a MOD-12 Synchronous Counter using JK Flip Flops and appropriate dataflow statements

3. Develop the Behavioral Verilog Model of a MOD-12 Synchronous Counter using always statements 4. Model a Ring Counter and Johnson Counter using Behvavioral & Structural Modeling (using DFFs) 5. Model a 4-Bit Up counter with parallel load



Model a 4-bit Universal Shift Register (Behavioral Modeling) module univsh(d, clk, sel, rst, serin, serout); input [3:0] d; input [1:0] sel; input clk, serin, ; output serout; output reg [3:0] q; always @(posedge clk or negedge rst) begin if(!rst) q = 5’b00000; else if(sel == 2’b00) q = d; else if(sel == 2’b01) q = {serin, q[3:1]}; else if(sel == 2’b10) q = {q[2:0], serin}; else q = q; end assign serout = q[0]; endmodule Model a 4-bit Universal Shift Register using D-Flip Flops(Structural Model) module univsh(d, clk, sel, rst, serin, serout); input [3:0] d; input [1:0] sel; input clk, serin, ; output serout; inout [3:0] q; wire [3:0] ff; mux41 m3 (d[3], serin, q[2], q[3], sel[1], sel[0], ff[3]); mux41 m2 (d[2], q[3], q[1], q[2], sel[1], sel[0], ff[2]); mux41 m1 (d[1], q[2], q[0], q[1], sel[1], sel[0], ff[1]); mux41 m0 (d[0], q[1], serin, q[0], sel[1], sel[0], ff[0]); dff d1 (ff[3], clk, rst, q[3]); dff d2 (ff[2], clk, rst, q[2]); dff d3 (ff[1], clk, rst, q[1]); dff d4 (ff[0], clk, rst, q[0]); endmodule



Model a 64-Word, 16-Bit RAM using Verilog module ram(clk, addr, wrb, din, dout); input clk; input [5:0] addr; input wrb; input [16:0] din; output [15:0] dout; reg [15:0] men[63:0]; always @(posedge clk) if(~wrb) mem[addr] = din; assign din = mem[addr]; endmodule



Finite State Machines Every sequential logic circuit consists of combinational logic circuit along with flip flops. The set of all the flip flops can be thought of as a register and the various set of values taken by all the flipflops taken together (register) can be named as states. We see that a sequential logic circuit essentially has two parts. First, a combinational logic circuit that takes inputs and current state and generates the output and nexstate. Second, a state register that accepts the nextstate and produces it at the output (as the current state) after the positive edge of clock pulse. The behavior of the combinational logic circuit can be modeled using an always block along with case statement (wherein the outputs for various input combinations are mentioned). The behavior of the state register can be modeling as an n-bit register (if number of states <=2N) using always block MOORE State Machine: The output of a moore state machine depends only on the state and not on the inputs.

Figure 1: A Moore State Machine

Model a Three 1’s Detector using a Moore State Machine and code it in Verilog module moore(ip, clk, op, rst); input ip, clk, rst; output op; reg op; parameter S0=0, S1=1, S2=2, S3=3; reg [0:1] cs, ns; always @(posedge clk or posedge rst) // State Register begin if(rst) cs = S0; else cs = ns; end



always @(cs) //Combinational Logic that implements state logic case(cs) S0: begin

op =0; if(ip) ns = S1; else ns = S0;

end S1: begin


end S2: begin


end S3: begin


end default: op = 0; ns = S0; endcase end endmodule Alternate Verilog Description of the above Moore State Machine module moore(ip, clk, op); input ip, clk; output op; reg op; parameter S0=0, S1=1, S2=2, S3=3; reg [0:1] cs; always @(posedge clk) //Combinational Logic that implements state logic case(cs) S0: if(ip) cs = S1; else cs = S0; S1: if(ip) cs = S2; else cs = S0; S2: if(ip) cs = S3; else cs = S0; S3: if(ip) cs = S3; else cs = S0; default: cs = S0; endcase end assign op = (cs==S0) ? 1 : 0; endmodule



Verilog Model of a 4-Bit Ring Counter implemented as a Moore State Machine module(clk, rst, q); input clk, rst; output [3:0] q; reg [3:0] cs, ns; always @(posedge clk or negedge rst) // State register that hold cs begin if(!rst) cs = 4’b1000; else cs = ns; end always @(cs) // Combinational logic that generates ns from cs begin case(cs) 4’b1000: ns = 4’b0100; 4’b0100: ns = 4’b0010;

4’b0010: ns = 4’b0001; 4’b0001: ns = 4’b1000; default: ns = 4’b1000;

endcase end assign q = cs; endmodule Student Exercise:

1. Model a 3-bit Johnson Counter as a Moore State Machine 2. Derive the sequence detector for the sequence “0101” and model it as a Moore State Machine

MEALY State Machine

Figure 2: Mealy State Machine



Model the rate ½ convolutional encoder as a Mealy State machine



Design Project – I: 4 X 4 Bit Multiplier Design

Figure 3: Block Diagram for Binary Multiplier

Figure 4: State Graph for Binary Multiplier Control



Verilog Model for Control Unit module control(clk,st,ld,sh,m,done ); input clk, m, st; output ld, sh, done; reg [3:0] cs,ns; reg ld, sh, done; always@(posedge clk) cs = ns; always@(cs or st or m) begin case(cs) 4'd0 : if(st) begin ns = 4'd1; ld = 1'b1; sh = 1'b0; done =1'b0; end else begin ns = 4'd0; ld = 1'b0; sh = 1'b0; done =1'b0;end 4'd1 : if(m) begin ns = 4'd2; ld = 1'b1; sh = 1'b0; done =1'b0;end else begin ns = 4'd3; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd2 : begin ns = 4'd3; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd3 : if(m) begin ns = 4'd4; ld = 1'b1; sh = 1'b0; done =1'b0;end else begin ns = 4'd5; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd4 : begin ns = 4'd5; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd5 : if(m) begin ns = 4'd6; ld = 1'b1; sh = 1'b0; done =1'b0;end else begin ns = 4'd7; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd6 : begin ns = 4'd7; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd7 : if(m) begin ns = 4'd8; ld = 1'b1; sh = 1'b0; done =1'b0;end else begin ns = 4'd9; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd8 : begin ns = 4'd9; ld = 1'b0; sh = 1'b1; done =1'b0;end 4'd9 : begin ns = 4'd0; ld = 1'b0; sh = 1'b0; done =1'b1;end default: begin ns = 4'd0; ld = 1'b0; sh = 1'b0; end endcase end endmodule



Verilog Model for 1-Bit Full Adder module fa1(a,b,cin,sum,cout); input a; input b; input cin; output sum; output cout; assign sum = a ^ b ^ cin; assign cout = (a&b) | (b&cin) | (cin&a); endmodule Verilog Model for 4-bit Full Adder module fa4(a,b,sum,cout); input [3:0] a; input [3:0] b; output [3:0] sum; output cout; wire c1, c2, c3; fa1 f1(a[0], b[0], 1'b0, sum[0], c1); fa1 f2(a[1], b[1], c1, sum[1], c2); fa1 f3(a[2], b[2], c2, sum[2], c3); fa1 f4(a[3], b[3], c3, sum[3], cout); endmodule Verilog Model for Shift Register module shireg(d,q,ld,sh,clk); input [8:0] d; output [8:0] q; input ld; input sh; input clk; reg [8:0]q; always @(posedge clk) begin if(ld) q = d; else if(sh) q = {1'b0,q[8:1]}; end endmodule



Verilog Model for Final Multiplier module mul(x,y,prod,st,clk,done); input [3:0] x; input [3:0] y; output [8:0] prod; output done; input st; input clk; wire [8:0] tempd; wire [8:0] q; wire [3:0] sum; wire cout; wire ld, sh, m; assign m = q[0]; assign tempd = st ? {5'b00000,y} : {cout,sum, q[3:0]}; shireg s1 (tempd, q,ld,sh,clk); fa4 f1 (x,q[7:4] ,sum, cout); control c1 (clk,st,ld,sh,m,done); assign prod = q; endmodule



Design Project – II: Greatest Common Divisor (GCD) calculator Verilog Model for Comparator module comp4(a,b,altb); input [3:0] a; input [3:0] b; output altb; assign altb = a < b; endmodule

Verilog Model for 1-bit Full Adder module f1(a,b,cin,sum,cout); input a; input b; input cin; output sum; output cout; assign sum = a ^ b ^ cin; assign cout = (a&b) | (b&cin) | (cin&a); endmodule Verilog Model for Substractor module sub4(a,b,sum); input [3:0] a; input [3:0] b; output [3:0] sum; wire c1, c2, c3,cout; f1 fulladd1(a[0], ~b[0], 1'b1, sum[0], c1); f1 fulladd2(a[1], ~b[1], c1, sum[1], c2); f1 fulladd3(a[2], ~b[2], c2, sum[2], c3); f1 fulladd4(a[3], ~b[3], c3, sum[3], cout); endmodule

Verilog Model for 4-Bit Register module reg4(d,clk,ld,q); input [3:0] d; input clk; input ld; output [3:0] q; reg [3:0] q; always @(posedge clk) begin if(ld) q = d; end endmodule

Verilog Model for checking not equal case module neq4(a,b,aneqb); input [3:0] a; input [3:0] b; output aneqb; assign aneqb = a != b; endmodule



Verilog Model for Control Unit module control(clk,go,xneqy,xlty,xsel,ysel,xld,yld,dld); input clk, go, xneqy, xlty; output xsel, ysel, xld, yld, dld; reg xsel, ysel, xld, yld, dld; reg [2:0] cs, ns; always @(posedge clk) cs = ns; always @(cs or go or xneqy or xlty) begin case (cs) 3'b000: begin if(go) ns = 3'b001; else ns = 3'b000; xsel = 1'b0; ysel = 1'b0; xld = 1'b0; yld = 1'b0; dld=1'b0; end 3'b001: begin ns = 3'b010; xsel = 1'b0; ysel = 1'b0; xld = 1'b1; yld = 1'b1; dld=1'b0; end 3'b010: begin if(xneqy) if(xlty) ns = 3'b011; else ns = 3'b100; else ns = 3'b101; xsel = 1'b0; ysel = 1'b0; xld = 1'b0; yld = 1'b0;dld=1'b0; end 3'b011: begin ns = 3'b010; xsel = 1'b0; ysel = 1'b1; xld = 1'b0; yld = 1'b1;dld=1'b0; end 3'b100: begin ns = 3'b010; xsel = 1'b1; ysel = 1'b0; xld = 1'b1; yld = 1'b0;dld=1'b0; end 3'b101: begin ns = 3'b000; xsel = 1'b0; ysel = 1'b0; xld = 1'b0; yld = 1'b0; dld=1'b1; end default: begin ns = 3'b000; xsel = 1'b0; ysel = 1'b0; xld = 1'b0; yld = 1'b0; dld=1'b0; end endcase end endmodule



Verilog Model for 4-bit 2X1 Multiplexer module mux421(a,b,sel,zout); input [3:0] a; input [3:0] b; input sel; output [3:0] zout; assign zout = sel ? b : a; endmodule

Verilog Model for the final GCD Module module gcd(x,y,go,clk,zout); input [3:0] x; input [3:0] y; input go; input clk; output [3:0] zout; wire [3:0] xsuby, ysubx; wire [3:0] zout1, zout2; wire [3:0] regx, regy; wire xlty, xsel, ysel, xld, yld, dld, xneqy; control cc (clk,go,xneqy,xlty,xsel,ysel,xld,yld,dld); mux421 m1 (x, xsuby, xsel,zout1); mux421 m2 (y, ysubx, ysel,zout2); reg4 xreg (zout1, clk, xld, regx); reg4 yreg (zout2, clk, yld, regy); sub4 s1 (regx, regy, xsuby); sub4 s2 (regy, regx, ysubx); comp4 c1 (regx, regy, xlty); neq4 n1 (regx, regy, xneqy); reg4 d (regx, clk, dld, zout); endmodule

verilog laboratory manual

Documents