verification futures the next three years · arm-based soc development palladium hybrid, ... –key...
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3 © 2014 Cadence Design Systems, Inc. All rights reserved.
November 2011 • SoC Integration Challenges
are the next frontier
4 © 2014 Cadence Design Systems, Inc. All rights reserved.
November 2011 • SoC Integration Challenges
are the next frontier
• Ensuring new design IP
correct by construction
5 © 2014 Cadence Design Systems, Inc. All rights reserved.
November 2011 • SoC Integration Challenges
are the next frontier
• Ensuring new design IP
correct by construction
• Need for automation for
common SoC components
like Interconnect
infrastructure
6 © 2014 Cadence Design Systems, Inc. All rights reserved.
November 2011 • SoC Integration Challenges
are the next frontier
• Ensuring new design IP
correct by construction
• Automation for common SoC
components like Interconnect
infrastructure
• Reducing barriers to
migration across simulation
engines
7 © 2014 Cadence Design Systems, Inc. All rights reserved.
November 2011 • SoC Integration Challenges
are the next frontier
• Ensuring new design IP
correct by construction
• Automation for common SoC
components like Interconnect
infrastructure
• Reducing barriers to
migration across simulation
engines
• HW/SW Challenges • Simulation performance
• Debug
9 © 2014 Cadence Design Systems, Inc. All rights reserved.
Evolution of integrated end-to-end platforms Enabling verification reuse and portability
2011 2012 2013 2014 2015
Sim VIP
Catalog
Forte™
Jasper®
Protium™
Safety
Palladium®
XP II, Hybrid ARM Solution
Interconnect
Validation
IEEE1801
Debug
Analyzer
VIP for
Palladium®
In-Circuit
Acceleration
Cadence System Development Suite
+ Forte & Jasper M&As
+ Incisive & VIP leadership
+ Hybrid & Perspec for software driven
verification technology
+ ARM, MDV, FuSa, MS, LP solutions
VSP
Incisive Virtual Prototyping
CtoS
Cynthesizer
High-level
Synthesis
JasperGold
+ IFV/IEV
Formal
Verification
Incisive
Simulation
Palladium™
Emulation &
Accelerattion
Protium™
FPGA Based
Prototyping
Verification IP Verification IP
Incisive Debug Analyzer, SimVision Debug Analysis
vManager Plan & Management
Perspec™ System Verifier System-level Use-Case Verification
TLM Design & Verification Stratus, Incisive, UVM-ML
Metric Driven Verification vManager, Incisive, Palladium, VIP, JasperGold
ARM-based SoC Development Palladium Hybrid, AMBA VIP/IPK, IWB, Perspec
Low Power CPF & IEEE1801, Palladium DPA, JasperGold LP
Mixed Signal Incisive DMS, AMS Designer, Spectre
Functional Safety Incisive Fault Simulator (JasperGold, Palladium)
Palladium
Hybrid
Low Power &
Mixed Signal
10 © 2014 Cadence Design Systems, Inc. All rights reserved.
• Multi-user / multi-project environment
• Database-driven for massive scaling
• Instant access to real-time reports
• Continuous operating modes
• Automatic data management
• Synchronous information
A New Era in Verification Management…
Verification is a team activity
Plans
Coverage
Results
Verification Engines
User Interface
Client #2
User Interface
Client #n
User Interface
Client #1
Incisive
vManager
Verification
Database
LAN
Incisive
vManager
Application
11 © 2014 Cadence Design Systems, Inc. All rights reserved.
• Formal pioneers consider it critical for RTL Designers to be active in verification effort
• Design and verification knowledge to be shared and maintained cross teams and cross projects
Formal-assisted design methodology
Impact
• Reduce costly and long design loops by enabling backend work flows to work on higher quality RTL design
• Design intent and validation collateral maintained across design projects
• Boost the overall TTM and quality of products
FMCAD 2012
12 © 2014 Cadence Design Systems, Inc. All rights reserved.
90’s 00’s 10’s 20’s
ROI Quality
Cost
Risk
Schedule
Spectrum of Formal Verification Solutions
Formal Verification in the Mainstream !
$$ Saving Integrate Verify Design Post-Si Arch
Arch Integrate Verify Design Post-Si
13 © 2014 Cadence Design Systems, Inc. All rights reserved.
Customer Design
Compute Subsystem
A15 x 4
Coherent Fabric
A7 x 2
Palladium Hybrid Early SW & System Validation
Customer Design (no RTL changes)
SoC Interconnect Fabric
DDR3 Display
INTC
Timer
CSI
DSI
UART
GPU Memory
Controller SATA
USB3
…
System
Boot
Peripheral Fabric
USB2
Ethernet
SW Integrator Solution
UARTs Timers
Fast
Processor
Model
A15 x 4
Coherent Fabric
A7 x 2
TLM2
AXI4 or ACE-Lite Interrupts
Smart DDR MM
eMMC
Interrupt
Manager
TLM/RTL
Bridge
Reconfigurable Interconnect
CPU Sub-system RTL I/F
Reset
Manager
Customer RTL
SW Integrator RTL
TLM
Back-Door I/F
Color Key:
Validate SoC + OS at 5-10 MHz on PXP High-performance memory coherency
Execute SW at 100MHz With standard or custom processor models
Shorten SoC Debug System Messages
HW / SW Debuggers
Plug and Play Integration with RTL SoC-specific transactors and RTL I/F
TLM
Memory
Smart
DDR
Resets
14 © 2014 Cadence Design Systems, Inc. All rights reserved.
Perspec System Verifier Solution
• 10x productivity for SoC complex test
creation
• Abstraction: UML style use-case diagrams
• Automation: system use-case test
generation
• Portability: reuse across all execution
platforms
• Measurement: SoC-level HW/SW
coverage metrics
15 © 2014 Cadence Design Systems, Inc. All rights reserved.
What will drive verification in the next 3 years ?
16 © 2014 Cadence Design Systems, Inc. All rights reserved.
Analysis traffic
Verification is changing… Power, Performance and Thermal Considerations
Performance
Analysis Thermal
Analysis
Power
Analysis
Architecture
System
• Performance goals/metrics
• Modeling/abstraction
• Key traffic data generated by
verification
• Use-case and SW-driven TB
increase value for analyses
Verification
• Requires physical for accuracy
• Packaging/ambient modeling
Implementation
Package
Board
17 © 2014 Cadence Design Systems, Inc. All rights reserved.
• Advanced Driver Assist Systems – Image video processing
– Sensor fusion
– Functional safety
• Infotainment systems – HiFi audio processing
– Voice triggering
– Active noise cancellation
• In-vehicle Networking – ADAS, infotainment, gateways, cameras, etc. will all use Ethernet
– Key Cadence IP to build and verify Ethernet networks
Automotive Challenges Mixed-Signal and Safety concerns
ADAS
ECU
ECU
Automotive
Ethernet Ethernet
Camera
Infotainment
Head Unit
Lidar/Radar
Sensors
V2X
19 © 2014 Cadence Design Systems, Inc. All rights reserved.
System Development Suite Engines
Analysis traffic
Implementation
Package
Board
Thermal
Analysis
Power
Analysis
Verification
Architecture
System
Performance
Analysis
SoC Power-Performance-Thermal
Incisive
Voltus
Stratus
Encounter
Sigrity
Power DC
IWB
VMgr
Perspec SVR
VCD, SAIF
Power map
Thermal map
Power
profile
SoC sim
configuration
Analysis
scoreboard
Floorplan
Layout
Floorplan
Layout
Allegro
Palladium
20 © 2014 Cadence Design Systems, Inc. All rights reserved.
• High initial quality
• 10+ year reliability
• Predictable failure recovery or fail safe mode
• Proven technology in connected flow
• Traceable requirements throughout
• Integrated safety verification
Cadence Functional Safety Solution
ISO 26262
IP
Re
qu
ire
men
ts
TC
L
Safety Manual
Design & Implementation
Signoff & Validation
Functional Verification
Safety Verification
Safety Testing (ASIL)
NEW!
21 © 2014 Cadence Design Systems, Inc. All rights reserved.
Metric Driven (HW Coverage, SW Coverage, Use-Cases,
Mixed-Signal, Functional Safety, Performance,
Power, Bug Count, Code Churn etc etc)
The Eras of Verification Looking at the past and into the future
SW-Driven Verification Era
Directed Testing Era
(aka “Stone Age)
HVL Driven Verification Era
1980
1990
2000
2010
2020