vdat2014 submission 97

8/9/2019 Vdat2014 Submission 97

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LOW POWER DRAM CELL DESIGN ON 32 nmTECHNOLOGY

Prateek Asthana, Sangeeta Mangesh

JSS Academy of Technical Education ,Noida

[email protected], [email protected]

Abstract — In this paper average power consumption of DRAMcell designs have been analyzed for the Nanometer scalememories. Many modern processors use DRAM for on chipdata and program memory. The major contributor of power inDRAM is the off state leakage current. Improving thepower efficiency of a DRAM cell is critical for theimprovement in average power consumption of the overallsystem. 3T DRAM cell, 4T DRAM and 3T1D DRAM cells aredesigned with the schematic design technique and theiraverage power consumption are compared using TANNER

EDA tool .A novel technique is used to optimize the averagepower consumption of 3T DRAM and 3T1D DRAM cell. Keywords-- L ow Power, DRAM, 3TDRAM, 4TD RAM , 3T1D DRAM

I. INTRODUCTION

Memories play an essential role in design of any electronicsdesign where storage of data is required. Memories are usedto store data and retrieve data when required. Read OnlyMemory (ROM) and Random Access Memory (RAM) aretwo types of mem ries used in modern day architectures.Random Access Memory is of two types Dynamic RandomAccess Memory (DRAM) and Static Random Access

Memory (SRAM). SRAM is static in nature and faster ascompared to DRAM.SRAM is expensive and consume less power. SRAM have more transistors per bit of memory.They are mostly used as cache memories. DRAMS on theother hand are dynamic in nature and slower as compared toSRAM. DRAM are expensive and consume more power,they require less transistor per bit of memory. They aremostly used as main memories. DRAM is widely used formain memories in personal and mainframe computers andengineering workstation. DRAM memory cell is used forread and write operation for single bit storage for circuits. Asingle DRAM cell is capable of storing 1 bit data in thecapacitor in the form of charge. Charge of the capacitordecreases with time .Hence refresh signals are used torefresh the data in the capacitor. When a read signal readsthe data it refreshes it as well. Many different cell designsexist for modern day DRAM cell. These designs aredifferentiated by the no. of transistors used in theirdesigning. As the no. of transistors increase, powerdissipation also increases. DRAM is one of the mostcommon and cost efficient random access memory used asmain memory for workstations. The charge stored inmemory cell is time dependent. For high density memories

DRAM cell with low power consumption and less area are preferred.

Many different cell designs exist for modern day DRAMcell. These designs are differentiated by the no. oftransistors used in their designing. As the no. of transistorsincrease, power dissipation also increases. DRAM is mostcommon and cost efficient random access memory used asmain memory for workstations. The charge stored in

memory cell is time dependent. First DRAM was proposedin 1971, having 1 kb capacity. This capacity has increasedfrom 1kb to 1-10 GB level today.

II. LITREATURE SURVEY1T1C DRAM Cell:The information is stored as different charge levels at acapacitor in conventional 1T/1C DRAM. The advantage ofusing DRAM is that it is structural simple: only onetransistor and capacitor are required for storing one bit,compared to six transistors required in SRAM. This allowsDRAM to have a very high density. The DRAM industryhas advanced over a period of time in packing more andmore memory bits per unit area on a silicon die. But, thescaling for the conventional 1Transistor/1Capacitor (1T/1C)DRAM is becoming increasingly difficult, in particular dueto a capacitor has become harder to scale, as devicegeometries shrink. Apart from the problems associated withthe scaling of the capacitor, scaling also introduces yetanother major problem for the DRAM manufacturers whichis the leakage current.

Fig.1.Schematic 1T1C DRAM cell



4T DRAM Cell:

Fig. 2 4T DRAM CELL

The cell structure shown in fig. 2 is a 4T DRAM cellstructure. This DRAM cell design consists of fourtransistors. One transistor is used as a write transistor, theother as a read transistor. Data in DRAM is stored in theform of charge at the capacitance attached with thetransistor structure. There is no current path to the storagenode for restoring the data; hence data is lost due to leakagewith the period of time. Read operation for the 4T DRAMcell is non-destructive, as the voltage at the storage node ismaintained.

3T DRAM Cell:

3T DRAM utilizes gate of the transistor and a capacitance tostore the data value. When data is to be written, write signal

is enabled and the data from the bit line is fed into the cell.When data is to be read from the cell, read line is enabledand data is read through the bit line. 3T DRAM celloccupies less area compared to the 4T DRAM cell.

Fig.3 3T DRAM CELL

3T1D DRAM Cell:

This is a DRAM structure derived from 3T cell, like allDRAM it uses few transistor compared to static randomaccess memory (SRAM). The 3T1D has an advantage overSRAM, is its resistance to process variation, this featurehelps it to be used at low feature sizes. Another advantageof 3T1D DRAM is that it does not slow down as its size is

scaled down.3T1D DRAM uses the gated diode instead ofcapacitor to store the data value. The absence of capacitor

provides significance reduction in power consumption ascompared to previous DRAM cell design.

Fig 4. 3T1D DRAM CELL

III. PROPOSED DESIGN

Gain 3T DRAM Cell:

This cell design is derived from the basic 3T DRAM celldesign. In the design ,the read signal is also shorted to thetransistor connected with capacitance which acts as astorage device. This design modification helps in thereduction of power consumption compared to the traditional3T DRAM cell design. Rest of the structure remains thesame. The gain 3T cell occupies small area as compared totraditional 3T DRAM cell. Average power consumptionanalysis and circuit diagram for the cell has been studiedand values are discussed in the paper.

Power Modified 3T1D DRAM Cell:

3T1D DRAM cell does not use a capacitor to store data

rather than a gated diode is used. This gated diode stores thedata to be used at a later time. In 3T1D DRAM gated diodeis a NMOS device, as the leakage current in NMOS is morecompared to PMOS device .Hence, in this design NMOSgated diode is replaced by the PMOS gated diode. A slightmodification in the design is also made. Average powerconsumption comparison with all previous design has beenmade in the paper.



IV. SCHEMATICS OF CELLSAll simulation carried out on TANNER EDA 14.0 withmodel file of 32nm high performance taken from PTM.Tool used for circuit design is SEDIT and for simulation isTSPICE.

Fig 5. Schematic of 4T DRAM

Fig 6. Schematic of 3T DRAM

Fig 7. Schematic of 3T1D DRAM

Fig 8. Schematic of Gain 3T DRAM

Fig 9. Schematic of Power Modified 3T1D DRAM

V. SIMULATION RESULTSSimulation for all five cells 4T, 3T,3T1D ,Gain 3T,Powermodified 3T1D design are carried out from 0-10ns.Duringthis interval all the four process write ‘0’, write ‘1’, read ‘0’and read ‘1’,are executed. Average power consumption iscalculated for the full 0-10ns duration consisting of all fouroperations.

Operation Time PeriodWRITE ‘1’ 2-3ns

READ ‘1’ 4-5ns

WRITE ‘0’ 6-7ns

READ ‘0’ 8-9ns



Fig 10. Read Write operation of 4T DRAM Cell

Fig 11. Read Write operation of 3T DRAM Cell

Fig 12. Read Write operation of 3T1D DRAM Cell

Fig 13. Read Write operation of Gain 3T DRAM Cell

Fig 14. Read Write operation of Power Modified 3T1D DRAMCell



SUPPLYVOLTAGE

GAIN3T DRAM

POWERMODIFIED

3T1D

0.7 34.0302 3.49716

0.8 54.7457 29.1717

0.9 74.5264 61.7516

1.0 95.9509 147.414

Fig. 16 Bar chart comparing power consumption of dram cell withsupply voltage

VII. CONCLUSION

Graphical comparison of average power consumptionfor the 4T, 3T and 3T1D DRAM cell show that due tothe absence of capacitor, average power consumption of3T1D cell is the lowest among the three. Average

power consumption values generally increases withincreasing temperature and supply voltage values.

Gain 3T cell, having a capacitor has significantly less power consumption compared to the 4T and 3T celldesigns. Average power consumption values from thegain 3T DRAM, remains almost constant throughoutthe temperature variation.

Power modified 3T1D DRAM cell uses less power ascompared to 3T1D DRAM. This average power

consumption is significantly less as compared to thetraditional 4T and 3T DRAM cell. Average powerconsumption for power modified 3T1D compared to the3T1D DRAM cell at lower temperature is less but itexceeds the value of average power consumption of3T1D DRAM at higher temperature.

REFRENCES:

[1] M. S. B. S. Shyam Akashe, "Analysis of power in 3TDRAM and 4T DRAM Cell design for differentTechnology," IEEE, vol. 12, no. 978-1-4673-4805-8,

pp. 18-21, 2012.[2] J. C. H. D. J. V. K. Wing k.luk, "A3-Transistor DRAM

Cell with Gated Diode for enhanced Speed andRetention Time," Symposium on VLSI CircuitsDigest ofTechnical papers, vol. 06, no. 1-4244-0006-6, 2006IEEE.

[3] j.-W. C. a. Y. C. Weijie Cheng, "Design of logiccompatible Embedded DRAM using Gain MemoryCell," ISOCC, vol. 12, no. 978-1-4673-2990-3, pp. 196-199, 2012 IEEE.

[4] H. K. L. H. H. S. J. a. Y. R. Myungjae Lee, "Analysisof Dynamic Retention Characterstics of Nwl Scheme inHigh Density DRAM," IPFA, vol. 13, no. 978-1-4799-0480-8, pp. 641-644, 2013 IEEE.

[5] D. B. S. Z. Yong Sung Park, "Low Power High

threshold LPDC decoder using non-refresh EmbeddedDRAM," JSSC, vol. 49, no. 0018-9200, pp. 1-12, 2014IEEE.

[6] P.-T. H. a. W. H. Mu-Tien Chang, "A 65nm LowPower 2T1D Embedded DRAM With leakage CurrentReduction," IEEE, vol. 07, no. 978-1-4224-1593-9, pp.207-210, 2007.

[7] S. G. R. C. Nivard Asymerich, "Impact of Positive biastempreature instability on 3T1D DRAM cells,"Integration , the VLSI Journal, vol. 45, no. 2011ELsevier, pp. 246-252, 2011.

[8] C. L. X. L. D. B. G.-Y. W. Kristen Lovin, "EmpericalPerformance Models for 3T1D Memories," IEEE, vol.

09, no. 978-1-4224-5028-2, pp. 398-403, 2009.[9] E. Amat, "Strategies to enhance 3T1D DRAM cellvariability robustness," Microelectronics Journal, no.2013 Elsevier, pp. 1-6, 2013.

[10] Tutorial TANNER EDA LEDIT and TSPICE

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vdat2014 submission 97

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