v labs product presentation
TRANSCRIPT
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Vayavya Labs 2009
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Vayavya Labs 2009
Agenda
About Vayavya Labs
Our Vision for ESL (Electronic System Level)
About DDGEN
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Vayavya Labs 2009
About Vayavya Labs
System Level Design Tools and Embedded Design services company
Markets :
– Semiconductors and
– Embedded Design Services
USP :
Significant improvements in TTM, QOR, COR
A new market segment for device driver generation
World’s first automated device driver generator
(US patent pending)
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Vayavya Labs 2009
Agenda
About Vayavya Labs
Our Vision for ESL About DDGEN
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Vayavya Labs 2009
Pain Points in Lower Layers -1
PainPoints
Hardware/software integration – aka device drivers
Market Needs
Productivity improvement tools
Golden reference model for the hardware enabling auto-generation of the drivers/firmware
Application, GUI etc
Middleware Protocols
Operating System &Associated Components
Firmware & Device Drivers
Embedded hardware
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Vayavya Labs 2009
Pain Points in lower layers -2
Automatic Generation of device drivers can significantly reduce the overall cost
& efforts
Number of SOCs 2(X86 and MIPS based)
App Domain CE, DTV
Operating System MontaVista Linux
On chip peripherals(drivers) 23
On board peripherals(drivers) 7
Effort for first release of firmware/drivers 78
Team Size 14
Engineering Support Team 5
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Vayavya Labs 2009
Hardware and Software differ in abstractions and design flows
Vayavya bridges the design flows
Reuse
Common Framework
Automatic code generation
80’s & later
90’s & later
2000 & now
Tools Evolution
UML
ESL 2.0
ESL
HDL HLL
Schematics Assembly
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Vayavya Labs 2009
Agenda
About Vayavya Labs
Our Vision for ESL
About DDGEN
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Conventional way of device driver development
Vayavya Labs 2009
IC Team
8.1 LINE CONTROL
REGISTER
.... Details on each of
bits in ..
Device Drivers
Software
architecture
considerations
Data sheetSW Team
F()
{
// …
}
FCurrently ad-hoc Methods (Word, Excel etc.) used to communicate information among IC and Software teams
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Vayavya Labs 2009
• DDGEN methodology helps formalize communication between hardware and software teams
DDGen Use case
DPS: Device Program Sequence
RTS: Run Time Specification
DDGen: Device Driver GeneratorDevice Drivers
Device Driver writer
1. Registers
2. Interrupts
3. Features
4. …
1. OS
2. ISR
3. buffer
4. …
DDGen
DPS file RTS file
F()
{
//
}F
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Vayavya Labs 2009
Software Space exploration using DDGEN
Device Drivers
1. Registers
2. Interrupts
3. Features
4. …
1. OS
2. ISR
3. buffer
4. …
DDGen
DPS file RTS file
F()
{ //
}F
Blocking/non-
blocking API
Buffering
• Pingpong
• Circular
Polling/
Interrupts
Split/Single ISR
Effective exploration of software design by relevant specification in RTS. Think in problem domain than implementation domain
Sync/AsyncDevice Driver writer
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DDGEN- Product details
~300% productivity gain in device driver development
Generates
ANSI C code including OS calls. Fully functional device driver
Unit test code of device driver
Supports
A range of device complexities: UART, I2C, USB, Ethernet, PCI, PCI Express, …
IP-XACT compliant input
Many popular OS drivers, including null OS
Vayavya Labs 2009
DDGen
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Vayavya Labs 2009
DDGEN derived utilities
DocGen– Generates HTML documentation for the device
RegGen– Generates HDL code for the register banks of the device
from the register specification in DPS
Verigen– Generates SystemVerilog test bench template for
functional verification
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DPS Entities
Device Specification
Register Specification
Interrupt Specification
Feature Specification
FIFO Specification
Bus Specification
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Device Specification
15
device_spec
{
device_name = pc16550D;
manufacturer_name = "National Semiconductors";
device_version = "D";
device_class = STD_D_C;
device_input_clock = 1.8432M, 3.072M, 18.432M;
}
Vayavya Labs 2009
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Register Specification8.1 LINE CONTROL REGISTER
.... Details on each bit follow:
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
The encoding of bits 0 and 1 is as follows:
Bit 1 Bit 0 Character Length
0 0 5 Bits
0 1 6 Bits
1 0 7 Bits
1 1 8 Bits
Bit 2: This bit specifies the number of Stop bits transmitted and received in each serial character. If bit 2
is a logic 0, one Stop bit is generated in the transmitted data. If bit 2 is a logic 1 when a 5-bit word
length is selected via bits 0 and 1, one and a half Stop bits are generated. If bit 2 is a logic 1 when
either a 6-, 7-, or 8-bit word length is selected, two Stop bits are generated. The Receiver checks the
first Stopbit only, regardless of the number of Stop bits selected.
Bit 3: This bit is the Parity Enable bit. When bit 3 is a logic 1, a Parity bit is generated (transmit data)
or checked (receive data) between the last data word bit and Stop bit of the serial data. (The Parity
bit is used to produce an even or odd number of 1s when the data word bits and the Parity bit are
summed.)
Bit 4: This bit is the Even Parity Select bit. When bit 3 is a logic 1 and bit 4 is a logic 0, an odd number
of logic 1s is transmitted or checked in the data word bits and Parity bit. When bit 3 is a logic 1 and
bit 4 is a logic 1, an even number of logic 1s is transmitted or checked.
CONTROL_REGISTERS {
LCR [8] @ 1 {
type = RW;
field wls <0:1> {
type = RW;
clearing_mode = DC;
value_on_reset = 0;
enum {
FiveBit = 0;
SixBit = 1;
SevenBit= 2;
EightBit= 3;
}
field stb <2:2> {
type = RW;
clearing_mode = DC;
value_on_reset = 0;
enum {
OneStopBit = 0;
OneAndHalfStopBit = 1 when(LCR.wls==0);
TwoStopBit = 1 when(LCR.wls==1||2||3));
}
}
. . . (contd.)
Vayavya Labs 2009
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Interrupt Specification
interrupt_spec {
interrupt_pending = IIR.IntPend(0) ;
IIR.IntID(RxLineStat) {
int_type = error ;
enable_field = IER.elsi(1) ;
disable_field = IER.elsi(0) ;
clear_field = COR LSR ;
source_field = LSR.pe(1)
|| LSR.oe(1)|| LSR.fe(1)
|| LSR.bi(1)
||LSR.erxfifo(1);
}
IIR.IntID(RxDataAv) {
int_type = device_read ;
enable_field = IER.erbfi(1) ;
disable_field = IER.erbfi(0) ;
clear_field = AUTO_CLEAR ;
}
IIR.IntID(TxRegEmpty) {
int_type = device_write ;
enable_field = IER.etbei(1) ;
disable_field = IER.etbei(0) ;
clear_field = AUTO_CLEAR ;
}
}Vayavya Labs 2009
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Feature specification
18
PROGRAMMABLE BAUD GENERATOR
The UART contains a programmable Baud generator that is capable of taking any
clock input from DC to 24 MHz and dividing it by any divisor from 2 to 216- 1. The
output frequency of the Baud Generator is 16 X the Baud [divisor# = (frequency
input) / (baud rate X 16)]. Two 8 bit latches store the divisor in a 16-bit binary
format. These divisor latches must be loaded during initialization to ensure proper
operation of the Baud Generator. Upon loading either of the divisor latches, a 16-bit
baud counter is immediately loaded. Table III provides decimal divisors to use with
crystal frequencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz, respectively. For
baud rates of 38400 and below, the error obtained is minimal. The accuracy of the
desired baud rate is dependent on the crystal frequency chosen. Using a divisor of
zero is not recommended.
feature configure_baud_rate
{
input int baud (50,75,110,9600,128000);
local int Divisor;
Divisor = DEVICE_INPUT_CLOCK
/(baud * 16);
LCR.dlab = TRUE;
DLL = Divisor & 0x00ff;
DLM = (Divisor >> 8) & 0x00ff;
LCR.dlab = FALSE;
}
Vayavya Labs 2009
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FIFO Specification
Vayavya Labs 2009 19
FIFO Rcv{
associated_feature_name = device_read;
enable_field = FCR.FifoEnb(1);
enabled_status_field = IIR.FifoEnbd(1);
max_fifo_size = 16;
fifo_size = FCR.RcvTrgr;
}
FIFO Tx{
associated_feature_name = device_write;
enable_field = FCR.FifoEnb(1);
enabled_status_field = IIR.FifoEnbd(1);
max_fifo_size = 16;
fifo_size = FCR.RcvTrgr;
}
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Bus Specification
Example 1: (UART)
Example 2:
Vayavya Labs 2009 20
bus_spec
{
register_acces_type = memory_mapped, io_mapped;
}
bus_spec
{
register_acces_type = memory_mapped, io_mapped;
data_transfer_type = spi, i2c;
spi_mode = 1,2;
base_address = 0xA000 – OxB000;
}
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21
RTS Entities
Processor Specification
OS Specification
ISR Specification
BSP Specification
Bus Specification
Error Handling Specification
Entry point Spec
Code Gen Spec
Buffer Spec
Compiler Spec
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22
RTS for UART
PROCESSOR_SPEC
{
PROCESSOR_NAME = ARM9 ;
CLOCK_FREQ = 32Mhz;
}
Processor Specification BUS Specification
ISR_SPEC
{
ISR_TYPE = single;
ISR_DRIVER_SYNC = global_var;
ISR_NO = 7;
}
ISR Specification BSP Specification
BUS_SPEC
{
REG_ACCESS_TYPE=MEMORY_MAPPED;
TRANSFER_MODE = PIO;
BASE_ADDRESS = 0x22;
}
BSP_SPEC
{
DEVICE_INPUT_CLOCK = 3.072MHz ;
}
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23
OS
{
OS_NAME = LINUX ;
RE_ENTRANCY =
BLOCK_BY_DISABLING_INTERRUPTS;
KERNEL_VERSION = “2.6.22”;
VIRTUAL_MEMORY = YES;
}
OS Specification Entry Point Specification
Error Handling Specification
ENTRY_POINT
{
QUALIFIER = blocking;
}
ERROR_HANDLING
{
RETRY = 3;
TIMEOUT = 9ms;
}
continued...
Vayavya Labs 2009
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24
COMPILER_SPEC
{
COMPILER_NAME = GCC ;
}
Compiler Specification Codegen Specification
BUFF_SPEC
{
BUFF_MANAGEMENT = DRIVER;
RECEIVE
{
BUFFER_TYPE = circular;
MTU = 256;
}
}
Buff Specification
CODEGEN_SPEC
{
field_usage_comments = yes;
TYPEDEFS
{
int = int32 ;
char = int8 ;
}
}
continued...
Vayavya Labs 2009
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Vayavya Labs 2009
Pilot Results
Customer-1
Device Details SoC for entertainment platform
Peripherals on SoC LCD, PIO, Interrupt Controller, Timers
Application code size, for manual written drivers 5 KB
Application size using tool generated drivers 5.28KB
No. of days for manual drivers writing 17 days
No. of days for drivers generation (by tool) 6 days
Effort and Time savings Close to 200%
% Code size overhead (by use of tool) 5.6%
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Vayavya Labs 2009
Pilot Results -2
> 300%Effort and Time savings
90+ daysTotal number of days for manual driver generation ( approx)
31 DaysTotal number of days for automated driver generation
2 DaysIntegrating driver code with environment
10 daysValidating driver code for functionality
19 DaysDevice Specification Capture
DMA, Interrupt handler,
Event Handler, Clock
distribution UnitDevice Details
Customer-2
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Vayavya Labs 2009
Business Model
Target
Semiconductor firms
• SOC, ASIC, FPGA
• IP vendors
VLSI and Embedded system design services firms
OEMs/ODMs
EDA and embedded tools vendors ( partnerships)
Business model
Tool licensing
Design Services using tool – optimised cost & time benefits
Tool customization and value-add services
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Vayavya Labs 2009
DDGEN Roadmap
DM355 support
Eclipse GUI
BSPGEN 1.0
CMSIS support
Optimization
knobs
IPXACT Vendor
Extensions
ModelGen 1.0
Sept 2009 Dec 2009 June 2010
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Vayavya Labs 2009
Thank You