Using GoldenGate to Verify and Improve Your

Designs Using Real Signals

Enabling more complete understanding of your designs

Agilent EEsof EDA

1

Outline

• What problems do designers face?

• Main point of this presentation

• What does GoldenGate enable you to do?

• Ways GoldenGate simulates modulated signals

• Examples

• Summary

2

What problems do designers face?

Will my design meet specifications?

What part of my design is causing the biggest degradation?

Does varying a parameter improve performance? If so, which parameter and how much?

3

Main point of this presentation

RFIC designs are under-characterized

One- or two-tone simulations are useful, but not sufficient

Need modulated signals for better understanding, more complete verification

4

What does GoldenGate enable you to do?

Simulate modulated signals from Ptolemy or files, with correct characteristics – bandwidth, peak-to-average power ratio, etc.

Include interfering signals

View specification-compliant results

View performances at different points in your design

Run simple simulations, quickly, for design investigation

5

Ways GoldenGate simulates modulated signals

“Virtual Test Benches” – Easiest if simulating WLAN 802.11a, 802.11b (WiFi), WMAN 802.16e (WiMax), TDSCDMA, or 3GPPFDD (WCDMA)

Export sources and sinks from Agilent Ptolemy – Numerous signals available – 3GPP LTE, UWB, GSM, EDGE, DTV, etc.

From .txt, .sig, .ascsig, or .wfm files. May be created with Agilent Signal Studio

Generic modulated signals (QPSK, OQPSK, or pi/4 DQPSK) from the ENVELOPE source library in ggLib

6

Advantages and disadvantages of each method

Virtual Test Benches – Easy setup, specification-compliant, results displayed automatically. Requires Ptolemy license.

Exported sources and sinks – Great flexibility, specification-compliant. May need Agilent help to create, requires Ptolemy license.

From file – no license needed, but may only change carrier frequency and signal amplitude, limited post-processing.

Generic modulated signals – no license needed, but may not be specification compliant, limited post-processing.

7

Examples

Power amplifier with WLAN signal

LNA degradation due to noise, blocker

Power amplifier with LTE signal

“Raw” EVM and specification-compliant EVM of baseband chain

“Raw” EVM of receiver (a predictor of BER)

“Raw” EVM of transmitter versus variable gain amplifier gain setting

8

Power amplifier with WLAN signal (1)

Spirals modeled using Momentum

Power amplifier subcircuit

Simulation “test bench”

9

How does Momentum help you in RFIC design?

• Create more accurate models than those in your PDK

• Create models for structures or components not in your PDK

• Check coupling effects due to adjacent structures in layout

• Use directly within the Cadence Virtuoso layout environment

• Integrate results with extracted parasitics from rest of layout

• Visualize current flow

10

Momentum capabilities and features

• Full-wave electromagnetic solver based on Method of Moments – gives full dispersion and radiation

• Quasi-static EM solver for faster modeling of larger designs (more layout structures but small compared to wavelength)

• Fully integrated in Cadence Virtuoso layout environment

• Very efficient swept frequency analysis

• Includes sidewall coupling between thick metal traces

• Automated multi-threading dramatically speeds simulations when multiple CPUs available

• Comprehensive data display for viewing and post processing results

11

Example of multiple, coupled spiralsMultiple spirals, including coupling

Use S-parameterresults in othersimulations

5 minutes 10 secs. to simulate 0-50 GHzusing 8 CPUs, via multi-threading. 734 Mbytes.

12

Using Momentum components with Cadence Assura extraction tool• Momentum component must be created without a reference pin

• Assura rules file (extract.rul) must be modified to define pinLayers and the geomConnect rule

• Momentum component must be defined as a blackbox to ensure the blackbox cell is extracted and keeps connectivity with the rest of the circuit

13

Overview of Momentum use model – assuming what you want to simulate is already a cell• Make Virtuoso cell a Momentum cell

• Simplify via arrays

• Define substrate stack up if not supplied in PDK

• Assign ports to pins in layout

• Check and/or set simulation options

• Run the simulation

• Automatically generate a model that may be used in other simulations

14

Will simulate spiral inductor from RFIC VCO

VCO spiral inductorlayout view

15

Create Momentum view from layout view (1)

Select Tools>Momentum

Creates Momentum-Virtuoso menu

16

Via arrays in momentum view should be simplified

Via arrays

17

Simplifying via arrays – flatten layout

Select component and flatten it so it may be edited

Select these options

After executing, should be ableto select individual via elements

18

Perform via simplification

Select Pre-Processing > Perform Via Simplification…

Via arrays after simplificationThese settings work

well for this design

19

Specify substrate file

*.tch files definestack up in text file.*.ltd files may beused in SubstrateEditor GUI.

Use Substrate Editor to see or modifysubstrate materials or stack up

20

Define simulation frequencies

Adaptive frequency sampling minimizes number of pointsrequired to accurately characterize frequency response.May add specified frequency points, also.

Dots: actually simulated pointsTrace: calculated response

21

Define ports

Auto-generate is easiest method

One port is assigned to each pin in the layout

22

Specify simulation options

RF mode should befaster if layout is electrically small.

“3D-distributed”includes horizontal sidewall currents

“2D-distributed” used for vias because original via arrays would not have significant horizontal sidewall currentsUsing Edge Mesh

improves accuracyslightly, but problem size becomesmuch larger

Recommended for relatively thick tracesclose to each other

23

Run simulation

Substrate onlyhas to be computed once

Layout is electrically smallbelow 429 GHz

Multi-threadingspeeds up simulation –automaticallydetects 8 CPUs

24

Simulation results

Dots: actually simulated pointsTraces: responses calculated from

Adaptive Frequency Sampling algorithm

25

Create simulator views to re-use results

Creates symbol without reference pinCreates symbol(s) with and/orwithout reference pin

New views created

Symbol view insertedin a schematic

26

Computing L, R, and Q from the Momentum S-parameter model

This is the simplest equivalentcircuit model for computing Q.

L R Q

27

JivaroGG Key Features

Page 28

Jivaro for GoldenGateWhat does it do?• Jivaro for GG is a model (RC parasitics netlist) order reduction tool based on

several different algorithms that reduce the order while keeping the accuracy within specified tolerances.

• Includes error control, that supervises the accuracy of the different algorithms. The default is very conservative leading to very accurate reduction up to highest frequencies.

• The default accuracy can easily be degraded by the user in order to gain higher reduction rate.

• Goals are:– Get the same simulation results, but:– Smaller memory footprint for GoldenGate simulation– Enhance already best in class speed of GoldenGate

• Allows the maximum utilization of simulation resources and hardware

29

Qualifying statement for nodes definition

VSS

VDD

IN OUT

VDD

VSS

IN OUT

Schematic Layout RC extractednetlist

What are internal or external nodes?

For JivaroGG there are 2 types of nodes:External nodes: Primary ports (*|P in dspf) and Instance ports (*|I)Internal nodes

The external nodes cannot be reduced, only internal nodes can.Parasiticdevices

Non parasiticdevices

VDD

VSS

IN OUT

Internal node

Primary portInstance port

Page 30

Graphical Interface

A graphical interface to select the database view to reduce and to set JivaroGG reduction options is available under Analog Design Environment (Tools->Jivaro Parasitic Reducer…)

Page 31

Reduction test cases

Oscillator Receiver

Page 32

extracted reduced ratio

res 45876 17191 62%

cap 69708 3210 95%

indInternal

nodes33610 3903 72%

CPU: CR 50m 28s 17m 06s

memory 4089M 1479M

extracted reduced ratio

res 498701 278725 44%

cap 1233503 110355 91%

indInternal

nodes263473 88214 66%

CPU: DC 4h 11m 1h 6m

memory 4652M 3093M

Reduction test cases, continued…

Transmitter VCO

Page 33

extracted reduced ratio

res 987980 84089 91%

cap 90426 40778 54%

indInternal

nodes492203 20362 95%

CPU:CR 11h 37m

memory ??? 65863M

extracted reduced ratio

res 5753 1883 68%

cap 156082 1396 99%

indInternal

nodes4127 495 88%

CPU:CR 52m 51s 10m 49s 80%

memory 3269M 394M 88%

Power amplifier with WLAN signal (2)

Virtual Test Bench replaces source.

Results taken from output node

This is same schematic as SP, gain comp., IP3simulations

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Specify Virtual Test Bench parameters

From ADE windowSpecify frequency, power, source filtering, measurement types, etc.

35

Automatically-generated results

Out of specification

Simulation takes only about 20 seconds to

measure 3 frames of data!

36

Sweep modulated source power

Simulation takes only about 2 mins. 10 seconds!

37

Examples

38

LNA degradation due to noise, blocker (1)

Spirals modeled using Momentum

LNA subcircuit

Simulation “test bench”

39

Reducing input power degrades constellation, spectrum, and EVM

40

With blocker tone at input

Sinusoidal blocker power and offset frequency may be set arbitrarily. May have multiple blockers.

All these simulations use the same test bench.

41

Examples

42

Power amplifier simulation with LTE signal

LTE source and sink components exported from ADS Ptolemy.

43

LTE source and sink parameters

All parameters are from original Ptolemy schematic. Modify as needed or use defaults.

SourceSink

44 May 19, 2009

LTE simulation outputs (1)

45

LTE simulation outputs (2)

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Examples

47

“Raw” EVM of baseband chains

I-channel baseband chain

1) If needed, correct for average gain, phase shift, and delay. 2) How well do vectors match input vector, at each time point?

Relatively fast simulation.Shows where and how much degradation occurs.

48

Baseband I and Qmodulationsource

Qin(t)

Iin(t)

Qin(t)

Q-channel baseband chain

I1(t)

Q1(t) Q2(t)

I2(t)

I1(t)

Q1(t)

I2(t)

Q2(t)Iin(t)

Simulation “test bench”

Baseband source exported from Ptolemy

Voltage-controlled voltage sources enable differential signal with DC bias at input

Analog filter with tunable bandwidth

49

Simulation outputs

Specify reference (input) and test (output) vectors.

Prior to adjusting time delay

After adjusting time delay

50

EVM improvement after increasing filter bandwidth

Simulation takes about 9 minutes

51

Specification-compliant EVM – requires sink from Ptolemy

Baseband source exported from Ptolemy

Baseband sink exported from Ptolemy

Sink parameters

52

Specification-compliant simulation outputs

With original, too-narrow filter bandwidth

53

Comparing “raw” and specification-compliant EVMs

Filter bandwidth= 7.77 MHz

Filter bandwidth= 12.46 MHz

Simulation time (for each filter bandwidth setting)

“Raw” EVM 18.8% 9.1% 9 minutes

Specification-compliant EVM

23.7-24.1% 11.82-11.88% 2 hours, 1 min., for three frames

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Examples

55

Receiver simulation test bench

LNA

LO signals generated from Noisecor files

WLAN RF sourceexported from Ptolemy

DC offset cancellation circuit

Variable gain amplifiers

Tunable, analog low-pass filter

56

Calculated “raw” EVMs

Test points “raw” EVMLNA output 3.3%Mixer outputs 3.5%DC offset cancellation circuit outputs 2.3%1st variable gain amplifier outputs 2.2%Tunable filter outputs 12.8%2nd variable gain amplifier outputs 12.4%

Most degradation occurs in baseband low-pass filters.

100 usec. simulation takes 50 minutes. A BER simulation would take days.

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Examples

58

How does EVM change at various points as VGA gain is adjusted?

PowerAmp

I-channel baseband chain

Q-channel baseband chain

Baseband I and Qmod.source

Qin(t)

Iin(t)

I1(t) I2(t)

RFin(t)RFout(t)

I1(t)

Q1(t)

I2(t)

Q2(t)

RF inRFin(t) RFout(t)

VGA gain versuscontrol voltage

Qin(t)

Iin(t)

59

“Raw” EVM table

VGA ControlVoltage

Filter Outputs VGA Outputs Mixer Outputs Power Amp. output

1.2 9.7% 13.1% 13.1% 12.9%1.25 9.7% 18.0% 18.2% 17.5%1.3 9.7% 20.6% 21.3% 19.3%1.35 9.8% 18.1% 19.3% 18.2%

1.4 9.8% 13.5% 13.6% 11.8%1.45 9.9% 10.7% 9.7% 16.2%

Simulation time: 3 hours 59 minutes.Shorten by reducing number of swept values.

Filter contribution to EVM is roughly constant

VGA contribution to EVM varies a lot

Power Amp only contributes to EVM when VGA gain is at its maximum

60

RF/Mixed-Signal Verification Transient / Verilog-AMS Co-sim

GoldenGate

DigitalSimulator

Verilog-AMSCo-simModule

New

Problem: RF and mixed-signal blocks are simulated separately today• PA with digital control / linearization• AGC, PLL• DAC• Digital Filtering

Solution: Transient / Verilog-AMS Co-sim• Simulate a combination of RF transistor level

blocks and digital/mixed-signal blocks• Full AMS support via co-simulation with a 3rd party

digital simulator (ModelSim, NCsim)

Future: Envelope / Verilog-AMS Co-sim (2009)

Page 61

RF/Mixed-Signal VerificationDigital State Sweeps Digital Control

Circuitry RF Circuitry

Problem: increasing use of digital control circuits driving RF circuits• Today, digital control circuits are replaced by

idealized sources for RF simulation• Simulations are manual, error-prone

Solution: Digital State Sweeps• Use VCD files from digital simulations to

automatically drive RF simulations• Quickly sweep through all control states

Discover mixed-signal interface problems earlier in the development process

RFSimulation

Digital Simulation

VCDFile

DSFFile

Page 62 Agilent Restricted

Digital State Sweep Example -- Variable Gain Amp

Swept Gain at 16 digital control states Control voltage vs. control state

Gain vs control voltage

Agilent RestrictedPage 63

GoldenGate DFY Tools & Capabilities

Fundamental DFY Capabilities• Corners, Monte Carlo• Correlation Analysis• Yield Analysis• Block Specific Statistical Variation• Trial Rerun

Advanced Sampling Algorithms• Latin Hypercube Sampling• Hammersly Sequence Sampling • Boundary Mode• Orthogonal Arrays

Parallel Simulation Tools• Job Manager• Parallel Monte Carlo Controller• Quad Pack Licensing• Parallel MC/Corner Licensing

Variable #1

Varia

ble

#2

x x x

x x xx x x

x x x x x

x

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GoldenGate Advanced Monte Carlo Modes

Variable #1

Varia

ble

#2

Variable #1

Varia

ble

#2

Variable #1

Varia

ble

#2

x x

x x

Variable #1

Varia

ble

#2 xx

xx

x

x x x xxx

x xx

Monte Carlo Quasi Monte Carlo (LHS, HSS)

Corners Boundary

Variable #1

Varia

ble

#2

x

x

x

x x

x

Boundary –Orthogonal Array

x x xx x x x

x xxx xxxx x xxxxx xx xx x

x x xxxx x x x xx xx x

x

x x x

x x xx x x

x x x x x

x

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Q Monte Carlo Controller (QMCC)

Graphical cockpit to control parallel Monte Carlo and Corners• More efficient dispatch based mechanism – reduces idle time• Supports LSF, Grid Engine, Local - ability to inspect and load balance

Page 66

Summary

GoldenGate enables you to:

• Use modulated signals for both design and verification

• Use “raw” EVM to quickly predict performance and find problem areas

• Run specification-compliant simulations for verification

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