using generic cell libraries to improve the automatic ... · method, operational amplifier, input...
TRANSCRIPT
Using generic cell libraries to improve the automaticsizing of operational amplifier with rail-to-rail input
and output
Nuno Miguel Rodrigues Machado
Thesis to obtain the Master of Science Degree in
Electrical and Computer Engineering
Supervisor(s): Prof. Nuno Cavaco Silva HortaProf. Jorge Manuel Correia Guilherme
Examination Committee
Chairperson: Prof. Goncalo Nunes Gomes TavaresSupervisor(s): Prof. Jorge Manuel Correia Guilherme
Member of the Committee(s): Prof. Pedro Mendonca dos Santos
November 2017
Acknowledgments
I would like to thank all the people who contributed in the work described in this thesis. I thank
my academic supervisors, Prof. Nuno Horta and Prof. Jorge Guilherme for their guidance during the
development and writing of this thesis. My MSc colleagues, Joao Bauto, Jonathan Calvillo e Jose
Cachaco , for the work and friendship during this last year. Additionally, I would like to thank, all the
team at the Integrated Circuits Group, for their help and companionship, which proved to be essential
for this thesis: Antonio Canelas, Nuno Lourenco, Ricardo Martins and Ricardo Povoa. Also, to my
colleagues and friends at Instituto Superior Tecnico that gave me the motivation in the last five years.
And finally to my family, especially to my sister, Dr. Ana Sofia Machado, for their unlimited support.
i
Abstract
The complexity grow in Systems-on-Chips (SoC) brings the necessity to automate their design
process in the analog world. This thesis presents a new tool to ease automate analog IC design and
design reuse. It was used an existent genetic algorithm optimization-based method (AIDA) with a new
structure layer. The new structure layer contains a generic cell library and a circuit class database to
facilitate the migration of different processes and topologies. To validate the topology independence in
the proposed solution, testbenches were built for a specific class of circuits - Operational Amplifier with
rail-to-rail input and output. The transfer knowledge through different topologies can be accomplished
by reusing an existent database of testbenches. In addition, technology migration was also validated
using two different technologies: XFAB 350 nm and ATMEL 150 nm SOI. Finally, this solution allows
the designer to develop easily a technology/topology independent system, which can be executed in
multiple designs, improving the automation process in the analog world.
Keywords
Analog integrated circuit design, Automatic sizing, Generic cell library, Genetic optimized-based
method, Operational amplifier, Input and output rail-to-rail.
iii
Resumo
O crescimento da complexidade nos sistemas-em-um-chip, obriga a necessidade de criar proces-
sos de desenvolvimento automatico no mundo analogico. Esta tese apresenta uma nova ferramente
que vem facilitar a automacao e reutilizacao de projectos analogicos. Foi utilizado um metodo de
optimizacao baseado em algoritmos geneticos (AIDA) com uma nova estrutura. Esta nova estrututa
contem uma biblioteca de celulas genericas e uma base de dados de classes de circuitos para fa-
cilitar a transferencia de diferentes tecnologias e topologias. De forma a validar a independencia da
topologia na solucao proposta, circuitos de teste foram desenvolvidos para uma classe de circuitos
especifica- Amplificador operacional com entrada e saıda rail-to-rail. A transferencia de conhecimento
atraves de diferentes topologias pode ser conseguida reutilizando uma base de dados de circuitos
de simulacao ja existente. Para alem disso, a migracao de tecnologia e tambem validada usando
duas tecnologias distintas: XFAB 350 nm e ATMEL 150 nm SOI. Finalmente, esta solucao permite ao
designer desenvolver facilmente um sistema independente da tecnologia e da topologia, que pode
ser executado em multiplos projectos, melhorando o processo de autmacao no mundo analogico.
Palavras Chave
Concepcao de circuitos integrados analogicos, Dimensionamento Automatico, Biblioteca de celulas
genericas, Metodo baseado em optimizacao gentica, Amplifcador Operacional, Entrada e saıda rail-
to-rail.
v
Contents
1 Introduction 1
1.1 Systems-on-chip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Current methodologies to optimize analog circuit design. . . . . . . . . . . . . . . 2
1.2 Amplifier Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Operational Amplifier Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Basic Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Thesis main goals and outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Overview of the existent topologies 9
2.1 Rail-to-Rail Operational Amplifier characterization . . . . . . . . . . . . . . . . . . . . . 9
2.1.1 Input Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1.A Range of input voltage, Vicm . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1.B Transconductance, gm, Vs Input Common-Mode Voltage, Vicm. . . . . . 12
2.1.1.C Input Stage with Constant Transconductance. . . . . . . . . . . . . . . 15
2.1.2 Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.3 Design of Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 Topology 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.2 Topology 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.3 Conclusion: Comparing the two best topologies . . . . . . . . . . . . . . . . . . . . . . . 23
3 Proposed Solution 25
3.1 Software Used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Cadence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.2 Mentor ELDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1.3 AIDA-C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 Solution architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.2.1 Configuration file to build the project . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.2 Script to build the project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3 Generic Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.3.1 Component Description Format, CDF . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Mapping File Creation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
vii
3.4.1 Mapping of process corners and Monte Carlo analysis . . . . . . . . . . . . . . . 37
3.4.2 Mapping file: at77k.lib & xh035.lib . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 Operational amplifier database 40
4.1 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.1 AC tb.cir.eldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.2 VCM tb.cir.eldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.1.3 AC CMRR tb.cir.eldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1.4 TRAN tb.cir.eldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1.5 OutSwing tb.cir.eldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1.6 ICMR tb.cir.eldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Netlists circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.1 YanLu circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.2 NimaShahpari circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2.3 CurrentFlow circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3 Configuration file default.design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5 Results 63
5.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.1.1 Selection of the best topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.1.A Configuration file: NimaShahpari . . . . . . . . . . . . . . . . . . . . . . 64
5.1.1.B Configuration file: Yanlu . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.1.2 Post-Optimization analysis and Conclusions . . . . . . . . . . . . . . . . . . . . . 67
6 Conclusions and Future Work 69
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Bibliography 73
Appendix A Current Flow Results A-1
viii
List of Figures
1.1 Analog circuit synthesis using a procedural generator-based method [1]. . . . . . . . . . 2
1.2 Analog circuit synthesis using an optimization-based method [1]. . . . . . . . . . . . . . 2
1.3 Generic incremental model of a Voltage Amplifier. . . . . . . . . . . . . . . . . . . . . . 4
1.4 Symbol of the Op-Amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Incremental model of the Op-Amp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.6 Inverting Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.7 Non-Inverting Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Generic input stage of operational amplifier, P-channel differential pair, adapted from [2]. 10
2.2 Generic input stage of operational amplifier, N-channel differential pair, adapted from [2]. 11
2.3 Generic complementary input stage of operational amplifier,[2]. . . . . . . . . . . . . . . 11
2.4 Transconductance Vs Input common mode of a N-channel differential pair [3]. . . . . . . 13
2.5 Transconductance Vs Input common-mode of a P-channel differential pair [3]. . . . . . . 14
2.6 Transconductance Vs Input common-mode of a complementary differential pair [3]. . . . 14
2.7 Output stage of a class-AB [4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8 Generic input stage of operational amplifier, N-channel differential pair, with DC-level
shifter [5]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.9 Overall scheme of the proposed design [5]. . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.10 Complete proposed rail-to-rail operational amplifier [5]. . . . . . . . . . . . . . . . . . . . 20
2.11 Input stage with dummy input differential pairs to gm-control [6]. . . . . . . . . . . . . . . 22
2.12 Design of constant-gm rail-to-rail Op Amp input stage [6]. . . . . . . . . . . . . . . . . . 22
3.1 General architecture of AIDA-C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2 Overview of the project architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Code Flow Diagram of the initial part of the Build Script. . . . . . . . . . . . . . . . . . . 30
3.4 Code Flow Diagram of the final part of the Build Script. . . . . . . . . . . . . . . . . . . . 32
3.5 Devices symbol views of the full Generic Library. . . . . . . . . . . . . . . . . . . . . . . 35
4.1 Structure of the database R2ROpAmp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2 Configuration for simulating the open-loop frequency and PSRR. . . . . . . . . . . . . . 42
4.3 Waveform simulation of the LSTB output, magnitude response in green and phase
response in blue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ix
4.4 Waveform simulation of PSRR magnitude response. . . . . . . . . . . . . . . . . . . . . 43
4.5 Waveform simulation of the VCM variation, transconductance of the differential pair in
blue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6 Configuration for simulation the CMRR. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.7 Waveform simulation of the CMRR magnitude response. . . . . . . . . . . . . . . . . . . 46
4.8 Configuration for simulate the Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.9 Waveform simulation of the Slew Rate, the input signal in blue and the output in green. . 47
4.10 Configuration for simulation the Output Swing Voltage. . . . . . . . . . . . . . . . . . . . 48
4.11 Waveform simulation of the Output-Voltage Swing. . . . . . . . . . . . . . . . . . . . . . 49
4.12 Configuration for simulation the Input Common-Mode voltage Range, ICMR. . . . . . . . 50
4.13 Configuration for simulation the Input Common-Mode voltage Range, ICMR. . . . . . . . 50
4.14 Waveform simulation of the Input Common Mode Range, ICMR. . . . . . . . . . . . . . 51
4.15 The first stage with control of the input transconductance from Yanlu circuit. . . . . . . . 52
4.16 The second stage with a class AB output stage from Yanlu circuit. . . . . . . . . . . . . 53
4.17 The first stage with control of the input transconductance from NimaShahpari circuit. . . 54
4.18 The second stage with a class AB output stage from NimaShahpari circuit. . . . . . . . 55
4.19 Current flow for a VCM = 0 [V]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.20 Current flow for a VCM = VDD/2 [V]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.21 Current flow for a VCM = VDD [V]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.22 The first stage with control of the input transconductance from CurrentFlow circuit. . . . 58
4.23 The second stage with control of the input transconductance from CurrentFlow current. 60
5.1 The results of objective optimization in tech at77k for all three topologies used. . . . . . 65
x
List of Tables
1.1 The list of basic amplifiers and their ideal terminal resistance. . . . . . . . . . . . . . . . 4
2.1 Comparison of the transconductance variation for various topologies. . . . . . . . . . . 16
2.2 Comparing the two best topologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 The list of Generic Cell Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 Definition of process corners models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3 Definition of process corners models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1 Association of which measure to the testbench file. . . . . . . . . . . . . . . . . . . . . 41
4.2 The list of devices and variables of Yanlu circuit. . . . . . . . . . . . . . . . . . . . . . . 52
4.3 The list of devices and variables of Yanlu circuit. . . . . . . . . . . . . . . . . . . . . . . 53
4.4 The list of devices and variables of NimaShahpari circuit. . . . . . . . . . . . . . . . . . 54
4.5 The list of devices and variables of NimaShahpari circuit. . . . . . . . . . . . . . . . . . 55
4.6 The list of devices and variables of CurrentFlow current. . . . . . . . . . . . . . . . . . . 59
4.7 The list of devices and variables of CurrentFlow circuit. . . . . . . . . . . . . . . . . . . 59
4.8 Default Corner Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.9 Default Values of the Constrains and Objectives. . . . . . . . . . . . . . . . . . . . . . . 62
5.1 Default variable ranges used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Values of the parameters for the circuit NimaShahpari with the tech at77k. . . . . . . . 66
5.3 Values of the parameters for the circuit NimaShahpari with the tech xh035. . . . . . . . 66
A.1 Values of the parameters for the circuit CurrentFLow with the two techs. . . . . . . . . . A-2
xi
Abbreviations
ASIC Application-specific IC
AIDA Analog Integrated Circuit Design Automation
CDF Component Description Format
CMOS Complementary Metal Oxide Semiconductor
CMRR Common-mode rejection ratio
EDA Electronic Design Automation
GBW Gain Bandwidth product
IC Integrated Circuit
ICMR Input common-mode range
IP Intellectual Property
Op-Amp Operational Amplifier
PDK Process Design Kit
PSRR Power-supply rejection ratio
SNR Signal-to-Noise Ratio
SoC Systems-on-Chip
SOI Silicon On Insulator
SPICE Simulation Program with Integrated Circuit Emphasis
xiii
1Introduction
The complexity grow in systems-on-chips (SoC), brings the necessity to automate their design pro-
cess. Tools to develop and automate the digital circuit design have been growing tremendously. How-
ever, analog circuit design has not grown in the same pace. The presents work uses an optimization-
based method with a new generic cell library to improve the analog circuit design process. In this
project it will be used as a class of circuit an operational amplifier (Op-Amp).
1.1 Systems-on-chip.
Nowadays, the need for high-advanced and adaptable equipments, forces the microelectronic
world to grown at exponential rate. Moving the markets for application-specific integrate circuits
(ASICs), which generates a higher level of integration complexity systems, also known as systems-
on-chip,[7].
A SoC’s generic structure is composed by 80% of digital design against 20% of analog, figure ??.
Despite the effort to replace analog with digital structures, some functions will always remain analog.
This raises a problem - design productivity gap. In design productivity gap more functionalities are
integrated on the circuit, increasing the complexity and reducing the productivity design rate [8]. The
reuse of intellectual property(IP), can improve this design productivity.
The concept, reuse IP, is well established in the digital world, using generic cell libraries in mem-
ories and CPUs to automate and simplify the reuse of each structure. On the other hand, the analog
world has a greater degree of freedom and different design rules. These prevents the creation of
generic cell libraries. However, several solutions have been developed to solve this problem.
1
1.1.1 Current methodologies to optimize analog circuit design.
The traditional way to design analog circuits requires significant amount of manual work done by
experts in the field. As a consequence, the quality and design are subject dependent, making this
process unreliable, tedious and not robust. In addition, the analog design constraints are specific
and restricted to each circuit. Therefore, the automation process of designing analog circuit is a
challenging.
Many approaches have already been developed and they basically can be divided into two ma-
jor methodologies: procedural generator-based method, (figure 1.1) or optimization-based method,
(figure 1.2) [1].
Figure 1.1: Analog circuit synthesis using a pro-cedural generator-based method [1].
Figure 1.2: Analog circuit synthesis using anoptimization-based method [1].
Procedural generator-based method consists in a ”bottom-up” sequential descriptions of analog
blocks with a simple dedicated structure. It’s dependent on a database knowledge created by experts
in the field [9] [1]. Several examples of procedural generator-based method are:
• The gPCDS is an interactive tool that generates conventional PCell for basic functions, giving to
the designer a familiar environment. These PCells are build by experts, facilitating the reuse of
knowledge across different projects [10];
• The technology abstracted layer is a generator programmer that uses a generic code of the
circuit, converting to an abstract representation. Technology-specific design rules can be apply
to the graph for a more robust circuit [11];
The low complexity and the predefined steps of the procedural generator-based method result in
a very high execution speed. It’s the optimal solution for a simple and restrict analog circuit design.
Although this method can be portable to different technologies, by the use of a generic cell library, it
is normally restricted to a specific software. In addition, the success is implicitly correlated with the
quality of the database knowledge [9] [1].
The optimization-based methods uses numerical algorithms to solve analog circuits design with a
2
higher degrees of freedom, while optimizing the performance of the circuit under the given specifica-
tion constraints [1][12][13]. Several examples of optimization-based methods are:
• Based Geometric Programming solutions, the optimization is proceeded using a list of design
equations to improve the results [12];
• Based Genetic Algorithm, simulate the natural process of nature. Selecting the best generation
until reach the final goals [13];
Using this type of approach the designer does not require an extensive database of knowledge.
When a group of constrains are defined the system will generate/calculate several solutions until reach
the desired goal. It allows the designer to extend and modify the system in a easy way [1][12][13].
When compared with the procedural generator-based method, the major advantages of the optimization-
based approaches are their high flexibility and extendibility. A disadvantage of it is the amount of com-
putation effort. In addition, there is a large deficit when it comes to the reuse IP concept. Applying
a generic cell libraries with a circuit class database could solve this problem. In this project it will be
used a genetic algorithm optimization-based method with a generic cell libraries to be applied as a
reuse IP concept.
The genetic algorithm is supported by the AIDA, a framework that implements an analog IC design
flow from circuit-level specification to a physical layout description. It focus on design optimization and
porting, using highly efficient searching methods combined with accurate circuit-level simulation. It
uses layout design rules and parasitic extraction engines [14]. A more detailed description will be
presented in chapter 3.
The concept of IP reuse will be validated through a specific class of circuits - the operational
amplifier with an input and output rail-to-rail. The idea is to create a system that can easily migrate to
different technologies and topologies.
Before presenting the proposed solution, it is important to understand the fundamental concepts
of an Op-Amp, as can be seen on the follow sub-chapters.
1.2 Amplifier Concepts
First of all, it is worth to review the fundamentals concepts of amplification and loading. An ampli-
fier can be modulated as a two-port device, an input port for external signals, and an output port that
generates a signal formulated by an equation output = gain x input.
Each amplifier is classify by associating the nature of the input and output signal. The input signal
can either be in voltage or in current, so the gain relation will give the type of amplifier. If the gain is
given by amperes per volt, the input signal is a voltage Vi and the output signal a current Io naming
the amplifier as ”transconductance”. For a gain performed by volts per ampere, the input signal is a
current Ii and the output signal a voltage Vo, giving the name of ”transresistance” to this amplifier.
The amperes per ampere gain, it will be used when the input and output signals are currents Ii and
3
Io, showing the ”current” amplifier. At last, the most common, the ”voltage” amplifier, which the input
and output signal are the voltages Vi and Vo, leading to a volts per volt gain.
Each amplifier can be modeled by the Thevenin or Norton equivalent, consisting of voltage or
current source and a series resistance. Using as example the ”voltage” amplifier, the input port is
modeled with just a resistance Ri, named the input resistance. To the output port it will be performed
by a voltage-control voltage source to signify the output dependence of Vo on Vi, plus a series resis-
tance Ro, named the output resistance. As can be seen on the figure 1.3.
Figure 1.3: Generic incremental model of a Voltage Amplifier.
The control-voltage source voltage is described as a gain, A, multiply by the input signal Vi. At
this point, only left derived an expression relating the Vo with Vs. Using the voltage divider formula at
the output an input, easily achieving the follow equation:
Vo =Rl
Ro +RlA
RdRs +Rd
(Vs) (1.1)
A drawback to this generic amplifier can be easily shown, the overall gain it will depend on the
particular input source and output load. The magnitude of Vo is less than the dependent-source
voltage due to the drop voltage across Ro. In similar way, the input port will drop some voltage on
the resistance Rs because Rd will draw current. An ideal amplifier can be reach if the loading effect
was eliminated. To achieve this condition, the voltage loss across Rs and Ro must be zero. So, the
voltage amplifier will require a Rd = ∞ and a Ro = 0. In practice, the resistance needed to ensure
the equations Rd � Rs and Ro � Rl. Similarity, the internal resistance of the each identify amplifier
can be resumed on the table 1.1.
Table 1.1: The list of basic amplifiers and their ideal terminal resistance.
Input Output Amplifier Type Gain Rd Ro
Vi Vo Voltage Amplifier V/V ∞ 0
Ii Io Current Amplifier A/A 0 ∞Vi Io Transconductance Amplifier A/V ∞ ∞Ii Vo Transresistance Amplifier V/A 0 0
4
1.3 Operational Amplifier Fundamentals
Op-Amp, is a voltage amplifier with the distinguish characteristic of having a very large gain. So
when a feedback loop is applied, a closed-loop transfer function independent gain is created. This
feedback loop can be performed using different components in order to obtain a variety of operations,
leading to it is name ” Operational Amplifier”.
The classic view of an Op-Amp consist in two inputs terminals, identified by the ”-” and ”+” symbols,
are designated inverting and non-inverting, to invert or preserve the phase of the input signal, and an
output terminal. In a macro way, his standardization symbol is given by the figure 1.4, some terminals
are ignored for a simple representation, like power supply.
Figure 1.4: Symbol of the Op-Amp. Figure 1.5: Incremental model of the Op-Amp.
Using as base the incremental model of the figure 1.3, it is possible to create an equivalent circuit to
the Op-Amp, as can be seen on the figure 1.5. An input port is performed by a differential resistance,
rd. Follow by the output port, build with a voltage-controlled voltage source and the output resistance
ro. If there is no loading on the output port the output voltage generated, vo, it will be the difference
between the input signals, vd, multiply by a gain A. So the output voltage can be modelled by the
equation 1.2.
vo = A(v+ − v−)
= A(vd)(1.2)
Where V+ define the voltage at the non-inverting input, and V− the inverting input terminal. The A
represents the voltage gain to the output terminal, Vo.
Following the ideal characteristics of the voltage amplifier, the Op-Amp must not draw current from
the input source and need to have a zero resistance to the output load. For an easy explanation, the
list bellow show the full attributes:
• Infinite open-loop gain; • Zero output impedance;
• Infinite bandwidth; • Infinite input impedance;
• Zero common mode gain;
1.3.1 Basic Configurations
As mentioned above, Op-Amp uses several passive components to perform a feedback circuit in
order to generate elementary gain stages. There are two basic configuration, the non-inverting and
5
inverting configuration.
The inverting configuration uses two resistor, R1 and R2, and an Op-Amp, as can be seen on
the figure 1.6. The resistor R2 creates the negative feedback, by linking the output terminal to the
inverting terminal. The resistor R1 is used to apply the input signal on inverting terminal.
Figure 1.6: Inverting Configuration.
Using the attributes of the Op-Amp, if the configuration presents a finite output voltage, the input
voltage need to be zero. Therefore, the inverting input remains at a virtual ground, V− = 0, and the
output voltage can be defined as,
V+ − V− =VoA
= 0 (1.3)
Applying the feedback configuration loop to the analysis, the gain can be obtained by the ratio of
the two resistor values R2 and R1, due to the closed-loop inverting configuration is added a minus
sign to the ratio. The final equation can be written as.
Vo = −R2
R1Vi (1.4)
In a similar way, the non-inverting configuration also consists in two resistor R2 and R1. The
closed-loop is the same of the inverting configuration, the resistor R2 creates a negative feedback,
linking the output to the inverting input terminal. The difference lies in the location of the input signal,
like the name implies, the non-inverting terminal will be used to apply the signal.
Figure 1.7: Non-Inverting Configuration.
An ideal Op-Amp has an infinite open-loop gain, so there is a virtual short circuit to his input
terminals, the difference between the non-inverting and the inverting terminals will be zero.
V+ − V− =VoA
= 0 for A =∞ (1.5)
6
So, the resistors R2 and R1 form a voltage divider across the output voltage, creating a feedback
with a gain of,
A =R2
R1+ 1 (1.6)
The output voltage can be written by the following equation.
Vo = (R2
R1+ 1)Vi (1.7)
1.4 Thesis main goals and outline
Digital circuit design have been growing tremendously due to automated process. However, ana-
log circuit has not grown in the same pace. Their design process is usually analytic and manual, there
is a general lack of standard cell libraries. Therefore, the aim of this project is to create a generic cell
libraries, using standard structures to facilitate the migration of different technologies. This thesis had
three main aims:
1. Create the generic cell library;
2. Apply the generic cell to a specific technology: X-FAB and Atmel;
3. Validate the generic cell library using an operational amplifier. In order to validate the
generic cell library in an operational amplifier the following steps were analysed:
• Selecting relevant topologies: the study of principal aspects of an operational amplifier
with rail-to-rail input and output stages, and of several solutions of different topologies. The
selection of designs that can be used to achieve the requirements of the project;
• Creating the schematic and defining related key performances: with the design that was
chosen, the next step is to use a generic cell library to create the schematics and to identify
the key elements for achieving the best performance in the circuit;
• Defining and creating the simulation benches: with the key performances identified, it is
important to create a simulation bench that can automatically give the result of these key
performances;
• Creating AIDA-C templates: the combination of the tool AIDA-C with the Mentor Graphics
Eldo, allows the optimization of the circuit. To achieve this functionality, it is necessary to
validate the schematics with the simulation benches, and to set the configuration files for
the key performances using typical and corners simulations;
• Providing a manual of each topology: with the results of every simulation it is provided a
manual which includes a functional description, key performances,and the optimized tran-
sistor parameters;
This document is composed by six chapters.
In first chapter is provided a general introduction with fundamental concepts about an Op-Amp
and overall objectives.
7
In second chapter is presented a general overview of the existent topologies, their problems and
solutions, as well as the selection of the most relevant topologies.
In third chapter is defined the flow of the solution proposed to the analog design reuse using the
EDA tools.
In fourth chapter is described the file structure needed to the solution proposed on the third
chapter, using as a case study the class of circuit, operational amplifier with input and output rail-to-
rail.
The fifth chapter is showed the final results of the selected topologies and validation of the pro-
posed solution. Finally, in sixth chapter is discussed and concluded the overall approach.
8
2Overview of the existent topologies
In this chapter will be presented the base structures of an Op-Amp with more focus on the input
and output rail-to-rail structures. The classic topology is hosted, citing its problems and showing the
necessity of the topology in study.
Finally, two topologies are presented and explained in order to be developed afterwards.
2.1 Rail-to-Rail Operational Amplifier characterization
Op-Amps are elements well established across analog circuit designs. They are used in many
applications such as filters and amplifiers, therefore, the existence of several topologies will fulfil the
requirements. Like the needed for a common-mode input range that reach a full rail to rail supply.
First of all, a conventional Op-Amp is divided into two stages, input and output. The input stage
is build using a differential pair that it will behave properly on a limited range of common-mode input
voltage. This limitation is solved using a more versatile input stage that works for a rail-to-rail common-
mode input range. A complementary differential amplifier is the most common method to reach the
full common-mode input range. A more detail explanation can be found in section 2.1.1. The output
stage is implemented with a typically class-AB output, as can be seen in section 2.1.2.
2.1.1 Input Stage
The realization of a rail-to-rail input stage typically employs double differential pairs, with N or P
channel transistors, extending the input voltage range in both direction. To adding the two differential
pairs, it is used a current adder to sum the effects of each input pair. This type of implementation
came with a main problem, the non-linearity of the input transconductance, gm, over the input voltage
swing. This affects many of the key operational amplifier characteristics, such as DC gain, GBW,
9
SNR, and a non-constant slew rate [6]. To understand this topology, it was divide the mains subjects
in the next sub chapters.
2.1.1.A Range of input voltage, Vicm
The input stage of a conventional operational amplifier consists of a single differential pair. This
can be either a P-channel, shown on Figure 2.1 or an N-channel input pair, shown on Figure 2.2.
Figure 2.1: Generic input stage of operational amplifier, P-channel differential pair, adapted from [2].
The common-mode input range of this P-channel differential pair, Vicm P, is given by the minimum
voltage needed at the gate of the input pair (M1,M2), to keep M3 or M4 in saturation, as well as the
maximum voltage possible at the input that will allow the input pair to remain in saturation.
VSS + VDSAT3 − |VTP1| ≤ Vicm P ≤ VDD − VDSAT5 − VDSAT1 − |VTP1| (2.1)
This range is given in Equation 2.1, where VDSAT is the minimum saturation voltage of a transistor,
VTP is the threshold voltage of a P-channel device.
In a similar approach, it can be calculated the common-mode input range of a N-channel differ-
ential pair, Vicm N. It is necessary to have a minimum voltage at the gate of the input pair (M6,M7), to
keep M8 in saturation, as well as the maximum voltage possible at the input that will allow the input
pair to remain in saturation.
The range is given by the Equation 2.2:
VSS + VDSAT8 + VDSAT6 + VTN6 ≤ Vicm N ≤ VDD − VDSAT9 + VTN6 (2.2)
Where VTN is the threshold voltage of a N-channel device.
Analysing the Vicm P and Vicm N ranges above, it can be seen that there is a strong relationship
with supply voltage. With the decrease of the supply voltage, there is a reduction in the input voltage
10
Figure 2.2: Generic input stage of operational amplifier, N-channel differential pair, adapted from [2].
range. For that reason, using a simple differential pair cannot perform the requirement of a rail-to-rail
common-mode input .
Using the P-channel and the N-channel differential pairs solves the problem of the rail-to-rail
common-mode input range. Where the P-channel differential pair is in saturation for low common-
mode input and N-channel differential pair is off. For high common-mode input, the P-channel dif-
ferential pair is off and the N-channel differential pair is in saturation. Therefore, the complementary
differential pair met the requirements to perform a rail-to-rail common-mode input range.
For better comprehension, in Figure 2.3 represents a simple complementary differential pair using
the two differential pair above.
Figure 2.3: Generic complementary input stage of operational amplifier,[2].
The Vicm range can be obtained by the equations 2.1 and 2.2.
Vicm = Vicm P + Vicm N (2.3)
11
VSS + VDSAT3 − VTP1 ≤ Vicm ≤ VDD − VDSAT9 + VTN6 (2.4)
As expected, the common-mode input has a range that starts below the VSS and finish above the
VDD.
With the complementary differential pairs forming the rail-to-rail input stage, it is necessary to add
the currents of each differential pair. This may be done using a folded cascode stage, as shown in the
Figure 2.3. The use of this stage gives another important feature, an high impedance and gain to the
output stage.
2.1.1.B Transconductance, gm, Vs Input Common-Mode Voltage, Vicm.
The necessity of using two complementary differential pairs solves the problem of a rail-to-rail
input common-mode range, but comes with a drawback of non-constant input transconductance, gmT.
This parameter is very important in the design of Op-Amp,[15]. Using the generic complementary
input stage of the Figure 2.3, it can be presented a simple explanation of this problem.
It is known that the transconductance of one differential pair can be expressed by the following
equation[16], in this case is for N-channel:
gmN =∂inout∂vicm
(2.5)
As the vicm has a range that starts in VSS and finishes in VDD, the current inout can be divide in
four regions,[16] [17] [18]. The first region occurs when the M6 and M7 are in cut-off, which puts the
M8 in linear region. Therefore, the transconductance of the N-channel differential pair, gmN, is equal
to zero because the currents through the transistors are all zero.
The second region is given by not assuming that the current only flows through the transistors, M8,
M6 and M7 when VGS > VT . There is an region below the threshold voltage that the transistor channel
follows current, sub-threshold. This region can be described with an exponential relation between the
gate-source voltage, VGS until reach the VGS = VT , according with the following equation:
iD ∝ eVGSnVT (2.6)
Consequently, the gmN also have an exponential relation with the gate-source voltage, in this case
with the Vicm.
In the third region, triode, even though the transistors M6 and M7 are in saturation, M8 is in the
linear region. This occurs because its VDS voltage has values between zero and VGS−VT . Therefore,
it is necessary to use the equations of current in the saturation, in M6 and M7, and triode, in M8, for the
relation of the current, inout with the input voltage, vicm [18]. To simplify the analysis, it is assumed:
βn = µnCOXWn
Lnβnb = 2βn1 = 2βn2 (2.7)
With these assumptions the current inout can be formulated using the following equations.
12
inout = βn1(VGS − VT )2
= βn1(vicm − VD nb − VT )2(2.8)
inout = βnb(VGS − VT −VDS
2)VDS
= βnb(VG nb − VSS − VT −VD nb − VSS
2)(VD nb − VSS)
(2.9)
Finally it is can be presented a general expression of inout as a function of vicm.
inout = βn1(Vicm − VG nb
2+
√2(−VT + (VG nb − (VSS)2 − (Vicm − VG nb)2
2)2 (2.10)
Applying the equation 2.5, the gmN is given by a square-root relation with the input voltage, vicm.
The last region appears when all three transistors, M7, M6 and M8, enter into the saturation region.
In other words, when the current tail could be expressed like the Equation 2.11. Assuming that the
transistors of the differential pair are operating in the saturation region in the strong inversion region,
the gmN is proportional to the square root of inout because the square-law model of the transistor is
valid [19].
inout =βnb2
(VGS − VT )2 (2.11)
The four regions can be schematized in the Figure 2.4.
Figure 2.4: Transconductance Vs Input common mode of a N-channel differential pair [3].
For the differential pair P- channel his transconductance can be calculated in a similar way. There
are four regions but in the opposite direction, saturation, triode, sub-threshold and cut-off.
With the transconductance of each differential pair defined is simple to know the total transconduc-
tance, gmT. It can be given by the sum of the transconductance of the N- and P-channel differential
pairs, gmN and gmP, respectively [15].
gmT = gmP + gmN (2.12)
Which can also be schematized in the Figure 2.5.
13
Figure 2.5: Transconductance Vs Input common-mode of a P-channel differential pair [3].
The combination of the two graphics, of Figure 2.4 and Figure 2.5 originates the total transcon-
ductance, Figure 2.6:
Figure 2.6: Transconductance Vs Input common-mode of a complementary differential pair [3].
Analysing the graphic of gmT, Figure 2.6, it can be identified that the transconductance varies by a
factor of two over the common mode input range, if the gmN is equal to gmP. This characteristic leads
to a several types of drawbacks like an undesired additional distortion, for example, if this input stage
is applied to an operational amplifier in a non-inverting feedback configuration the gain varies about
100% over the common-mode input range, which leads to distortion [20]. Another drawback is the
impossible realization of the optimal frequency compensation, as the gmT variation leads to the gain
variation that, in turn causes a perturbation in the unity gain bandwidth, wu.
wu =gmTCc
(2.13)
To keep a constant wu the Cc, compensation capacitor, needs to variate in the same way as the gmT
which is not possible [21].
There are several solutions to overcome these drawbacks of rail-to-rail input stages. In the next
section it will be present some of these solutions in different topologies.
14
2.1.1.C Input Stage with Constant Transconductance.
With the previous analysis, it is possible to define the total transconductance in function of the
input stage bias in strong inversion. Accordingly, the transconductance is given by
gmT =
õPCOX
WP
LPIP +
õNCOX
WN
LNIN (2.14)
It is possible to write in function of a voltage point of view
gmT = µPCOXWP
LP(VSG − VTP ) + µNCOX
WN
LN(VGS − VTN ) (2.15)
Consequently, these equations give us the idea to keep gmT constant. It can be identified by three
techniques, controlling the tail currents, IP and IN, changing the gate-source voltage, VSG and VGS, or
varying the W and L rations.
The tail current control consists of maintaining a constant gmT by keeping the sum of the square
roots of the tail current of each complementary input pair steady. First, it is need to consider that
µP (W/L)P equal to µN (W/L)N to have a single relation with the tail current
√IN +
√IP = 2
√Iref (2.16)
Exist several topologies to reach a tail current constant. These techniques are based on the idea
of increasing the tail current. When a single differential pair is active the tail current is equal to four
times the current of reference, Iref, giving rise to a gmT proportionality to 2√Iref . On the other hand, if
the two differential pairs are active it is necessary to have a tail current equal to Iref in each device to
originate a gmT proportionality to 2√Iref . This can be possible adding a non working pair that remove
three times Iref from the tail current of each working pair. The use of this technique has drawbacks as
for example, the mismatch of the two differential pairs, the process variations may change the nominal
value of the parameters µN and µP . Other example, it is the increasing use of the current in each tail
current, which will consume more power [20].
Voltage Control is another technique to keep a constant gmT for all input range of Vicm. Assuming,
the input transistors are biased in strong inversion in order to control the gmT by controlling the gate-
source voltages of each differential pair. Using the equation 2.15, it can be identified that the sum of
VGS with VSG need to be constant. It may be accomplished by connecting a voltage source between
the common sources of the N and P channel differential pair forcing the both pairs working for all Vicm
range[20].
W over L based gm Control is a technique that uses the aspect ratio of the complementary
differential pair to achieve a constant gmT. The general method for implementing this technique is by
using a second complementary pair in parallel with the principal. The idea is in the middle region
only the principal complementary differential pair works and in the others regions, the secondary
and principal complementary differential pairs work at the same time, which causes the gmT to be
constant. In others words, when only the N-channel differential pair is working the second N-channel
differential pair is working to duplicate the transconductance, the same for the P-channel differential
15
pair. For the middle region only one complementary differential pair is working and it is well know
that the transconductance is double of one differential pair [20]. Therefore, it can possible to obtain a
constant gmT for all range of Vicm. It is important to refer that in the transition of the operation regions
may occur a non-smooth current transition leading to a relatively large variations in gmT [20].
There is one more alternative method to originate a constant gmT. All the previous solutions use
a complementary differential pair to make a rail-to-rail input stage, the idea of this solution is to use
only one differential pair. This technique is known as DC level shift, the overall idea is to realize a DC
shift in Vicm with the goal of putting the differential pair always in the saturation region. One method
to perform this solution is using a kind of multiplexer in the input of each transistors of the differential
pair. The multiplexer select whether the Vicm or the Vicm plus a DC shift, form better compression is
explained in the subsection 2.2.1.
The Table 2.1 summarizes different topologies that use the methods previously mentioned with
the purposed of identifying and choosing the lowest variations of transconductance, in order to select
the best topologies. Selecting two topologies, [6] e [5].
Table 2.1: Comparison of the transconductance variation for various topologies.
Methods used Topology gmT variation
The tail current control
[22] 15%
[23] 15%
[24] 15%
[15] 10%
[25] 5%
[6] 2%
[26] 8%Voltage control[27] 10%
W over L based gm control [28] 20%DC level shift [5] 0.9%
2.1.2 Output Stage
The need of adding an output stage to an operational amplifier is to transmit the signal to the load
with enough power to reach a low level of signal distortion. In order to achieve a better efficiency, the
output voltage need to have a wide range, i.e., a rail-to-rail output. Therefore, a typical output stage
of an operational amplifier can be accomplished with a class-AB.
A class-AB biasing, as the name implies, it is the combination of a class-A and a class-B biasing,
in order to obtain a commitment between the distortion and the dissipation on the quiescent stage.
Where, the class-B biasing delivers a large output current with an almost zero current in the quiescent
stage. However, this implies a distortion on the output signal because of the cross-over distortion
[20]. This problem can be solved using a class-A biasing, but it has the drawback of the current in the
quiescent stage be equal to the output current, leading to a lower efficiency [20]. The solution is to
16
obtain a compromise between the two classes.
Therefore, it is presented a class-AB for the output stage, which demonstrates the mentioned
compromises.
Figure 2.7: Output stage of a class-AB [4].
The topology uses two complementary transistors (MO1,MO2) connected in common-source con-
figuration. As well as a current biasing with the aim of decreasing power consumption. This can be
controlled by a correct tuning of the current that flow through MO4. The existence of the capacitor CF
and the resistance RF are intended to apply a conventional Miller technique for frequency compensa-
tion.
2.1.3 Design of Op-Amp
An Op-Amp’s design can be divided into two activities independent of each another. First, the
selection of his basic structure, normally represented by a diagram describing the interconnection of
all the transistors. During the project the structure can be modified to satisfy the requirements. At
the end, with the structure selected, the designer chose the all polarization sources and begin the
transistors sizing.
The work presented focuses on the last activity, performed by an automated circuit optimizer,
like the AIDA-C. To achieve a properly scaled devices, the central task is setting all the AC and DC
requirements and boundaries conditions to reach the best sizing and efficient design.
The next chapters describe how this can be done. But firstly, it is essential to identify the must
important requirements needed to design class of circuit in study. The following list describes this
requirements.
17
• Gain[Adc]; • Power-Supply Rejection Ration[PSRR];
• Gain Bandwidth[GBW ]; • Output-voltage Swing[VHO,VLO];
• Phase Margin[Φm]; • Offset Voltage[VOS ];
• Common-Mode Rejection Ratio[CMRR]; • Power dissipation[Pdis];
• Slew Rate[SR+,SR−]; • Transconductance Variation[∆gm];
• Input Common-Mode Range[ICMR];
All the circuits needed to perform this requirements are describe on the chapter 4
2.2 Related Work
In this section, it will be presented and described the solutions previously chosen.
2.2.1 Topology 1
The conventional topologies use two complementary differential pair that leads to a problem of
sensitivity to mismatches. To eliminate this problem, it is proposed the present topology [5] which,
only use one differential pair.
The circuit use a N-channel input differential pair. As mentioned in the previous chapter 2.1.1,
the use of a single differential pair cannot keep a constant transconductance for all the common-
mode input range. Therefore, it is necessary to ensure a common-mode input high enough to put
the differential pair in saturation. The solution is to add a DC voltage, VS, with the gate of the input
transistors, the DC-level shifter has a function to ensure that the input transistor always remain in the
saturation, as can be shown in figure 2.8.
Figure 2.8: Generic input stage of operational amplifier, N-channel differential pair, with DC-level shifter [5].
This simple solution entail a problem, it does not work for a high value of Vicm, as seen before in
the equation 2.2 there are an upper limit, VDD - VDSAT + VTN. If this threshold is exceeded this puts the
18
input transistors in the triode region. To overcome this problem, a multiplexer is added to each input
transistor switching back the initial Vicm when the shifting voltage, VS, is not necessary. This transition
takes place when Vicm higher then VDSAT M1 + VTN 1 +VDSAT In, therefore the multiplexer can be define
by the following equation, in which the Vi correspond to his output.
Vi =
{Vicm + VS Vicm < VDSAT M1 + VTN M1 + VDSAT In
Vicm Vicm > VDSAT M1 + VTN M1 + VDSAT In(2.17)
With this in mine it can be present the overall scheme of the proposed design.
Figure 2.9: Overall scheme of the proposed design [5].
The utilization of these non ideal components, DC-level shifter and a multiplexer, shows that the
gain associated to each element needs to be accounted for. Amux represent the gain of the multiplexer
and AVs the gain of the DC-level shifter. Therefore, the total of transconductance, gmT can be given
as:
gmT =
{AmuxAV sgmN Vicm < VDSAT M1 + VTN M1 + VDSAT In
AmuxgmN Vicm > VDSAT M1 + VTN M1 + VDSAT In(2.18)
Having these equations in mind, it is important to define the multiplexers’ control circuits and to
know how to calculated the value of VS. First, the multiplexers’ control circuits have one input signal,
Vicm, and one output signal, Vsel. This control circuit uses a simple inverter that acts as a comparator.
The switching voltage, Vsw, of the inverter is compared with the Vicm [29]. Knowing that the Vsw depend
on the PMOS and NMOS devices sizing used in it. The Vsw is given by [5].
Vsw =
√βN
βPVTN + (VDD − |VTP |)
1 +√
βN
βP
(2.19)
In conclusion, when Vicm is smaller then Vsw it originates a Vsel equal to one, or VDD. Which
select the input that has been raised by the DC-level shifter. For the opposite situation when the Vicm
19
is higher then Vsw the Vsel is set to zero, and the input signal directly pass to the gate of the input
transistors without any shift.
Secondly, VS value is created by the gate source voltage of the transistor Mdc2. The amount of
shift is determined by adjusting the current, Idc, of the cascode current source created by the Mdc0
and Mdc1, and Mdc2 sizing. For VS we will have.
VS =
√2Idcβdc2
+ VTdc2 (2.20)
With these in mind, the figure 2.10 present the complete proposed rail-to-rail operational amplifier
of this topology.
Figure 2.10: Complete proposed rail-to-rail operational amplifier [5].
2.2.2 Topology 2
Another solution to keep a constant transconductance, gm, is present in this section [6]. This
solution suggests a dynamic control of the tail current with respect to the input differential pairs by
using a dummy input differential pairs.
The circuit uses two complementary input differential pairs and a control of the tail current. This
last topic distinguish them from the others topologies, [6]. For an easy explanation it is illustrated in
Figure 2.11. From the equation Equation 2.14 the gm of input transistors is given by:
20
gm =√ItailK (2.21)
It is important to refer that the K is given by:
K = µnCOXWn
Ln= µpCOX
Wp
Lp(2.22)
It is known that there are three regions of operation where the gm needs to be kept constant. In
other words, the gmN needs to be equal to gmP and equal to the sum of gmN with gmP. The proposed
solution consists of the use of a dummy input differential pair N-channel type connected to the tail
current transistor of input differential pair P-channel type, M6. In the same way, a dummy input
differential pair P-channel type is connected to the tail current transistor of input differential pair N-
channel type, M5.
A tail current, Itail, is equal to four times the current of reference, Iref :
Itail = 4Iref (2.23)
With this in mind, when there is only one active input pair, the dummy input differential pairs do
not have effect, which corresponding to have a gm:
gm = gmN = gmP =√
4IrefK = 2√IrefK (2.24)
When both differential pairs are in operation, the dummy input pairs take away three times of the
Iref from the Itail, which originates a gm:
gm = gmN + gmP =√IrefK +
√IrefK = 2
√IrefK (2.25)
The current IC has a function of keeping M11 and M12 in the triode region when the dummy input
differential pairs are turn off, which decreases the gm variation. This behaviour occurs when the input
differential pairs are turned off, putting the transistor M5 and M6 in triode region [6]. It is important to
have a relation of IC with the Iref. Keeping this in mind, it is possible to formulate the following equation:
IC3Iref + IC
=3Iref4Iref
IC = 9Iref
(2.26)
Finally, a conventional folded cascode is used to sum all the currents from the two complementary
differential pairs. A complete solution of this topology is shown on figure 2.12.
21
Figure 2.11: Input stage with dummy input differential pairs to gm-control [6].
Figure 2.12: Design of constant-gm rail-to-rail Op Amp input stage [6].
22
2.3 Conclusion: Comparing the two best topologies
In this chapter it was presented the classic topology for the input stage of an Op-Amp, their prob-
lems and solutions. The conventional classic topology is built by a single differential pair. Its properly
behaviour is limited to a specific common-mode input-voltage range. In order to face this limitation
several topologies were analysed using the following methods: the tail current control, voltage control,
W over L based gm control and DC level shift. Based on the gmT variation variable it was selected the
two best topologies. One based on the tail current control method and the other based on DC level
shift method. The following table present all results from the two best topologies, as well as the used
technology, table 2.2 .
Table 2.2: Comparing the two best topologies.
Topology Process Supply V. gmT variation DC gain Bandwidth P. margin Year
Topology 1 [5] 0.18µm 1.8V 0.9% 76dB 69MHz 51◦ 2015
Topology 2 [6] 0.18µm 1.8V 2% 61dB 25MHz 78◦ 2008
23
24
3Proposed Solution
The variety and non-uniformity of CMOS process technologies hamper the reuse of analog de-
signs projects.
The solution proposed uses several software tools with a particular emphasis on the AIDA-C opti-
mizer to expand the reuse of analog designs. Presenting the developed structures in order to under-
stand the design-flow. An example will be presented for the circuit class in study, Operational Amplifier
with Input and Output Rail-to-Rail stages.
3.1 Software Used
The Electronic Design Automation(EDA) represent the category of software tools used on the
design of integrated circuits. Therefore, choosing the correct tool is extremely crucial to the project’s
success. The first step will be define the main tasks on the EDA.
The work conducted in this thesis focuses in two areas of the four main from EDA, Design and
Simulation leaving Manufacturing preparation and Analysis and Verification for a future task.
Design and Simulation reflect into a topology selection and circuit sizing by a designer [30].
The first step to understand the proposed solution will be to know the tools chosen.
3.1.1 Cadence
A designer engineer needs to capture and record the flow of a circuit, a graphical schematics can
be use to achieved this necessity, creating an overview of the complete circuit/topology and how all
the components are link [31].
The chosen software is Virtuoso Schematic Composer fromm Cadence. It was used to imple-
ment the circuit design of each typology by using the generic design kit of CMOS components, that
will be presented in this chapter.
25
3.1.2 Mentor ELDO
The next step is a simulation program that perform all the needed analyses. Like SPICE, the most
popular analog simulator in the design engineer community. It is an open source program use on
integrated circuit to verify the integrity and predict the behaviour of the designs. There are several
tools based on this type of simulation program, which were developed by different corporations. The
tool chosen for this thesis is the Mentor Eldo from Mentor Graphics.
Eldo offers a unique partitioning scheme, allowing the use of different algorithms on differing parts
of the design. The user has a flexible control of the simulation accuracy using a wide range of device
model libraries and a high accuracy yield, combining the high speed and performance [32].
In order to run an Eldo simulation, it is necessary to provide the following input file, Complete
Netlist Simulation File (.cir), file that contains the circuit netlist, testbenchs and simulation com-
mands. This file can be divided in several others to achieve a better organization.
The principal output files that Eldo generates can be seen on the list below:
• <file>.chi, file that includes the results and errors.
• <file>.aex, file that contains the extraction information. It is created when .OPTION AEX is used
in conjunction with a .EXTRACT command.
3.1.3 AIDA-C
The last main task is performed by a circuit optimizer. The tool chosen is AIDA-C.
AIDA-C is a tool that target sizing of the analog devices using state-of-the-art multi-objective multi-
constraint optimization techniques, addressing robust design requirements in a worst case approach.
In order to reach a accurate circuit’s performance, this tool use several industrial grade circuit simula-
tors, enabling the designer to choose his own simulator [33]. As already indicated above, the Mentor
Eldo simulator was selected for this thesis. The following figure shows the AIDA-C architecture.
Figure 3.1: General architecture of AIDA-C .
26
Since this is a central tool of the work, it is important to understand all the specs involved on
AIDA-C.
Before AIDA-C can be executed, it should be developed a description file in XML language. The
file is structured by a header, identifying the XML version and document type definition, and contains
one Design element, identifying a series of elements described in the following code:
1 <?xml version="1.0"encoding="UTF -8"?>
2 <!DOCTYPE Design SYSTEM "design -1.1. dtd">
3 <Design name="..."author="...">
4 <Description >...</Description >
5 <Circuit schematicImage="... " technologyNode="... ">
6 <Variable name="..." min="..." step="..." max="..."/>
7 </Circuit >
8 <TestbenchSetup >
9 <TestCase name="..."/>
10 <NominalTb netlist="..." simArgs="...">
11 <Measure name="..." description="..." units="..."/>
12 </NominalTb >
13 <WorstCaseTb netlist="..." simArgs="...">
14 <ImportFromtb="..."/>
15 </WorstCaseTb >
16 </TestbenchSetup >
17 <Objective op="..." meas="..."/>
18 <PerformanceSet name="..." applyTo="...">
19 <Constraint meas="..." op="..." value="..."/>
20 </PerformanceSet >
21 <Optimizer TypG =... TypP =... CnrG =... CnrP =.../>
22 </Design >
The XML file is structured into the six groups of elements, description, circuit, test benches, objec-
tives, performance and parameters of the optimizer:
• Organization is crucial to a project, for that reason the element Description gives the user
space to describe his project;
• For a project, it is mandatory to refer the technology, technologyNode option on the element
Circuit, and identify the ranges of each variables, Variable
• The next step is to define all the testbenches for the circuit, TestbenchSetup. This element
can perform nominal or worst case analysis. The nominal is identified by NominalTb and the
measures needed, Measure. In order to run the worse case is required to identify each case
using TestCase and finally call the function WorstCaseTb with the correct testbench.
• Define an objective is a fundamental spec when using an automate optimizer, it is important to
define a goal to reach better results. For that reason there is the element Objective.
• Each project needs to have minimal specs to a correct function. The element PerformanceSet
defines a minimal specs applying to each case test. This feature is call constraint, the designer
can indicate the measure with his restriction function value, greater or smaller than.
• AIDA-C is a circuit optimization which uses a genetic algorithm. It is mandatory to identify the
number of generations and population size using the element Optimizer
27
3.2 Solution architecture
The solution developed is structured into three central blocks described below.
• CircuitClass, database of a topology independent testbenches with the aim of extracting mea-
sures to characterize a specific circuit class;
• GenericCellLibrary, database of generic symbols which can allow the creation of technology
independent circuit netlists, due to their ability of ported into a specific technology;
• Building Script + Configuration file, files that join the previous databases, CircuitClass and
GenericCellLibrary, into a project folder for AIDA-C, in order to optimize the circuit using all the
input given by the configuration file;
For a better understanding of the solution architecture, a overview of the tool with the scheme depicted
is presented in the figure 3.2.
Figure 3.2: Overview of the project architecture.
Also, the solution architecture should help guide us through the relevant procedures to achieve the
final project.
So, the project starts with two important blocks, created by the designer: Configuration file and
the circuit netlist.
The files that make up the topology choose, correspond to the circuit netlist. The schematic need
to be outlined using the devices in the generic cell library, present on the next chapter. This can be
28
done using Cadence Virtuoso Schematic Editor.
The other important block is the configuration file, the designer can choose the technology, the
topology and dependent options. The following sub-chapter represents all the information about the
current file.
With these two blocks created, the building script can be run. The output generates an AIDA-C
complete project, located in a folder with the same name of the configuration file, containing the files:
• Testing files, which have the technology independent testbenches with the topology dependent
measure files.
• Directory files, which have all the directories need to choose the exact mapping file technology,
specified in the configuration file.
• AIDA-C configuration file is generated to the project’s demands by the designer, obtaining the
file design.xml (it can be edit form default values, like, constraint, objectives, variables ranges,
corners, etc).
At this point, the AIDA-C optimizer can be executed in order to reach the performance that the
project’s demand. It is important to mention that even if the first topology used can reach the project’s
demand, a new topology can be easily tested, fulfilling one of the objectives of this work.
3.2.1 Configuration file to build the project
In order to facilitate and make this system more user-friendly a configuration file was created. In
this file the designer only needs to specify four main parameters. Then, the configuration file has the
fundamental steps to create the final project, by guiding the building script.
The structure of this file was define through the analysis of a project. The first step is the selection
of a TECHONOLOGY, followed by the characterisation of the circuit class, CLASS, making reference to
the path of the circuir netlist, CIRCUIT. At the end, restrictions can be added to reach all the designer
specifications, MEASURES.
The configuration file uses the .config filename extension to be identify by the script.1 TECHNOLOGY: "Tech name"
2 CLASS: "Circuit class"
3 CIRCUIT: "Path to netlist"
4 MEASURES: "Transistor region measures"
The list below show each parameter with more detailed:
• TECHNOLOGY, the target technology can be choose by this parameter. To operate properly, it is
mandatory to create a mapping file of each technology, locate on the Generic Cell Library, and
register all this information on the config file techs in order to check their availability by the script.
It is important to refer that the path for the Generic Cell Library directory must be specified in
config/options/database paths.
• CLASS, the circuit class is select by the parameter in study. To operate properly, it is mandatory to
create a measures.config and all the test benches to perform all the analysis. The files created
29
are organized in a folder with the name of the circuit class, locate on the CircuitClass, and
register all the information on the config file classes. As well, it is important to refer that the
path for the CircuitClass directory must be specified in config/options/database paths.
• CIRCUIT, path to the netlist generate by the designer using the generic devices.
• MEASURES, parameter that allows the designer to specify the measures of each mosfet device. It
is possible to have different options, +SAT and +TRI, to set what device it will be in the saturation
and triode region, with a given overdrive and saturation margin.The option +GMPAIR give the
value of the input stage transconductance.
3.2.2 Script to build the project
A fast creation of AIDA-C templates create a requirement to generate all the setup files automati-
cally. The Building Script will be the solution.
To build the script was used the programming language python. Python brings several advantages,
it is an interpreted high-level language and interpreters are available for Windows, Mac OS X, and
Unix. Thus the same code can be executed on these different platforms with no changes to the code.
It hosts thousands of third-party modules, helping to overcame all challenges. And it is open-source.
Figure 3.3: Code Flow Diagram of the initial part of the Build Script.
The script is divided into two stages, it starts with the checking of all the input information and
30
then pass to the creation of all the specific project files. In order to understand the script flow, it is
presented an explanation of each stage with a code flow diagram.
The first stage of the script represents a verification of an input configuration file and all its param-
eters. An essential step to reach the success of the final setup. As can be seen in the flow diagram
3.3, the verification process starts with an Argument Validation by reading the configuration file.
The configuration file is defined by several parameters needed to be validate. The script executes
a sequential verification:
1. Technology Validation, the script will check if the chosen technology is located on the file
techs;
367 techs = readfile ("./ options/techs")
368 techs = formatText(techs)
369 techs = map(lambda tech: tech.strip(), techs)
370 readDirectory ()
371
372 if tech in techs:
373 pass
374 else:
375 print "Error: Unknown technology\n Available technologies :\n\t"
376 print techs
377 sys.exit()
2. Directory Validation, the script will check if the designer set a directory on the file database path
to the class of circuit and the generic cell library .
379 if os.path.isfile(netlist) != 1:
380 print "Error: Cannot find netlist"
381 sys.exit()
382 else:
383 netlist_lines = readfile(netlist)
3. Class of circuit Validation, the script will check if the designer specify an existing class on the
circuit class database, the list of each class is located on the file classes.
385 classes = readfile ("./ options/classes ")
386 classes = formatText(classes)
387 classes = map(lambda clas: clas.strip(), classes)
388
389 if circlass in classes:
390 pass
391 else:
392 print "Error: Unknown circuit class\n Available classes :\n\t"
393 print classes
394 sys.exit()
Passing by these three validations the script will create the directory tree of folders and generic
circuit class files needed to AIDA-C.
31
Figure 3.4: Code Flow Diagram of the final part of the Build Script.
The second stage represents the Creation Files for the project.
The flow diagram 3.4 shows a sequential creation of the files needed to the project.
1. Technology File creation, knowing which technology will be use, the script choose a tech
libraries accordingly. Two files are create a typical and worst case analyses and other file for
Monte Carlo analysis, techs.inc and techs MC.inc.
586 def createtech ():
587 fout = open(directory + "/" + tech + "/tech.inc", "w")
588 fout2 = open(directory + "/" + tech + "/ tech_MC.inc", "w")
589
590 fout.write ("""
591 .LIB '%s' devices
592 .LIB key=proc '%s' typ
593 """ % (source_library , source_library))
594
595 fout2.write ("""
596 .LIB '%s' devices
597 .LIB key=proc '%s' mc
598 """ % (source_library , source_library))
599
2. Device path search, device path is mandatory in order to create the next files. A search algo-
rithm was create to read and formulate the device path from the .cir files of the project. This
algorithm uses a base file path, devices paths. The need of the file comes from the path variety
of each technology.
32
618 def readdevices ():
619
620 f = open ( './options/devices_paths ' , 'r')621 fin=formatText(f.readlines ())
622 paths = [ line.split() for line in fin ]
623 f.close()
624 for j in range(len(paths)):
625 devices.append(paths[j][0])
3. Measures File creation, the script perform all measures functions defined on the configuration
file. At the moment the script only perform three types of measures, mosfet saturation, mosfet
triode and input transconductance, +SAT, +TRI and +GMPAIR.
618 def createmeasuresinc ():
619 fout = open(directory + "/" + tech + "/ measures.inc", "w")
620 f = open ( './options/devices_paths ' , 'r')621 ...
622 for line in measures:
623 if '+SAT:' in line:
624 ...
625 if ('VOV=' in line) and ('DELTA=' in line):
626 vov_value = line[line.index('VOV=')+4: line.index('DELTA=')]627 delta_value = line[line.index('DELTA=')+6:]628 else:
629 print "Error: On Config File measure +SAT , VOV or DELTA not defined .\n\t"
630 sys.exit()
631
632 measure_vov(fout ,i, vov_value)
633 measure_delta(fout ,i, delta_value)
634
635 if '+GMPAIR:' in line:
636 foutvcm = open(directory + "/" + tech + "/ measures_VCM.inc", "w")
637 ...
638 foutvcm.write('.DEFWAVE GMPAIR =(GM(Xuut.'+ AuxName [0] +') + GM(Xuut.'+AuxName [1] +'))\n')
639 foutvcm.close ()
640
641 if '+TRI:' in line:
642 ...
643 if ('VOV=' in line) and ('DELTA=' in line):
644 vov_value = line[line.index('VOV=')+4: line.index('DELTA=')]645 delta_value = line[line.index('DELTA=')+6:]646 else:
647 print "Error: On Config File measure +TRI , VOV or DELTA not defined .\n\t"
648 sys.exit()
649
650 measure_vov(fout ,i, vov_value)
651 measure_delta(fout ,i, '-'+delta_value)
4. Corner File creation, a corner.inc file is create using a pre-create file corner .inc with the
technology specification defined on the configuration file. AIDA-C Setup File creation, the script
uses a pre-structure file, default.design and the project configuration file information to pre-
form the final setup, design.xml.
604 def correctcorner ():
605 f = open(directory + "/" + tech + "/ corner_.inc", "r")
606 f2 = open(directory + "/" + tech + "/ corner.inc", "w")
607
608 for line in f:
609 line = line.replace ("tech", library_directory + "Generic_Cell_Library /"+ tech)
610 f2.write(line)
At the end, a directory tree of all the files needed to run an AIDA-C project was created. The direc-
tory tree is composted with a design.xml, circuit netlist, testbenchs, technology files and measures
33
files. For better comprehension, it is presented in section 3.3 how the technology files are created, as
well as the circuit class files, presented in section 4.
3.3 Generic Cell Library
In order to meet the objective proposed, a small group of generic devices are created. In this
section, it is described the detailed list of devices that can be used by different software, CADENCE,
AIDA-C and Mentor ELDO.
The aim was the establishment of a platform to facilitate the technology transferability of the same
circuit/topology. The solution consists in having a generic library to map the technology chosen for all
the devices.
The generic library had a collection of 10 devices, mosfet transistor type N and P, resistors, ca-
pacitors and one bipolar transistor. It is important to refer that not all devices have a match for the
technologies in study, as can be seen in table 3.1.
Table 3.1: The list of Generic Cell Library.
Generic Name Description Parameters Port order AT77K XH035
nmos1v8 1.8V NMOS Transistor W,L,Mul Drain, Gate, Source, Bulk nmos N/Anmos3v3 elt ELT 3.3V NMOS Transistor W,L,Mul Drain, Gate, Source, Bulk nfetox3 ring nmos elt
pmos1v8 1.8V PMOS Transistor W,L,Mul Drain, Gate, Source, Bulk pmos N/Apmos3v3 ELT 3.3V PMOS Transistor W,L,Mul Drain, Gate, Source, Bulk pfetox3 pmos
rpoly Poly resistor W,L,Mul Plus, Minus, Sub rplow rp1
rpolyhr Poly resistor W,L,Mul Plus, Minus, Sub rphigh rpp1
rpolyxr Poly resistor W,L,Mul Plus, Minus, Sub N/A rhp1
mimcap MIM capacitor W,L,Mul Plus, Minus, Sub cmim34 cmm
dmimcap Double MIM capacitor W,L,Mul Plus, Minus, Sub N/A cdmm
pnp vertical Vertical PNP transistor Mul Collector, Base, Emitter pnp vert qp4
3.3.1 Component Description Format, CDF
For easy utilization, all the devices are designed in CADENCE environment.
In order to use the CADENCE environment, each device had to be represent by a complete el-
ement cell. Which can be accomplished through the Component Description Format, CDF. A CA-
DENCE option that describes the parameters and the attributes of individual components and their
libraries, letting the creation and description of own components, [34].
To create a cell element using CDF, it is important to chose what type of application intend to be
used. The following list presents all the information which was selected on CDF.
• Application:
34
– Design Entry;
– Simulation;
• Requirements views:
– Desing Entry: Symbol with G, S, B, and D pins for the gate, source, bulk and drain;
– Simulation: Type of Simulator(Eldo);
• Requirements parameters:
– Simulation: Width, Length and Multiplicity (W,L,M);
A library was created with the name of Generic lib, where all the cell elements are presented.
Each cell element had two require views for the application, a symbol and an EldoD. Now, it is impor-
tant to configure the right CDF parameters, using the edit CDF form.
With all this configuration done, it is possible to use the generic library elements to create a
schematic, all the devices are showed in figure 3.5. For the simulation process, it is important to
pick the correct mapping file, allowing the schematic run in both technologies.
Figure 3.5: Devices symbol views of the full Generic Library.
3.4 Mapping File Creation
First, it is important to understand what level the project it will be preformed. As mentioned before,
the idea of the solution was to reach the best performance in SPICE level.
35
The SPICE level consists of a netlist which describes the various circuit devices and their connec-
tions, a set of models for the circuit devices and a specification of the type of analysis to be performed
for a given circuit. Then transform all the circuit into equations to be solved using the follow numerical
techniques [35]:
• Node Admittance Matrix, using the Kirchoff voltage and current laws and branch equations;
• Newton Raphson techniques, to linearize a non-linear equations;
• Integration, a transient simulation typically involves solving non-linear differential equations that
can be solved using fixed time points in the interval of interest;
In order to chose a technology, the designer select which models provided by a manufacturer,
which will be refer to each circuit device to reach a more accurate simulation. Due to the large variety
of manufactures, each model had his own cell view, being necessary to rebuild every time the circuit
when the designer change the technology.
The solution presented resolve this problem, as stated before, a generic cell library has been
created for standardise the listed devices. Now the second stage is to map this cell views with the
models of each manufacture.
The mapping file solution needed to be done one time only for each manufacturer technology
using the following method. First each generic device is defined as a subcircuit, using the .SUBCKT
command, this feature consists on represent a circuit in a fashion similar way to devices models, see
the next general example:
1 .SUBCKT SubName Connection1 <Connection2 Connection3 ...>
2 *Technology models*
3 .ENDS
4
It is presented an example of the headers of the subcircuit of the following generic devices,
nmos3v3 elt, pmos3v3 and rpoly:
1 .SUBCKT nmos3v3_elt drain gate source bulk
2 *Model Tech*
3 .ENDS
4 .SUBCKT pmos3v3 drain gate source bulk
5 *Model Tech*
6 .ENDS
7 .SUBCKT rpoly plus minus sub
8 *Model Tech*
9 .ENDS
10
The technologies of different manufactures, ATMEL and X-Fab, have been used to verify the solution
presented.
Before presenting the final structure of the mapping file for each technology, it is crucial to under-
stand the process corners and Monte Carlo Analysis and how to related with different technologies.
36
3.4.1 Mapping of process corners and Monte Carlo analysis
Two types of simulation are done on this thesis, process corners and Monte Carlo. Like the pre-
vious problem, there were not a standardisation for the two types of simulation by the manufactures.
Each one had its own way to perform the simulation combining different libraries.
First, it is important to understand how each simulation is represented in order to identify at the
technology files.
Starting with the simulation of process corners, the designer can see the effect of global process
variations, due to inaccuracies, temperature and other parameters, PVT. All the process corners
provided by the manufacture are located in the models library on the PDK. As example, for a CMOS
process usually include the following corners: WS Worst case Speed, WP Worst case Power, WO
Worst case One, WZ Worst case Zero and TM Typical Mean. Additionally, more corner models can
be provided for capacitors, resistors, bipolares transistors, etc.
Each manufacture had a different way to present their processes corners. Therefore, create a
generic definition to each process corner is the first step. Table 3.2 provide these information, must
more combination are possible:
Table 3.2: Definition of process corners models.
Corner Mosfet Resistor CapacitorsNmos Pmos
TM: Typical Mean Nominal Nominal Nominal Nominal
WO: Worst Case One Fast Slow Nominal Nominal
WS: Worst Case Speed Slow Slow High High
WP: Worst Case Power Fast Fast Low Low
WZ: Worst Case Zero Slow Fast Nominal Nominal
In the design of an IC is important to simulate the mismatch and process variations, a Monte Carlo
analyses is used to fulfil these simulations. Like the process corner, each manufacture had its own
method to represent this analyses.
In closing, table 3.3 shows the matching of library’s corners and Monte Carlo analyses between
the two technologies in study, X-FAB 350 nm and ATMEL 150 nm SOI, with the generic library.
Table 3.3: Definition of process corners models.
Generic Name Lib: XH035 Lib: AT77K
typ: Typical Mean tm mos nom, rnom, cnom
wo: Worst Case One wo mos fsc, rnom, cnom
ws: Worst Case Speed ws mos wcs, rhigh, chigh
wp: Worst Case Power wp mos bsc, rlow, clow
wz: Worst Case Zero wz mos sfc, rnom, cnom
mc: Monte Carlo mc g mc, matching
37
3.4.2 Mapping file: at77k.lib & xh035.lib
After defining the generic devices and the process analyses, including the corners and Monte
Carlo. The next step was performing a match structure for each technology in study. So, following the
previous chapter, the structure needed to include a device library and the process analyses libraries.
To facilitate the designer finding all the information needed to a specific technology, each matching
structure is located in a single file. For the case of AT77K technology, the file was the name at77k.lib
and for the XH035 technology, the file xh035.lib.
The file structure for XH035 and AT77K technologies, can be divided in two parts, the library of
process analysis and the library of generic devices.
1 ** XH035
2 ** Library process
3 .LIB typ
4 ...
5 .endl
6 .LIB wo
7 ...
8 .endl
9 .LIB wp
10 ...
11 .endl
12 ** Library of devices
13
14 .LIB devices
15 ...
16 .SUBCKT pmos3v3 drain gate source
bulk
17 .PARAM W_eq=W*1e-6
18 .PARAM L_eq=L*1e-6
19 XM0 drain gate source bulk
20 pmos W=W_eq L=L_eq m=Mul
21 .ENDS
22 ...
23 .endl
Listing 3.1: Library to XH035
24 ** AT77K
25 ** Library process
26 .LIB gen
27 ...
28 .endl
29 .LIB typ
30 .lib 'at77k.lib ' gen
31 ...
32 .endl
33 .LIB wo
34 .lib 'at77k.lib ' gen
35 ...
36 .endl
37 ** Library Devices
38
39 .LIB devices
40 ...
41 .SUBCKT pmos3v3 drain gate source
bulk
42 M0 drain gate source bulk
43 pmosox3 L={L*1u} W={W*1u} M=Mul
44 .ENDS
45 ....
46 .endl
Listing 3.2: Library to AT77K
An example of a circuit using the previous mapping files can be seen in the following way.
1 ** Inverter Example Circuit **
2 .INC "at77k.lib" typ
3 .INC "at77k.lib" devices
4 .PARAM VDD =3.3
5
6 XMP0 VOUT VIN NVDD NVDD pmos3v3 W=.6 L=.36 Mul=1
7 XMN0 VOUT VIN 0 0 nmos3v3_elt W=.6 L=.36 Mul=1
8 V0 NVDD 0 DC vdd
9 ** ********* Analysis ***************************
10 .AC DEC 20 1 10G
11 .END
38
3.5 Conclusions
It is known from the literature, that two essential methodologies: procedural generator-based and
optimization-based method have been used to optimized analog circuits design. In this thesis, it was
used the optimized-based method due to its high flexibility and extendibility. However, there is a large
deficit when it comes to the reuse of IP concept. To solve this problem, a new generic cell library was
integrated with an existent genetic algorithm optimized-based method. The new developed structure
layer which contains the generic cell library and a circuit class database was used to facilitate the mi-
gration of different technologies and topologies. This solution combines several existing software with
a special emphasis in the AIDA-C optimizer. AIDA-C optimizer achieves good performance results at
multi-objective, multi-constraint and circuit-level optimization. In addition, to make the system more
user-friendly and to automatically generate all the needed files for AIDA templates, a file configuration
and building scripts were developed.
39
4Operational amplifier database
This chapter presents the file structure for the database, describing the procedures to perform a
correct simulation environment for the class of circuit selected. As well the implementation of several
Op-Amp topologies with the special feature of reaching a rail-to-rail input and output.
As mentioned before, there are two main database required for the solution. The generic library,
already cited, and a circuit class database, created by the designer when a new class of circuit is
added to the database. His creation can be explained using as example the class of circuit Operational
Amplifier Input and Output Rail-to-Rail, R2ROpAmp.
A generic circuit class database is defined by three groups. The first one is identified by the name
of Netlist, all the topologies examples are locate here. The second group establishes the tests and
measures files, it is identified by the name TestBench. The last group is a single configuration file,
with the name default.design, which has all the class circuit’s characteristics but independent of the
circuit topology. Each group is presented in the following sub-chapters. The follow image represented
the graphic diagram for a better understanding.
Figure 4.1: Structure of the database R2ROpAmp.
40
4.1 Testbenches
A class of circuit is characterized by a list of performance parameters. Each parameter is mea-
sured using a data set of simulations files, creating TestBench group.
In this case, the Op-Amp is the circuit class under study. His characterization has already been
mentioned on the background chapter. For each parameter is associated a simulation file, the table
?? resumes all the association.
Table 4.1: Association of which measure to the testbench file.
Testbench file Name Performance Parameter
AC tb.cir.eldo
Gain;
Gain Bandwidth
Phase Margin
PSRRVCM tb.cir.eldo Variation of transconductance;
AC CMRR tb.cir.eldo CMRRTRAN tb.cir.eldo Slew rate;
OutSwing tb.cir.eldo Output-voltage swing;ICMR tb.cir.eldo ICMR;
To reach these requirements, the correct circuit test needed to be performed. It is presented each
testbench created, in order to measure every requirement. The circuit simulator used to conduct the
performance parameters was MENTOR ELDO, so all the database’s testbenches are written for this
software.
4.1.1 AC tb.cir.eldo
The testbench presented in the figure 4.2 is one of the method used to measure the AC per-
formance. This configuration give the possibility to obtain several performance parameters in one
analysis which would normally be required two different testbench. One for measure the PSRR and
other to measure the open-loop characteristics.
The circuit uses an AC small signal source inserted in series with the power supply VDD, a volt-
age common mode source is added to the non-inverting input ”+” and a loop stability source is link
between the output and the inverting input ”−”. Stability analysis traditional are done breaking the
feedback loop, although maintaining a correct DC conditions. This indicate that the loop needs to
terminate with an appropriate impedance which is not always a simple task. The use of the Loop Sta-
bility Analysis, LSTB, simplify this problem with a Middlebrook Technique, a technique that measure
the loop gain by successive injection.
Therefore, the open-loop characteristics are obtained using a specific commands from the LSTB.
The DC gain and gain bandwidth are calculated by the command lstb db but the phase margin
41
use the command lstb p. The remaining measures are done using conventional functions from the
simulator program,YVAL to extract a spefic value from the y-axis, for the x-axis is used the command
XDOWN and final the command MIN ensure the minimum value of a selected waveform.
In order to measure the specifications are done the following analysis, first a .OP, DC operation
point, and closing with AC analysis, .AC.
All the previous commands are jointly executed with the .EXTRACT function from Mentor Eldo. The
next brief code presents the structure how to calculated the following parameters, the Open-Loop
Gain, GDC, Gain Bandwith, GBW, the phase margin, PM, and PSRR, PSRR.
1 .EXTRACT AC label = GDC YVAL(lstb_db ,1)
2
3 .EXTRACT AC label = GBW XDOWN(lstb_db ,0,start ,end)
4
5 .EXTRACT AC label = PM MIN(lstb_p ,start ,Extract(GBW)) + 180
6
7 .EXTRACT AC label = PSRR YVAL(VDB(OUT) ,1)
The simulation configuration circuit are present on the next figure, figure 4.2.
Figure 4.2: Configuration for simulating the open-loop frequency and PSRR.
In order to evaluate the veracity of the previous commands, a graphic presentation of the wave-
forms used are presented.
Starting with the figure 4.3, where the waves lstb d and lstb db are shown, it is possible to
measures the parameters open loop gain, define by the name Gain in the figure, the gain bandwidth,
with his same name on the figure, and finally the phase margin.
42
Figure 4.3: Waveform simulation of the LSTB output, magnitude response in green and phase response in blue.
The final parameter is measured from the wave V(OUT), as can be seen in the figure 4.4 confirming
the code.
Figure 4.4: Waveform simulation of PSRR magnitude response.
4.1.2 VCM tb.cir.eldo
The variation of the input stage transconductance is an important measure for this type of circuit
class. The transconductance affects a numbers of parameters on the Op-Amp, so, this value needed
to have the minimal variation possible, as previously mentioned on the beginner of the thesis.
The previous testbench of the figure 4.2 is used to perform the needed analysis. The simulation
uses the same structure, the change only occurs on the type of analysis. It is perform a DC Sweep
analysis of the common mode voltage source, VCM, from 0 to VDD.
The correct value of the full input transconductance are given by the sum of each input differential
pair, N and P type. This type of operation can be done using the .DEFWAVE function from Mentor
Eldo. The command is used to define a new waveform by using previously defined wave, like in this
case, the final waveform is created by summing the input transconductance of each differential pair,
originating the waveform GMPAIR.
43
1 .DEFWAVE GMPAIR =(GM(Xuut.XMN1.XM0.X1.M1) + GM(Xuut.XMP1.M0))
After defining the waveform for the input transconductance, it is possible to measure his variation
from the average value. The first step is measuring of the average value, can be done using the func-
tion AVERAGE from the command .EXTRACT. With the average value define the final step is calculating
the positive variation classified by the name VARGMP and the negative by the name VARGMN.
1 .EXTRACT DC label=AV average(W(GMPAIR), start , end)
2
3 .EXTRACT DC label=MIN MIN(w(GMPAIR) ,0,3.3)
4 .EXTRACT DC label=MAX MAX(w(GMPAIR) ,0,3.3)
5
6 .MEASURE DC VARGMP =param (100*( ABS(AV-MAX))/MAX)
7 .MEASURE DC VARGMN =param (100*( ABS(AV-MIN))/MIN)
The figure 4.5 present a graphic explanation.
Figure 4.5: Waveform simulation of the VCM variation, transconductance of the differential pair in blue.
4.1.3 AC CMRR tb.cir.eldo
There is the need to eliminate the common signal of both inputs for a correct functioning of an
Op-Amp. Therefore, the common mode rejection ratio, CMRR, is an important requirement, defining
the standard measurement factor when comparing differential circuits. The equation 4.1 is used to
calculate the CMRR.
CMRR =AdAc
(4.1)
In which the Ad and Ac stands for differential gain and common-mode gain in the same order.
There are several solutions to perform this measurement using different configurations, such as
Matched Sources Measurement Setup, Power Supply Measurement, DC CMRR Measurement Setup
and Matched Resistor Measurement Setup [36].
44
The solution selected is presented on the figure 4.6, represents the method Matched Resistor
Measurement Setup. The circuit is composted by a differential amplifier configuration with the two
inputs link together, using matching resistor. The problem associate with this circuit is the non direct
measure of CMRR. So, it is important to reach a relation to the input and the output in order to
reaches the value of CMRR, the following equations represent in the system 4.2 will give the relation.
Figure 4.6: Configuration for simulation the CMRR.
Vout = VcAd + VdAd
Vd = VINP − VINNVc = VINP+VINN
2
VINN = VINRR+R + VoutR
R+R
VINP = VINRR+R
(4.2)
Using the previous system of equations in order to isolate the ratio of Ad with Ac by relating with
the output and input signal, like it is possible to see on the following equation.
Vout = (VIN
2+Vout
4)Ad +
Vout2Ad
2 +AdAC
=VIN + Vout
2
Vout2 +AdAC
=VcVout
(4.3)
Assuming that Ad � 1, the CMRR can be given by the following equation,
VcVout
=AdAC
= CMRR (4.4)
So, measuring the CMRR using the Mentor Eldo, it is needed to selected tree signals from the
testbench, the output voltage, V(OUT), the inverting and non-inverting input voltage, VINN and VINP.
45
With the signals define, applying the relation develop on the equation 4.4 is the first step, therefore
using the function .DEFWAVE to establish the waveform InCMRR. After, the value of the CMRR can
easily be obtained using the function .EXTRACT with the command YVAL. As can be observed in the
next code.1 .DEFWAVE InCMRR= 2*(v(OUT)/(V(NETVINP)+V(NETVINN)))
2
3 .EXTRACT AC label=CMRR YVAL(wdb(InCMRR) ,1)
The graphic presentation can be seen on the figure 4.7
Figure 4.7: Waveform simulation of the CMRR magnitude response.
4.1.4 TRAN tb.cir.eldo
Another crucial parameter to characterize an Op-Amp is the Slew Rate. First, it is not frequency
response but instead it is the ability of the output change from one value to other within a certain time,
typically measured by V/µs.
The circuit configuration of the Op-Amp lead to different values of the slew rate on the positive and
negative transitions. This occurs because the complementary output configuration pull the signal to
both directions, up and down, and this means the two sides of the circuit cannot be the same.
An unit-gain configuration can be use to perform this measure. This configuration presented a
largest feedback, resulting in the largest values of loop gain. Therefore, it should only be used to
worst-case measurement. That is why the unit-gain configuration testbench was selected for this
work, as can be seen in figure 4.8.
The circuit uses a pulse function, PULSE, link on non-inverting input. The signal generate is an
impulse of 5µs starting in 0 Volts and finish in VDD with a rising and falling time of 25ps.
A transient analysis with a period of 10µs are performed in order to measure the Slew Rate. The
following code demonstrate how to extract the measure using Mentor Eldo.
1 .EXTRACT TRAN label=SLWUP (SLEWRATE(v(OUT),VTH=((VDD+VSS)/2),BEFORE =(1u+2.5u))*(1u))
2 .EXTRACT TRAN label=SLWDOWN (SLEWRATE(v(OUT),VTH =((VDD+VSS)/2),AFTER =(1u+2.5u))*(1u))
Where SLWUP represents the positive Slew Rate and the SLWDOWN the negative Slew Rate.
46
The followed figure represent the circuit of the testbench used to performed the transient analysis.
Figure 4.8: Configuration for simulate the Slew Rate.
The graphic representation can be seen on the figure 4.9.
Figure 4.9: Waveform simulation of the Slew Rate, the input signal in blue and the output in green.
4.1.5 OutSwing tb.cir.eldo
The class of circuit in study represents an Op-Amp rail-to-rail output. Therefore, the output voltage
range of the amplifier can span one supply to the other. But in reality, the use of complementary CMOS
to preform the output stage limit the voltage range due to the internal resistance of the transistors, so
the output voltage swing will be reduced.
47
For this reason it is important to know how close the amplifier is from a true output rail-to-rail. This
specification is typically noted as VOH and VOL, which stands for the high-level and the low-level output
level respectively.
As the output voltage reach to his extremes, the output transistors are pushed into the triode re-
gion, dropping the voltage gain. Therefore, the necessity of measure the maximum voltage available
is crucial for a correct operation of the Op-Amp. With this idea, selecting a correct testbench config-
uration is important, in order to examine the gain as the output-voltage swings grows and obtain the
values of VOH and VOL.
The testbench selected are present on the figure 4.10, the Op-Amp are placed in an inverting
configuration, where it is applied a DC Sweep input signal to perform a transfer curve output signal.
The output-voltage swing is located on the linear part, so, when the linearity is lost the values of VOH
and VOL can be obtained.
Figure 4.10: Configuration for simulation the Output Swing Voltage.
Therefore, a DC Sweep analysis is applied on the source voltage V1 starting in −0.35V and finish
in 0.02V (this values can be change if the supply voltage is different of 0V to 3.3V). At the output it will
be seen an transfer function starting in 3.3V and finish in 0V, with an linear slope of 10 (Represents
the inverting gain of the configuration R1R0 = 10). The derivative of the output signal is applied to locate
the needed slope, for this analysis, it is allowed a 10% drop of the gain. So when the slope is equal to
9, the measures of VOH and VOL can be located. The following code express all the need functions to
obtain the measures using the Mentor Eldo.1 .DEFWAVE DDOUTt=DERIV(V(OUT))
2 .EXTRACT label=VOH (VDD -xycond(V(OUT), W(DDOUT) <-9,-0.34,-0.3))
3 .EXTRACT label=VOL (xycond(V(OUT), W(DDOUT) >-9,-0.04,0.02)-VSS)
48
The graphic representation can be seen on the figure 4.11
Figure 4.11: Waveform simulation of the Output-Voltage Swing.
4.1.6 ICMR tb.cir.eldo
The creation of the current testbench aims to validate if the topology selected has the characteristic
needed to the class of circuit in study, Op-Amp with an input rail to rail.
The definition of this parameter consists to identify the range of input voltage where the Op-Amp
will operate correctly. So, the idea is to sweep the common mode input voltage in order to identify
where the normal operation output will no longer be possible. Identifying the voltage edges, where
the low voltage is named by VIL and the high voltage with VIH.
The testbench selected is based on the example of the figure 4.12, where the Op-Amp is placed
in a differential configuration. The goal was to obtain a constant value in the output voltage, in this
case, the constant is equal to the common mode voltage, VCM.
Firstly, it is important to understand the selection of the differential configuration, the reason are
located on the output result signal, given by the sum of the non-inverting and inverting configurations.
As can be seen on the follower equation.
Voni = (1 +R1
R2)Vin1 Non-inverting Configuration
Voi = −R1
R2Vin2 Inverting Configuration
(4.5)
The differential output configuration is given by adding the two previous equations.
Vout = Voni + Voi
Vout = (1 +R1
R2)Vin1 −
R1
R2Vin2
(4.6)
The input variation signal can be eliminated using the difference factor between the non-inverting
and inverting input. So, it is possible to have a constant value in the output.
49
Having the equation of this configuration, assuming all the resistor are equal, the output needed
to be equal to VCM and on the non-inverting input terminal is applied a signal VIN, obtaining the input
signal to the inverting terminal of the Op-Amp is the next step. So, the follower equations demonstrate
the final result of this final signal.
Vout = Vvcm ⇔
(1 +R
R)VV IN −
R
RVin2 = Vvcm ⇔
Vin2 = (1 + 1)VV IN − Vvcm ⇔
Vin2 = 2VV IN − Vvcm
(4.7)
The signal needed to be apply to the inverting input is 2*VIN-VCM. As can be seen on the figure
4.12.
Figure 4.12: Configuration for simulation the Input Common-Mode voltage Range, ICMR.
To performing this simulation, the simulator need to allow the DC sweep of two voltage sources.
Unfortunately, the Eldo Mentor don’t allow this type of analysis, only with one voltage source, so the
figure 4.13 presents the solution to this problem.
Figure 4.13: Configuration for simulation the Input Common-Mode voltage Range, ICMR.
Therefore, a DC Sweep analysis is applied on the source voltage V1 starting in −2V and finish in
50
9V. At the output it will be seen an constant signal with the value of the VCM=1.65. When the Op-Amp
loses this linear behaviour, it is possible to measure the value of VIL and VIH. So, the derivative of the
output signal is applied to locate where his slope is higher than 0.001, a value near to 0. The following
code express all the need functions to obtain the measures using the Mentor Eldo.1 .DEFWAVE DDOUT=ABS(DERIV(V(OUT)))
2 .EXTRACT label=VIL xycond(V(VINP), W(DDOUT)<1m,-2,1)
3 .EXTRACT label=VIH xycond(V(VINP), W(DDOUT)>1m,7,9)
The graphic representation can be seen on the figure 4.14.
Figure 4.14: Waveform simulation of the Input Common Mode Range, ICMR.
4.2 Netlists circuits
As discussed in the former chapter, each Op-Amp topologies employ a traditional a two gain
stages, differential pair and a folded cascode stage, in order to achieve high impedance and gain
followed by a class-AB output stage, providing an output rail-to-rail.
The followers Op-Amp topologies are designed in virtuoso’s environment with Generic Library
process, having previously presented.
The next sub-chapters it will be presented the three topologies use to test the proposed solution.
4.2.1 YanLu circuit
As already said on the initial chapter, the circuit topology presented here was selected from the
paper [6]. Like the presentation of the topology, it was started with the first stage and the circuit for
the control of the input transconductance of the Op-Amp.
The Yan Lu circuit consist in having two dummies input differential pairs in order to control the
tail current, as can be seen the MP3 and MP4 defining the p-type differential pair and the MN3 and
51
MN4 the n-type. Plus two input differential pairs to perform the rail to rail input stage, defining by the
transistors MP1, MP2, MN1 and MN2, and a conjunction of current mirrors for providing all the correct
current to the circuit. As can be seen on the following figure, 4.15.
Figure 4.15: The first stage with control of the input transconductance from Yanlu circuit.
The table 4.2 presents the name list of the devices used and their variable names. The geometry
relation of the devices and the function of each device in the circuit also can be seen. It is important
to refer that the variable named AT is used to reach the equation 2.16 by equally the µP (W/L)P with
µN (W/L)N . The value it will be present on the next chapter.
Table 4.2: The list of devices and variables of Yanlu circuit.
PMOS NMOS
Device W L Mul Description Device W L Mul Description
MP1 = MP2 MNA*WN1 LN1 MN1 Differential Pair MN1 = MN2 WN1 LN1 MN1 Differential Pair
MP3 = MP4 MNA*WN1 LN1 MN1 Dummy Diff. Pair MN3 = MN4 WN1 LN1 MN1 Dummy Diff. Pair
MP5 WP5 LP5 MP5 Current Mirrors MN5 = MN6 WN5 LN5 MN5 Current Mirrors
MP7 3*WP5 LP5 MP5 Current Mirrors MN8 3*WN5 LN5 MN5 Current Mirrors
MP8 4*WP5 LP5 MP5 Current Mirrors MN9 4*WN5 LN5 MN5 Current Mirrors
MP6 WP6 LP6 MP6 Current Control MN7 WN7 LN7 MN7 Current Control
The second stage presented consisted on a folded cascode and a class AB output stage. As
already mention, the initial circuit from the chapter 2.2.2 don’t present an rail to rail output, so it has
52
needed to add this feature with a class AB output circuit. The follower image presents the migration
of the class AB proposed with the folded cascode already implement in the solution.
Figure 4.16: The second stage with a class AB output stage from Yanlu circuit.
In a similar way, the table 4.3 presents the list of devices and their variables, plus the relation
geometry needed to the correct operation of each device.
Table 4.3: The list of devices and variables of Yanlu circuit.
PMOS NMOS
Device W L Mul Description Device W L Mul Description
MP10 = MP11 WP10 LP10 MP10 Folded Cascode MN11 = MN12 WN11 LN11 MN11 Folded Cascode
MP12 = MP13 WP12 LP12 MP12 Folded Cascode MN14 = MN13 WP13 LP13 MP13 Folded Cascode
MP15 WP15 LP15 MP15 Polar. of VBIAS1 MN10 WN5 LN5 MN5 Polar. of VBIAS1
MP14 WP14 LP14 MP14 Polar. of VBIAS1 MN15 WN15 LN15 MN15 Polar. of VBIAS2
MP15 WP15 LP15 MP15 Polar. of VBIAS2 MN16 WN16 LN16 MN16 Polar. of VBIAS2
MPO16 WPO16 LPO16 MPO16 Class AB MNO20 WN5 LN5 MN5 Class AB
MPO17 WPO17 LPO17 MPO17 Class AB MNO18 WNO18 LNO18 MNO18 Class AB
MPO21 WP5 LP5 MP5 Class AB MNO19 WNO19 LNO19 MNO19 Class AB
MPO25 WPO25 LPO25 MPO25 Class AB MNO24 WNO24 LNO24 MNO24 Class AB
MPO22 WPO22 LPO22 MPO22 Class AB MNO23 WNO23 LNO23 MNO23 Class AB
The final overview netlist building with the generic components can be seen on the appendix xxx.
53
4.2.2 NimaShahpari circuit
The topology presented is named by his author Nami Shahpari [5]. Following the same structure
of a presentation from the last topology, starting with the first stage and the control of the input
transconductance.
As already refer on the initial chapter, a single n-type differential pair is used in this topology and a
DC level shifter to perform a constant transconductance as Vcm varies from rail to rail. So, it is possible
to define each part of the circuit, the differential pair is defined by the transistor M1 and M2, the DC
level shifter by the transistors MDC2, MDC21, MDC1 and MDC11, the multiplexer is created by the
transistors from MS0 to MS7, being controlled by a set of inverters assembled with the transistors
MS8 to MS13. The remainder transistors build the needed current mirrors, the figure 4.17 presents
all this parts of the circuit.
Figure 4.17: The first stage with control of the input transconductance from NimaShahpari circuit.
To resume all the figure it is presented a table, table 4.4, with all the transistors names, functions
and variables to perform the optimization.
Table 4.4: The list of devices and variables of NimaShahpari circuit.
PMOS NMOS
Device W L Mul Description Device W L Mul Description
– – – – – M1=M2 W1 L1 M1 Differential Pair
MIDC3 WIDC3 LIDC3 MIDC3 Current Mirrors MI1=MI2=MIDC1 WI1 LI1 MI1 Current Mirrors
MDC21 = MDC2 WDC2 LDC2 MDC2 DC Level MDC11=MDC1 WDC1 LDC1 MDC1 DC Level
MS1 = MS3 WSP LSP 1 Multiplexer MS0 = MS2 WSN LSN 1 Multiplexer
MS5 = MS6 WSP LSP 1 Multiplexer MS4 = MS7 WSN LSN 1 Multiplexer
MS8=MS10=MS12 WSP LSP 1 Control of Mult. MS9=MS11=MS13 WSN LSN 1 Control of Mult.
In the similar way, the second stage is performed by a folded cascode and a class AB output stage.
As all the previous circuit, the initial circuit didn’t present a rail-to-rail output, so it was required to add
54
a class AB output stage. As seen on the figure 4.18.
As always, all the list of the devices and their variables are present on the following table 4.5.
Table 4.5: The list of devices and variables of NimaShahpari circuit.
PMOS NMOS
Device W L Mul Description Device W L Mul Description
M9=M10 W9 L9 M9 Folded Cascode M5=M6 W5 L5 M5 Folded Cascode
M7=M8 W7 L7 M7 Folded Cascode M3=M4 W3 L3 M3 Folded Cascode
MI16=MI14 WI15 LI15 MI15 Current Mirrors MI3=MI15 WI1 LI1 MI1 Current Mirrors
MI8=MI9 WI15 LI15 MI15 Current Mirrors MNO1 WNO1 LNO1 MNO1 Class AB
MPO1 WPO1 LPO1 MPO1 Class AB MI7 WI7 LI7 MI7 Polar. of VB3
MI5 WI5 LI5 MI5 Polar. of VB2 MI6 WI6 LI6 MI6 Polar of VB3
MI4 WI4 LI4 MI4 Polar. of VB2 MI10 WI10 LI10 MI10 Polar. of VB1
– – – – – MI11 WI11 LI11 MI11 Polar. of VB1
– – – – – MI12 WI12 LI12 MI12 Polar. of VB0
– – – – – MI12 WI12 LI12 MI12 Polar. of VB0
Resistor Capacitor
Device W L Mul Description Device W L Mul Description
R0 WRO1 LRO1 MRO1 Class AB C0 WCO1 LCO1 MCO1 Class AB
Figure 4.18: The second stage with a class AB output stage from NimaShahpari circuit.
55
4.2.3 CurrentFlow circuit
The circuit presented here was not referenced in the background chapter, as well any reference it
will be added to the author’s request.
That said, an explanation it will be done using the previous flow explanations. Starting with the
initial stage plus the control circuit of the transconductance and finalize with the cascode stage plus
the output stage perform by a class AB.
The structure used to create the functionality of an input rail-to-rail, are done by the classical
structure of two differential pairs, one of N-type and other of P-type. As already mention this solution
creates a problem of current duplicity when the two differential pairs are on. So, adding a structure to
reduce this current is mandatory.
The control is done using two mirror currents and two dummies differential pairs, as can been
seen on the figure 4.19. The dummies differential pairs are constant polarized by VPOLAP and VPOLAN
from the polarization of the folded cascode, this characteristics gives to the input differential pairs the
total flow current control.
In order to understand the circuit in study, a current analysis is performed. As already mentioned,
the behaviour of the transconductance can be performed using this type of analysis, applied a three
different values of VCM. Before starting to describe each analysis is important to refer two initial
characteristics of the topology, the final current send to the folded cascode is always equal to twice
the current of reference, I. The tail currents transistors of each differential pair are always in saturation,
MN3 and MP3.
Figure 4.19: Current flow for a VCM = 0 [V].
56
The figure 4.19 shows the current flow, in red, when is applied a zero voltage to a VCM. Only the
differential pair type-P is on saturation mode, knowing that the circuit will consume twice the reference
current and the tail current transistor MP3 only provide an unit of reference current. Obviously, there
is the needed of adding a circuit to provide this extra reference current. Like, the circuit composed by
the transistors MP8 and MP9 and the dummy differential pair type-N. As can be seen on the figure,
the circuit will provide the extra reference current and will put the transistor MN3 in saturation.
When is applied a VDD/2 voltage to VCM, the two differential pairs are on saturation mode, follow
the same idea of sending twice the reference current to the folded cascode, each pair will consume
one reference current from the tail current transistors, MP3 and MN3. The circuit of current control do
not consume or produce any current to the circuit as can be seen on the figure 4.20.
Figure 4.20: Current flow for a VCM = VDD/2 [V].
The final analysis corresponds to apply a VDD voltage a VCM. So, only the differential pair type-
N will stay in saturation mode, as already mention the total current delivered is equal to twice the
reference current and the tail current transistor MN3 only provide an unit of reference current. The
current control circuit is needed to provide the extra current, as similar to the one previous presented
the circuit is composed by a current mirror, performed by the transistors MN9 and MN8 and the
dummy differential pair type-P. Like in first analysis, the opposite tail current transistor need to have in
saturation mode, MP3 .
57
Figure 4.21: Current flow for a VCM = VDD [V].
The topology presented is named by the type of control, CurrentFlow circuit. Following the same
structure of a presentation from the past two topology, the first part presents the initial stage and
control of the input transconductance and finalise with the folded cascode and the final stage, perform
by a class AB.
Figure 4.22: The first stage with control of the input transconductance from CurrentFlow circuit.
58
As already mention how the first stage work, the figure 4.22 presents the complete schematic with
all the polarization circuit.
All the transistors names, functions, geometry and variables to perform the optimization are re-
sume on the table 4.6.
Table 4.6: The list of devices and variables of CurrentFlow current.
PMOS NMOS
Device W L Mul Description Device W L Mul Description
MPA = MPB AT*WNA LNA MNA Differential Pair MNA = MNB WNA LNA MNA Differential Pair
MPAD = MPBD AT*WNA LNA MNA Dummy Dif. Pair MNAD = MNBD WNA LNA MNA Dummy Dif. Pair
MP3=MP11=MP16 WP1 LP1 MP1 Current Mirrors MN3=MN14=MN13 WN3 LN3 MN3 Current Mirrors
MP8=MP9 WP1 LP1 MP1 Current Mirrors MN9=MN8 WN3 LN3 MN3 Current Mirrors
MP1=MP2 2*WP1 LP1 MP1 Current Mirrors MN1=MN2 WN1 LN1 MN1 Current Mirrors
MP4=MP5 2*WP1 LP1 MP1 Current Mirrors MN15=MN12 WN12 LN12 MN12 Current Mirrors
MP17=MP14=MP12 WP12 LP12 MP12 Current Mirrors MN11 WN11 LN11 MN11 Current Control
MP15 WP15 LP15 MP15 Current Control – – – – –
In the similar way, the second stage is performed by a folded cascode and a class AB output stage.
As all the previous circuit, the initial circuit didn’t present a rail-to-rail output, so it was required to add
a class AB output stage. As seen on the figure 4.23.
As always, all the list of the devices and their variables are present on the following table 4.7.
Table 4.7: The list of devices and variables of CurrentFlow circuit.
PMOS NMOS
Device W L Mul Description Device W L Mul Description
MP4=MP5 2*WP1 LP1 MP1 Folded Cascode MN4=MN5 WN1 LN1 MN1 Folded Cascode
MP6=MP7 WP6 LP6 MP6 Folded Cascode MN7=MN6 WN6 LN6 MN6 Folded Cascode
MP18 WP1 LP1 MP1 Current Mirrors MN16 WN16 LN16 MN16 Polarization for VPOLANBuff
MP19 WP12 LP1 MP1 Current Mirrors – – – – –
MP10 WP10 LP10 MP10 Class AB MN10 WN10 LN10 MN10 Class AB
Resistor Capacitor
Device W L Mul Description Device W L Mul Description
R1 WR1 LR1 MR1 Class AB C1 WC1 LC1 MC1 Class AB
59
Figure 4.23: The second stage with control of the input transconductance from CurrentFlow current.
4.3 Configuration file default.design
The final step to complete the circuit database consists on the creation of default.design file.
The needed came form the necessity to build the AIDA-C configuration file design.xml.
The design.xml file, as already mentioned, has certain requirements needed to be fulfilled. The
requirements can be divided into two groups, the independent class-characteristic topology or the
dependent class-characteristic topology.
The independent class-characteristic topology merge all the tesbenchs previous presented, the
list of corners and independent constrains. Defining all the default requirements of the circuit class on
the default.design file. In order to the script understand all the requirements some key words are
defined, as can be see on the list bellow.
• START CORNER : Command for the script, defining the beginning of the default corner;
• END CORNER : Command for the script, defining the ending of the default corner;
• START TESTBENCH: Command for the script, defining the beginning of the default testbench;
60
• END TESTBENCH : Command for the script, defining the ending of the default testbench;
• START CONSTRAINS : Command for the script, defining the beginning of the default constrains;
• START CONSTRAINS : Command for the script, defining the beginning of the default constrains;
The dependent class-characteristic topology merge all the topology dependent requirements cre-
ated by the script. This type of requirements are defined on the default.design file by the key word
MEASURE.
The defaults values used in this project can be resume on the following tables. Starting with the
default corners presented on the table 4.8, was chosen four cases of PVT, defining the two typical
cases, Worst Speed ( Worst Speed process, high temperature and low voltage supply) and Worst
Power(Worst Power process, low temperature and High voltage supply). The other two PVT cases
represent the Worst One case and Worst Zero case combining the variation of temperature and supply
voltage.
Table 4.8: Default Corner Process.
Name Process Supply Voltage Temperature
wp TempLow VDDHigh Worst Power WP VDD*1.05 = 3.465 [V] -55 [◦C]
ws TempHigh VDDLow Worst Speed WS VDD*0.95 = 3.135 [V] 125 [◦C]
wo TempLow VDDHigh Worst One WO VDD*1.05 = 3.465 [V] -55 [◦C]
wz TempLow VDDLow Worst Zero WZ VDD*0.95 = 3.135 [V] -55 [◦C]
For the circuit class in study, defining the default values of each parameter and what are the
objectives of the optimization. So, to a easy comprehension all the default values of each parameters
will be present on the table 4.9 associating with the testbench already presented on the section 4.1.
The default.design for the circuit class in study, Operational Amplifier With Rail-To-Rail Input or
Output, R2ROpAmp.
61
Table 4.9: Default Values of the Constrains and Objectives.
Constrains
Testbench Measure Name Condition Value
AC tb.cir.eldo GDC Greater than [≥] 70 [dB]
AC tb.cir.eldo GBW Greater than [≥] 60 [MHz]
AC tb.cir.eldo PM Greater than [≥] 45 [◦]
AC tb.cir.eldo PSRR Lower than [≤] -70 [dB]
VCM tb.cir.eldo VARGMP Lower than [≤] 4 [%]
VCM tb.cir.eldo VARGMN Lower than [≤] 4 [%]
AC CMRR tb.cir.eldo CMRR Lower than [≤] -70 [dB]
TRAN tb.cir.eldo SLWUP Greater than [≥] 5 [V/µs]
TRAN tb.cir.eldo SLWDOWN Greater than [≥] 5 [V/µs]
OutSwing tb.cir.eldo VOH Lower than [≤] 0.1 [V]
OutSwing tb.cir.eldo VOL Lower than [≤] 0.1 [V]
ICMR tb.cir.eldo VIH Greater than [≥] 3.3 [V]
ICMR tb.cir.eldo VIL Lower than [≤] 0 [V]
Objectives
Testbench Measure Name Objective
AC tb.cir.eldo IDD Minimize
VCM tb.cir.eldo VARGMP Minimize
VCM tb.cir.eldo VARGMN Minimize
4.4 Conclusion
In this chapter, a basic structure for a generic class circuits was presented, using as a case study,
an operational amplifier with rail-to-tail input or output.
With the independent topology testbenchs, it was possible to identify how all the measures were
extracted. In addition, three circuit topologies were also presented in order to demonstrate the veracity
of the solution proposed by the use of developed generic cell library.
Finally, a default file with default values is created to complete the AIDA-C configuration file,
design.xml.
62
5Results
The current chapter presents the final procedure, execution and collection of results in order to
validate the solution presented. Presenting the decision procedure to choose the best topologies.
And all post-optimization analyses possible, showing the versatility of this solution.
As it is known, the solution gives the designer an easy and fast migration of different topologies
and technology. Therefore, it needs to be validated.
5.1 Results
All the results that will be presented are based on the AIDA-C automatic generator. As already
mentioned, AIDA-C generates a value for a variable by defining a range of values and its stepping.
The variable is the dimensions of CMOS. The table 5.1 presents the default ranges used in the
optimization process for the variables W, L and Multiplicity.
Table 5.1: Default variable ranges used.
Type of Variable Min Max Step
W 1 30 0.1
L 0.4 10 0.1
Mul 1 1000 1
The results concerning the circuits will be presented in the next chapters, starting with the pre-
sentation of the configuration file for each topology and technology selected. Following, with the
optimization results. Finalizing with the validation of all the results accomplishing a post-optimization
simulations for a better characterization of the circuit.
63
5.1.1 Selection of the best topology
The solution validation is step present in the current chapter. The validation need to prove two
essential characteristics:
• Technology independent system;
• Topology independent system;
The circuit netlist needed to be created using the generic cell library, already shown in the chapter
4.2 for all three topologies.
The configuration file of each topology and its respondent technology will merge all the information
to build the correct setup for AIDA-C. The class of circuit, CLASS, is the same for all the configuration
files with a code name R2ROpAmp.
The circuit topology, CIRCUIT, is specific for each topology, the parameter will receive the relative
path to a netlist file.
• For the case of NimaShahpari circuit: .../R2ROpAmp/Netlist/shah.cir;
• For the case of Yanlu circuit: .../R2ROpAmp/Netlist/yanlu.cir;
• For the case of CurrentFlow circuit: .../R2ROpAmp/Netlist/currentflow.cir;
The correct operation will be accomplish by defining the circuit measures, MEASURES. Setting all
transistors needed to be in linear zone, using the command +SAT plus the name of each device. It will
inform the script to perform the calculation for the overdrive and saturation margin. The variation of
the transconductance could be measured using the command +GMPAIR identifying the input differential
pair transistors. The list of transistors change for each topology.
The circuit technology, TECHNOLOGY, defines the two technologies in study, at77k and xh035. So
each topology will have a configuration file to each technology.
In order to validate the description it is presented all configuration files.
5.1.1.A Configuration file: NimaShahpari
1 ** ***********************
2 *** Author: Nuno Machado
3 *** Year: 2016
4 *** Local: IT Lisbon , IST
5 *** Comment: Circuit of Yanlu with
the technology at77k
6 ** ************************
7
8 TECHNOLOGY: at77k
9
10 CLASS: R2ROpAmp
11
12 CIRCUIT: .../ R2ROpAmp/Netlist/yanlu.cir
13
14 MEASURES: +SAT: {ALL , MP1 , MP2 , MN1 ,
15 MN2} VOV =0.1 DELTA =0.15
16 +SAT: {MP1 , MP2 , MN1 ,
17 MN2} VOV =0.05 DELTA =0.1
18 +GMPAIR: {MN1 , MP1}
Listing 5.1: Configuration file to Yanlu on the tech:at77k.
1 ** ***********************
2 *** Author: Nuno Machado
3 *** Year: 2016
4 *** Local: IT Lisbon , IST
5 *** Comment: Circuit of Yanlu with
the technology xh035
6 ** ***********************
7
8 TECHNOLOGY: xh035
9
10 CLASS: R2ROpAmp
11
12 CIRCUIT: .../ R2ROpAmp/Netlist/yanlu.cir
13
14 MEASURES: +SAT: {ALL , MP1 , MP2 , MN1 ,
15 MN2} VOV =0.1 DELTA =0.15
16 +SAT: {MP1 , MP2 , MN1 ,
17 MN2} VOV =0.05 DELTA =0.1
18 +GMPAIR: {MN1 , MP1}
Listing 5.2: Configuration file to Yanlu on the tech:xh035.
64
5.1.1.B Configuration file: Yanlu
1
2 *** Author: Nuno Machado
3 *** Year: 2016
4 *** Local: IT Lisbon , IST
5 *** Comment: Circuit of NamiShahpari
with the technology at77k
6
7 TECHNOLOGY: at77k
8 CLASS: R2ROpAmp
9 CIRCUIT: .../ R2ROpAmp/Netlist/shah.cir
10
11 MEASURES :+SAT:{ALL , MS0 , MS1 , MS2 , MS3 ,
12 MS4 , MS5 , MS6 , MS7 , MS8 , MS9 , MS10 ,
13 MS11 , MS12 , MS13 , M1, M2 , MI12 , MI11 ,
14 MI6 , MI5} VOV =0.1 DELTA =0.15
15 +SAT:{M1 , M2} VOV =0.05 DELTA =0.15
16 +GMPAIR :{M1}
Listing 5.3: Configuration file to NimaShahpari onthe tech: at77k.
1
2 *** Author: Nuno Machado
3 *** Year: 2016
4 *** Local: IT Lisbon , IST
5 *** Comment: Circuit of NamiShahpari
with the technology at77k
6
7 TECHNOLOGY: xh035
8 CLASS: R2ROpAmp
9 CIRCUIT: .../ R2ROpAmp/Netlist/shah.cir
10
11 MEASURES :+SAT:{ALL , MS0 , MS1 , MS2 , MS3 ,
12 MS4 , MS5 , MS6 , MS7 , MS8 , MS9 , MS10 ,
13 MS11 , MS12 , MS13 , M1 , M2 , MI12 , MI11 ,
14 MI6 , MI5} VOV =0.1 DELTA =0.15
15 +SAT:{M1 , M2} VOV =0.05 DELTA =0.15
16 +GMPAIR :{M1}
Listing 5.4: Configuration file to NimaShahpari onthe tech: xh035.
The selection of the class of circuit, R2ROpAmp, was used to define which circuit database will be
chosen. The default.design file define all the measures that will be preform on the optimization
process. The results were presented uses as objective the minimization of positive and negative
variation of the input transconductance.
The traditional presentation of the results in this type of optimization circuit process are performed
by a Pareto Front. The enhancement of an objective performance is impossible to obtain without com-
promise others. One example, it is the engagement of the power consumption with gain bandwidth or
dc gain. However the objectives chosen for this thesis did not create a Pareto Front. Therefore, the
results presented here refer to the best achieved in each technology.
Figure 5.1: The results of objective optimization in tech at77k for all three topologies used.
Using the results of the graphic 5.1, it is possible to see the best topology for the objective selected
in the technology at77k. As can be seen, the topology NimaShahpari presents the best achieved
solution. The table 5.2 give a complete parametrization.
65
Table 5.2: Values of the parameters for the circuit NimaShahpari with the tech at77k.
AT77KParameter Typical C[0] C[1] C[2] C[3] Seek
IDD [mA] 30.86 31.7 30.3 31.6 30.6GDC [dB] 101.9 97.8 102.3 97.8 103.9 [≥] 70GBW [MHz] 72.9 95.2 55.6 83.9 95.4 [≥] 60PM [◦] 51.8 51.7 53.2 56.1 46.6 [≥] 45PSRR [dB] -94.4 -77.6 -101.8 -78.9 -104.4 [≤] -70VARGMP [%] 0.11 0.45 0.19 1.05 0.51 [≤] 4VARGMN [%] 0.35 0.69 0.93 1.63 0.76 [≤] 4CMRR [dB] -86.6 -90.0 -74.5 -92.3 -92.0 [≤] -70SLWUP [V/µs] 69.9 73.9 61.4 67.7 74.0 [≥] 5SLWDOWN [V/µs] 66.4 69.2 65.4 67.6 68.3 [≥] 5VOH [mV] 55.6 68.6 71.1 68.6 49.3 [≤] 100VOL [mV] 9.6 8.1 34.1 8.1 3.0 [≤] 100VIH [V] 3.57 3.77 3.36 3.77 3.57 [≥] 3.3VIL [V] -0.26 -0.29 -0.18 -0.4 -0.31 [≤] 0.0
In the same way, it was perform the optimization process for the technology xh035, reaching a
similar result. The topology NimaShahpari shows the best results in the objective selected.
Table 5.3: Values of the parameters for the circuit NimaShahpari with the tech xh035.
XH035Parameter Typical C[0] C[1] C[2] C[3] Seek
IDD [mA] 13.24 13.58 13.11 13.26 12.93GDC [dB] 89.5 87.0 88.0 94.2 86.5 [≥] 70GBW [MHz] 62.1 87.3 45.4 79.6 77.3 [≥] 60PM [◦] 50.6 46.8 54.1 45.2 50.8 [≥] 45PSRR [dB] -84.9 -78.8 -87.2 -86.4 -84.3 [≤] -70VARGMP [%] 0.89 1.60 0.17 1.67 1.20 [≤] 4VARGMN [%] 0.92 1.60 0.47 2.23 1.38 [≤] 4CMRR [dB] -91.2 -97.2 -74.1 -97.9 -92.2 [≤] -70SLWUP [V/µs] 82.9 83.4 66.5 85.0 82.2 [≥] 5SLWDOWN [V/µs] 73.5 77.4 68.2 73.6 71.9 [≥] 5VOH [mV] 79.3 70.0 94.2 65.8 72.4 [≤] 100VOL [mV] 18.4 11.3 92.5 2.8 10.2 [≤] 100VIH [V] 3.78 4.09 3.42 4.15 3.76 [≥] 3.3VIL [V] -0.25 -0.33 -0.13 -0.35 -0.38 [≤] 0.0
66
5.1.2 Post-Optimization analysis and Conclusions
The system build give to the designer a verifiability and freedom by using the post-optimization
analysis. This feature speed up the process of optimization, overpassing non-essential simulations to
the desired performance, adding a more complete characterization to the circuit.
The idea is to choose a smaller list of tests and verifications to be perform with AIDA optimizer.
The compute power needed will be reduce and hence the number of generations increase faster,
given a more diverse solutions to test.
The possibility to preform a more stringent simulations with more corners process, having the abil-
ity to identify the critical ones. When a specific corner does not meet the constrain, a new optimization
can be started with the objective of reaching the constrain. With this feature it is possible to speed
up the process of optimization, overpassing non-essential simulations to the desired performance,
adding a more complete characterization to the circuit.
The validation of the solution is reach, showing that the portability across technologies were easy
and fast. Three different topologies were chosen to verify the knowledge transferability inside the
same class of circuit. The topologies are NimaShahpari, Yanlu and the CurrentFlow. In addition,
two technologies (XFAB and ATMEL) were also tested to validate the portability of each topology in
different technologies.
67
68
6Conclusions and Future Work
6.1 Conclusion
The increasing complexity in systems-on-chip demands a well defined structures and reliable pro-
cesses. Therefore, an automated process is desired to have a consistent and higher productivity.
However, a drawback is imposed by the analog world, due to a more disperse design rules. Several
strategies have been used to solve this problem.
In this work it is presented a new tool to ease automate analog circuit design and design reuse. It
was used an existent genetic algorithm optimization-based method (AIDA) with a new structure layer.
The new structure layer contains a generic cell library and a circuit class database to facilitate the
migration of different technologies and topologies. Fulfilling the goal of reducing the productivity gap
between digital and analog world.
One of the advantage of the structure layer, that is specifically related to the new generic cell
library, is the ability to be independent from different technologies. The creation of this generic cell
library gave a more versatility, convenient and portable solution to the designer by using a familiarly
environment as SPICE netlist level. However, as is stands now, it can only be applied at a schematic
level and not at the layout level.
In order to validate the generic cell library two distinct technologies were used. One of them
was the foundry XFAB and the other one the ATMEL. A mapping file was applied, which link each
technology to the developed generic cell library. It is important to refer, that the generic cell library
has a collection of 10 initial devices which can be increased by the designer. In addition, each device
69
can be associated to a specific symbol, that can be used on a CADENCE environment.
The structure layer has a second advantage - topology independence. This concept is a crucial
step to the IP reuse. The transfer knowledge through different topologies can be accomplished by
reusing an existent database of simulation files. The simulation file is a testbench, that is topology
independent. Each database of testbench refers to a specific circuit class. In this project it was create
a database of testbenchs for an operational amplifier with rail-to-rail input and output - R2ROpAmp.
There is a constrain on this structure. The number of pins and its names are restricted to description
of the circuit in the testbench. So the designer needs to have an extra attention when defining the
pins and its names for the specific topology.
The proposed solution is not complete without the AIDA-C framework, so the new developed struc-
ture layer needs to merge with AIDA-C. The proposed solution receives from the designer, a netlist
circuit and a configuration file. The netlist circuit can be generated using the CADENCE environment.
In the configuration file, the designer will indicate the target technology, the circuit class, the directory
of the circuit netlist file and the transistors measures needed.
The templates for AIDA-C will be automatic generated by a building script that follows the rules
given by the configuration file, making this proposed solution user-friendly and automated. Each
project needs to have, in advance, all the specifications for the testbenches. They can be extended
and/or modified by the designer, making the system more flexible. This is easily achieved because
the building script recreates and organizes all the known files in a familiar environment. Thus, the
designer can adjust his needs to different projects.
The validation of the solution is the final and fundamental step in this thesis. Three different
topologies were chosen to verify the knowledge transferability inside the same class of circuit. The
topologies are NimaShahpari, Yanlu and the CurrentFlow. In addition, two technologies (XFAB and
ATMEL) were also tested to validate the portability of each topology in different technologies. The re-
sults shows that the portability across technologies were easy and fast. In addition, post optimization
analyses are also performed to a specific topology. With this feature it is possible to speed up the
process of optimization, overpassing non-essential simulations to the desired performance, adding a
more complete characterization to the circuit.
Finally, in this work it was showed the advantages of using this proposed solution- a genetic
optimization-based method merged with the new technology and topology abstraction. This solution
allows the designer to develop easily a technology/topology-independent system, which can be exe-
cuted in multiple design. Based in our knowledge we believe that this approach is the most suitable
to reduce the productivity gap problem in analog circuit design.
70
6.2 Future work
The proposed solution in this thesis showed a good results in overcoming the productivity gap
between analog and digital world. However, the results only apply to a limit small circuit class, op-
erational amplifier. Therefore, to improve the proposed solution, further work is required to create a
robust and extensive class database, adding more circuit classes. Furthermore, the simulations analy-
ses only were applied to typical and corners processes in the optimization process, then parametrized
testbenches and future developments on AIDA framework could help to more complete analysis, for
example. The random offset, a performance characteristic on operational amplifier, are presently
done in a post-optimization analysis, using a Monte Carlo analysis.
Layout technology independence is a more complex process, than the netlist level perform in this
thesis. So, with the use of the AIDA-L, a module from AIDA framework that generates the complete
layout for sized circuits, in order to create a generic cell library integrating layout level to reach a full
technology independence database of devices.
71
72
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ACurrent Flow Results
A-1
The table A.1 presented the best result of each technology to be easily compare.
Table A.1: Values of the parameters for the circuit CurrentFLow with the two techs.
AT77K XH035
Parameter Typical C[0] C[1] C[2] C[3] Typical C[0] C[1] C[2] C[3] Seek
IDD [mA] 2.32 2.39 2.30 2.36 2.38 1.55 1.57 1.48 1.51 1.60
GDC [dB] 114.4 102.7 120.5 103.9 121.1 95.3 89.7 91.5 87.4 97.5 [≥] 70
GBW [MHz] 72.0 95.5 59.5 99.8 96.2 76.5 88.1 61.2 89.3 77.6 [≥] 60
PM [◦] 73.9 73.2 61.7 56.9 73.1 71.5 70.2 58.6 54.3 67.6 [≥] 50
PSRR [dB] -77.6 -65.0 -84.4 -66.2 -83.4 -77.4 -69.3 -72.5 -64.2 [≤] -70
VARGMP [%] 3.69 9.01 9.35 6.20 8.37 3.78 8.54 9.21 3.13 7.57 [≤] 4
VARGMN [%] 2.65 5.71 6.35 2.43 11.54 3.01 5.43 6.43 3.11 7.4 [≤] 4
CMRR [dB] -111.0 -94.71 -105.3 -100.6 -107.3 -95.1 -85.1 -99.2 -100.2 -102.2 [≤] -70
SLWUP [V/µs] 5.60 6.14 5.31 5.22 5.77 6.3 7.1 5.4 5.32 5.67 [≥] 5
SLWDOWN [V/µs] 5.71 6.25 4.73 5.49 5.30 5.9 6.2 4.9 5.3 5.21 [≥] 5
VOH [mV] 19.49 63.15 28.10 63.49 19.88 31.54 57.21 40.38 31.54 ?? [≤] 100
VOL [mV] 7.32 9.97 23.72 8.68 1.81 8.41 10.2 17.2 7.25 4.23 [≤] 100
VIH [V] 3.93 4.24 3.59 4.38 3.82 4.02 4.12 3.81 4.17 3.67 [≥] 3.3
VIL [V] -0.71 -0.87 -0.48 -0.84 -0.97 -0.81 -0.74 -0.48 -0.85 -0.47 [≤] 0.0
A-2