Useful Design Guide Useful Design Guide To To

Make the PLDMake the PLD

Xilinx FPGA Gate Count Standardized on Logic Cell as unit of measure

Maximum capacity = number of logic cells

Usable capacity = logic cells x utilization

ASIC "gate" estimate = 8-12 gates / cell

Example: XC4062XL = 4992 logic cells = 62,000 gates

Result: Simplicity, easy Xilinx FPGA capacity comparisons

4-input LUT FF

4 8

First Order Size Estimate

Count I/Os required Select FPGA with next higher number of bonded IOBs

Count flip-flops required Select FPGA with next smaller number of CLBs Capability of using two flip-flops in one CLB, or flip-flops in IOBs,

may balance with combinatorial CLBs XC4000 allows higher utilization than XC3000

Device may be determined by special resources Decoder width Busses Structured logic fitting in one column (especially carry)

Consider Architecture

Use dedicated logic functions

Limit clocks

Abundant flip-flops Also RAM

AND gate options (e.g., comparator) Lookup tables Edge decoders Wired-AND of three-state buffers Carry logic Writable RAM

CLB Lookup Table

Functions of 4 inputs are best

Xilinx FPGAs are built from lookup tables

A lookup table can implement any function of its 4 inputs

Similar to addressing ROM

Limit is on inputs, not complexity Reducing inputs/function (fan-in) to fit CLBs improves density

and speed

Inverters are free

Why Use to Hierarchy

Adds structure to design

Eases debug

Users can build libraries of common functions

Allows each design portion to be entered by most efficient method

Improves incremental design

Allows for floorplanning

Provides for team design

Hierarchy Guidelines

No limit to number of levels Recommend placing all I/O pads on top level

Create macros for common functions Do not save user-defined macros in vendor-supplied library Future software updates may overwrite the library

Do not leave macro inputs floating Run logic simulation before place and route to check overall

functionality

Locking I/O Pins

Avoid it until the last possible iteration Or until design is 75-80% complete & timing

requirements met More flexibility on board than inside FPGA Then re-align I/Os in logical pattern with minimal

movement

Specify edge locations only to guide layout If schematic is entered, let place & route choose I/O

locations Useful for partial designs or incremental design

Use Legal and Readable Names

Allowable characters Alphanumerics A - Z, a - z, 0 - 9 Underline _ Dollar sign $ Dash - Angle brackets (reserved for buses) <> Slash / (reserved for hierarchy)

Names must contain at least one non-digit

Avoid using names that correspond to device resources CLB row/column locations in XC3000: AA, AB, etc. IOB pin locations: P1, P2, etc.

Synchronous Design

Be careful not to glitch a clock signal

Be careful not to glitch an asynchronous set or reset

The FF in fast FPGAs can respond to very narrow “glitch” pulses

An easy rule to follow is “Never source a clock, asynchronous set or asynchronous reset signal from combinatorial logic”

Glitches Delays through CLB are balanced for all inputs

Lookup table is a multiplexer built from transfer gates Logic inputs are select lines Non-overlapping decoder cannot glitch

If multiple inputs change, make sure possible intermediate codes do not cause problems

Synchronous designs are fundamentally immune to glitches except on clocks and reset direct nets

0-->1---1

1----1->0

0-->1-->0CLRD

Q

Avoid Gated Clock and Reset

Move gating to non-clock pin to prevent glitch from affecting logic

Or separate input signal changes by at least a CLB delay to minimize the likelihood of a glitch

D QCarry

Q0Q1Q2

3-Bit Counter

D QCarry-1

Q0Q1Q2

3-Bit Counter

CLB Delay

Use Clock Enables

Use clock enable when using most of or all logic inputs

Not recommended to gate clock signal directly

Use muxed data to allow multiple clock enables in a CLB

Required even for opposite edges of same signal

Some macros use logic for clock enable while others use the CE pin

Make sure CE, if unused, is always connected to VCC

D Q

CE

D Q

CE

FDxE

D Q

R

PINPUT

CLOCK

D Q

R

P

D Q

R

P

12.13.6

3.33.6

3.1

3.0

This shift register will not work because of clock skew!

Clock Skew

Use global buffers for clocks and there are no clock skew concerns (guaranteed to meet FF hold times)

Asynchronous Logic

Analyze carefully

Check for potential problems with faster parts

Try fastest speed grade available

Try low temperature and high VCC to speed up chip If failure is at hi temp and/or lo VCC, improve delays If failure is at lo temp and/or hi VCC, check for asynchronous

logic and clock skew issues

Safely Synchronising Design for Asynchronous Inputs

D Q

RAsync input

System clock

Sync input

Device periphery

D Q D Q

Ensures no metastability

D Q

tCO tNET tPD tNET tPD tNET tSU

CLB CLB CLB CLB

Performance Estimation

Use block delays as estimate of net delays

Use desired clock frequency to determine allowed CLB depth Compare to functional requirements and modify design to meet

performance needs

Example for 50 MHz clock frequency in XC4000XL-3: Clock period 20 ns One level - 8 ns (tCO + tNET + tSU) Delay allowance 12 ns Each added level div 6 ns (tPD + tNET) Added levels of logic allowed 2 CLBs

Pipeline Logic

Registers are “FREE” in FPGAs

Increases system through put

D

CE

Q

R

PD

CE

Q

R

P

D

CE

Q

R

PD

CE

Q

R

P

25MHz

50MHzD

CE

Q

R

P

State Machines Three Types

Binary: The States have a counter like progression S1 = 001, S2=010, S3=011, S4=100, etc…

Enumerated: The States have assigned values S1=100, S2=110, S3=101, S4 = 111, etc…

One Hot: Only 1 register is active for each state S1=00000001, S2=00000010, S3=00000100, etc…

Binary and Enumerated have lots of feedback to make the present state to next state jump. This is good for CPLDs like the XC9500.

State Machines

Use One Hot Encoding for larger machines

Binary or Enumerated Encoding okay for smaller state machines

Remember the 4 input LUT! State Machines can have wide fan-in and lots of feed back

For One Hot limit number of input states to 4 for highest speed.

Input 1

Input 3

State 4

State 6

State 19

1 LUT

StateA

StateA1

StateA2

StateB

cond1

StateB

cond1 cond1

State Machine Design Tips

Split complex states

Need to minimize number of inputs, not number of flip-flops, in FPGAs

Complex states may be improved by breaking up into additional simpler states

D Qfn1 D Qfn1

D Qfn1

Duplicate Registers

High fanout nets (>16 loads) are hard to route and slow

Consider duplicating source in schematic/HDL to improve routing or speed

The M1 tools don’t do this automatically

Name duplicate registers _a, _b, _c, NOT 1,2,3. M1 Mapping will be more effective.

O1

I1

O1

I1N1

N1 must go to two places, so O1 may require a second level of logic Duplicating first gate allows N1A to

always be collapsed inside a single lookup table

N1A

N1B

Duplicate Combinatorial Logic The M1 tools will duplicate combinatorial logic automatically if

Logic Replication is selected

Collapsing logic into CLBs lowers the number of levels

The gates you use will determine mapping Nets with a fanout >1 may be outside a CLB Pay attention to mapping of speed-critical paths

LAYOUT: Pin Selection I

Data Flow

LAYOUT: Pin Selection II

Control Pins

Control Pins

LAYOUT: Pin Selection III

• Remember the Carry Chain Flow Direction if your design uses arithmetic functions

For EX/XL/XV Spartan

LSB I/O

MSB I/O

MSB or LSB I/O

LSB or MSB I/O

LAYOUT: Pin Selection IV

Stay off the FPGA Control Pins DOUT, M0, M1, M2, JTAG

Wire-and DONE signals to determine when all FPGAs are finished programming.

Don’t join the INIT signal for all FPGAs in the same Daisy Chain

Monitor INIT for each FPGA for CRC check failure

LAYOUT: CCLK CCLK is the download clock.

Many boards contain two or more FPGAs in a daisy chain configuration. The Cclk is taken from one FPGA to the other.

CCLK has a very fast slew rate driver and that is can cause a lot of reflections on the clock line.

Inside the FPGA the CCLK is first routed to the CCLK pin and then taken back inside to the configuration circuit.

Treat the Cclk line as a transmission line. Terminate it properly.

Ideas : active termination via two Shottky diodes, or a slow slew rate driver mounted immediately after the first device.

Use Tick marksTo help with pinidentification onyour board

LAYOUT: Debug Tips

XC4KFPGA

XC17XXPROM

VCCGND

CCLKDIN

PROGDONE

INIT

RDRT

M0

M1

M2

VCC

LAYOUT: Debug Tips Use the Xilinx Download Cable for debug

Use the FPGA Readback, RD & RT

CPLDCPLD

<5K gates<5K gates

Simple tools

Simple tools

Low cost (SW + IC)

Low cost (SW + IC)

Equations

Equations

Schematics

Schematics

Tpd, ISPTpd, ISP

High Volume FPGAs

High Volume FPGAs

Higher integration

Higher integration

5K–20K gates

5K–20K gates

3rd party tools

3rd party tools

Equations

Equations

Schematics

Schematics

Verilog/VHDL

Verilog/VHDL

High End FPGAs

High End FPGAs

>20K gates

>20K gates

ASIC-like flow

ASIC-like flow

System level tools

System level tools

Verilog/VHDL

Verilog/VHDL

Schematics

Schematics

Xilinx Product Strategy

Serve the ASIC Designer

Serve the PAL Designer

PALPAL

ASICASIC

XC9500

XC4000E

XC5200

XC4000EX/XL/XV

Integrated Software Migration

Integrated Software Migration

FPGA Technology Roadmap

1995 1997 1998 1999

Year

XC4000ELargest DeviceXC402545,000 sys. gates0.5m5 Volt

XC4000EXLargest DeviceXC4036EX65,000 sys. gates0.5m5 Volt30% faster than E

XC4000XLLargest Device180,000 sys. gatesXC4085XL0.35m3.3 Volt30% faster than EX

XC4000XVLargest Device500,000 sys. gatesXC40250XV0.25m2.5 Volt30% Faster than XL

1996

Virtex 1 Million+ sys. gatesSystem Solution0.25/0.182.5/1.8 Volt

Den

sity

/Pef

orm

ance

2.0M gatesin the year

2001

2.0M gatesin the year

2001

4000 Series X = EX/XL/XV

How to keep naming straight

Markets the X architecture

eXtra routing eXtra density

eXtra performance

EXXLXV

5 Volts

3.3 Volts2.5 Volts

X Architecture

X Architecture

XC4000X Family Features

• Select-RAM (Synchronous Single and Dual-Port RAM)

• Pin Locking Flexibility with VersaRing

• 100% PCI Compliance

• LogiCore Modules (PCI, DSP and USB)

• Strong Footprint compatibility

• High density, up to 125,000 Gate (250,000 System Gate)

• Internal Three-state Buffers

• JTAG Boundary Scan

• System performance to 100 MHz (-0.9)– 1/ (T setup + Tclk-out)

XC4000X Series High DensityXC4000EX XC4000XL XC4000XV

Family Family Family

Logic Cells 2,432 - 3,078 152 - 7,448 10,982 - 20060

Max Logic Gates 28,000 - 36,000 2,000 - 85,000 125,000 - 250,000

Typ Gate Range 50,000 - 65,000 5,000 - 180,000 250,000 - 500,000 (Logic + Select-RAM)

I/O 256 - 288 112 - 448 288 - 544

Number of Devices 2 11 5

Power Supply 5 V 3.3 V 3.3 V + 2.5 V

I/O Interface 5 V 5 V / 3.3 V 5 V / 3.3 V

Xilinx FPGA ComparisonXC5200 XC4000E XC4000X SPARTAN

Function Generators/CLB 4 3 3 3

Flip-flops/CLB 4 2 2 2

Global Nets 4 8 20 8

Extended Routing No No Yes No

Global Three-State Control Yes Yes Yes Yes

Wide Decode Capability Cascade Dedicated Yes No

Carry Logic Yes Yes Yes Yes

On-Chip Memory No Yes Yes Yes

Wired-AND Function No Yes Yes No

Internal Three-State Buffers Yes Yes Yes Yes

Output Slew Rate Control Yes Yes Yes Yes

Boundary Scan Logic Yes Yes Yes Yes

Output Drive (Sink) 8 mA 12 mA 12 mA 12 mA

Power-Down Option No No No No

4002XL 4005XL 4010XL 4013XL 4020XL 4028XL 4036XL 4044XL 4052XL 4062XL 4085XL 40125XV

PC84 PC84 PC84

PQ100 PQ100 PQ100

VQ100 VQ100

TQ144 TQ144 HT144 HT144

PQ160 PQ160 PQ160 PQ160 HQ160 HQ160 HQ160

TQ176 TQ176 HT176 HT176

PQ208 PQ208 PQ208 PQ208 HQ208 HQ208 HQ208

PQ240 PQ240 HQ240 HQ240 HQ240 HQ240 HQ240

HQ304 HQ304 HQ304 HQ304 HQ304

BG256 BG256 BG256 BG256

BG352 BG352 BG352

BG432 BG432 BG432 BG432

PG411 PG411 PG411

BG560 BG560 BG560

PG559 PG559

XC4000XL Footprint and Packaging

Future extensions

Density: The Facts

Xilinx Device Competing ProductMax Max

Max RAM Logic RAM MaxDevice I/O Bits Cells Bits I/O DeviceXC4000 Series Altera FLEX 10KXC40125XV 544 148K 10,982XC4085XL 448 100K 7,448

6,656 32K 470 EPF10K130XC4062XL 384 74K 5,472

4,992 25K 406 EPF10K100XC4052XL 352 62K 4,598XC4044XL 320 51K 3,800

3,774 18K 358 EPF10K70XC4036EX 288 42K 3,078

2,880 20K 310 EPF10K50XC4028EX 256 33K 2,432XC4025E 256 33K 2,432

2,304 16K 278 EPF10K40XC4020E 224 25K 1,862

1,728 12K 246 EPF10K30

XC4000 Series FPGA Architecture

XC4000X Interconnect Hierarchy

Abundant high-speed, segmented interconnect Optimized resources for high-density designs Delivers fast compilation times and ensures high first-pass completion rates

Routing Resource XC4000EX XC4000E

V/H Quad Line 12/12 0/0V/H Long Line 10/6 6/6V/H Direct Connects 2/2 0/0V/H Single Line 8/6 8/6V/H Double Line 4/4 4/4Vertical Global Lines 8 4

Global Low Skew Buffers (BUFGLS)connect to any or all clock inputs.

8 7

3 4

1

2

6

5

8 7

3 4

1

2

6

5

Global Early Buffers (BUFGE)#8 connects to CLB and IOB clockinputs in its local quadrant. BUFGE #3,#4, and #7 are similar.

1

2

4

3

FastCLK Buffer (BUFFCLK) #1connects to half the IOB clock inputsalong the same edge. FCLK2, FCLK3,and FCLK4 are similar. FastCLKbuffers only drive IOB clocks along theleft and right device edges.

XC4000EX Clocking Options

Global Low-Skew

Buffers

FastCLKBuffers

Global Early

BuffersIdeal for

“system clocks”or critical

control signals

High speed clockfor localized

macros or cells

Optimized for high-speed I/O

6ns setup6ns pin to pin

6ns clock to out

XC4000X VersaRingTM

0.35 FPGA, 5 Volt Compatible

accepts 5 volt inputs

drives standard TTL levels

totally compatible in 5 volt environment

Any 5 V

device

XC4000XLFPGA0.35

3.3V Core3.3V I/O

5V3.3v

5V

3.3V

Meets TTLLevels

30% faster than 0.5 70% power reduction over 0.5 at same speed and density

3.3 volt power supply, I/Os 5 volt compatible

XC4000XL

Density (Logic Cells)

XC4000E

XC4000EX

Price($)

7,500

Price reductionfrom 5 volt devices

400

XC4085XL

High Performance 0.35u FPGAs3.3 volts in 1997

5,000 85,000 Density (Gates)

XC4000XL Delivers High Performance at 3.3 V

80 MHz internal speed (3-4 LUT levels)

66 MHz internal speed (4-5 LUT levels)

I/O performance XC4013XL XC4036XL

Tco (output register) 6.4 ns 6.4 ns Tsu (input register) 4.5 ns 5.4 ns Th (input register) 0 ns 0 ns Max I/O frequency 92 MHz 85 MHz

0%5%

10%

15%20%25%

30%35%40%

45%50%

< 50KGates

50K to100K

> 100KGates

Gate Array Densities

FPGA Capability

FPGAs Overlap Gate Array Design Starts

Source: Dataquest 1996 Design Starts

0%5%

10%15%20%25%30%35%40%45%50%

> 0

.6m

icro

n

0.5

- 0.

6m

icro

n

< 0

.4m

icro

n

Asic Line Widths

FPGA Performance Level

XC4000XL Performance Overlaps with Gate Arrays

Process Geometry Typ GA performance*>1.0mm 33Mhz0.8mm 50Mhz

0.65mm 66Mhz0.5mm 100Mhz

0.35mm 150Mhz

* Design Dependent, source:Major GA supplier

Gate Array performance advantage shrinking annually

XC4000XL

Equivalent

XC4000XL-2

XC4000XL-1

XC4000XL-09

* 25-30% of CLBs as RAM

* 20-25% of CLBs as RAM

4002XL 4005XL 4010XL 4013XL 4020XL 4028XL 4036XL

Logic Cells 152 466 950 1,368 1,862 2,432 3,078

Typ Gate Range* 2-5K 3 - 9K 7-20K 10-30K 13-40K 18-50K 22-65K(Logic + Select-RAM)

Max. RAM bits 2K 6K 13K 18K 25K 33K 42K

I/O 64 112 160 192 224 256 288Initial Packages PQ160 PQ160 PQ160 PQ160 PQ160 PQ160

TQ176 TQ176 HT176 HT176PQ208 PQ208 PQ208 HQ208 HQ208 HQ208

HQ240 HQ240 HQ240 HQ240BG256 BG256 BG256 BG256

BG352 BG352 BG432

4044XL 4052XL 4062XL 4085XL

Logic Cells 3,800 4,598 5,472 7,448

Typ Gate Range* 27-80K 33-100K 40-130K 55-180K(Logic + Select-RAM)

Max. RAM bits 51K 62K 74K 100K(no Logic)

I/O 320 352 384 448

HQ160

HQ208

Initial packages HQ240 HQ240 HQ240BG352BG432 BG432 BG432

BG560 BG560 BG560

XC4000XL Family

XC4000XL Success Story

Big Datacom company

ATM Switch Application

Division was 100% Altera for PLDs

Board with 10K50 failed to meet 25MHZ after one month of effort (including Altera Engineers). XC4028XL-1 ran at 30MHZ with no problem.

This socket allowed us to win ALL FPGAs on the board. New ATM platform is 95% Xilinx.

XC4000XL Success Story

Subsidiary of major networking company

Design included 12x14 multiplier and high-speed pipelined RAM, target speed 100MHZ

Began with Altera 10K100 - Simulation said design would work at 74MHz

Altera part began “melting the printed circuit board” at 60MHz

XC4000XL-1 works at 91MHZ - will hit 100MHZ target with -09 speed

World’s...First 0.25 micron FPGA,First 250,000+ Gate FPGA,First 2.5 Volt FPGA,First 25 million transistor logic device

Technology Leadership: XC4000XV Family

Advanced process technology 5 layer metal 0.25u CMOS stacked vias CMP (chemical mechanical polishing)

XC4000XV+ includes extra routing 100XV, 150XV, 200XV, 250XV eight tracks of octal lines added per CLB minimizes routing congestion

World’s Most Advanced Logic Devices

Tra

nsi

sto

r co

un

t (m

illi

on

s)

7.5

25

50

4Q97 1Q98 2Q98

Intel Pentium II

XC40125XV

XC40150XV

XC40200XV

XC40250XV

XC40100XV

Xilinx FPGA Density LeadershipXC4000XV Production Roadmap

0

5,000

10,000

15,000

20,000

25,000

Lo

gic

Ce

lls

10K130 XC4085XL XC40125XV XC40150XV 10K250 XC40200XV XC40250XV

Jan ‘98

Q2 ‘98

Q1 ‘98

Q3 ‘98

NOW NOW

Q1 ‘98

Altera Altera

0.25 FPGA, 5 Volt Compatible

accepts 5 volt inputs

drives standard TTL levels

totally compatible in 5 volt environment

Separate I/O & Core Supplies

Any 5V

device

XC4000XVFPGA0.25

2.5V Core3.3V I/O

Any 3.3V

device

5V3.3V2.5V

5V

3.3V 3.3V

3.3V

I/OSupply

CoreSupply

Meets TTLLevels

30% faster than 0.35 70% power reduction over 0.35 at same speed and density

2.5 volt power supply, I/Os 5 volt compatible

High Performance 0.25 FPGAs1997/1998

XC4000XV

Logic Cells

Price($)

32,00011,000

XC40125XV

Generation 3 Architecture

Up to 400klogic gates

400K125K Gates

The XC4000XV - 0.25 µm Fast

Performance summary XC40125XV Internal operation (3-4 LUT levels) 100 MHz Tco (output register) 7.5 ns Tsu (input register) 5.0 ns Max I/O frequency 80 MHz

XC40125XV: 10,982 logic cells (265,000 system gates)

Combining VERY high densityAND

VERY high performance

4KXV Addresses 90% ASIC Starts by Speed

Source: Dataquest and Xilinx 1997

0%

5%

10%

15%

20%

25%

30%

0-20 40-60 80-100 120-140 160-180

Average Clock Speed (MHz)

% of 1997 GateArray Starts

Adressed by FPGAs

Xilinx: The Density Leader

0

2,000

4,000

6,000

8,000

10,000

12,000

XilinxXC40125XV

Altera 10K130V Lucent 2T40A

Lo

gic

cel

ls 40%bigger]

XC4000XV Family

Device LogicCells

RAMbits

Typical GateRange

(logic + RAM)

Availability

XC40125XV 10,982 147,968 80,000 – 265,000 Now

XC40150XV 12,312 165,888 100,000 – 300,000 1Q98

XC40200XV 16,758 225,792 130,000 – 400,000 2Q98

XC40250XV 20,102 270,848 160,000 – 500,000 mid-98

Foundation FPGA Express

Foundation Express Features

Express Technology Optimizes the design for Xilinx Architectures Optimized arithmetic functions Automatic Global Signal Mapping Automatic I/O Pad Mapping Resource Sharing Hierarchy Control Source Code Compatible With Synopsys Design

Compiler and FPGA Compiler Verilog (IEEE 1364) and VHDL (IEEE 1076-1987)

Support Easy, graphical constraint entry

Xilinx-Express Design Flow

.VEI.VHI

.UCF Reports

DSP COREGen & LogiBLOX

Module Generator

XNF.NGO

HDL Editor

State DiagramEditor

VHDLVerilog

.V.VHD

Foundation Design Entry Tools

Gate LevelSimulator

SchematicCapture

EDIFXNF

TimingRequirements

VHDLVerilog

Express

EDIF/XNF .XNF

BITJDEC

SDFVHDL

Verilog

Reports

EDIF

Xilinx Implementation Tools

HDL

SIMULATION

VHDLVerilog

Behavioral Simulation Models

Express Input and Output Input files may be VHDL or Verilog format

Mixed Verilog/VHDL modules are accepted Schematics may also be used, but should not be

input into Express Schematic files in XNF or EDIF format will be

merged into the design in Xilinx Design Manager

Output netlists are in XNF format

Timing Specifications may be specified in Express

Timing Specifications are not used during Synthesis

Timing Specifications can be included in the output netlist

Reports

TimingRequirements

VHDLVerilog

Express

.XNF

Express Design Process (1)

2. Implement - Create generic logic design (Elaborate)

1. Analyze - Syntax check

2. Enter constraints and optionsFoundationExpress

Layout with Xilinx Design Manager

5. Evaluate Results

4. Synthesize -Optimize the design for specific device

Create a Project

Invoke Express with Start -> Programs -> Xilinx Foundation Series -> Foundation Express

• The Main Window Appears

Analyze the Design (1) “Analyze” checks the HDL code for syntax errors

Also creates internal files

Files are automatically analyzed when selected for a project

Do not select XNF or EDIF files

Will be merged into the design by Design Manager

Synthesis -> Identify Sources

Analyze the Design (2) As the design blocks are analyzed, status is displayed:

No Errors or Warnings Out of Date

Warnings

Errors

In this example, all blocks were analyzed successfully

Main Window

Implement the Design Express Implementation maps the HDL code to standard

logic, creating a generic netlist.

At this stage, the design has not been optimized

• To implement a design, select only the top level block, and then select the Implement icon

Main Window

Check for Errors and Warnings

After implementation is complete, the chip symbol plus status is displayed

View errors, warnings and messages

Right click inside window to save information to a text file

Define Clock Period

Enter Period, Rise, and Fall Time Select Clock entry -> Define

Synthesis -> Edit Constraints -> Clocks -> Define

Synthesis -> Edit Constraints -> Clocks

Define Global Synchronous Delays (1) The clock period creates 3 types of global constraints:

All input ports to sequential Elements (1) Setup of flip-flop or latch is included

Sequential Element to all output ports (2) Flip-Flop Clock to Q delay is included

Sequential Element to Sequential Element (3)

All constraints have the same value by default

3

Clock period

logic

logic logicD Q1

D Q

2

Define Global Synchronous Delays (2)

Use the Paths form to edit delays assigned by the clock period Default delays from the clock period are shown here

Synthesis -> Edit Constraints -> Paths form

3

Clock period

logic

logic logicD Q1

D Q

2

Define Individual Synchronous Delays

Default delay from Clock specification is used in the Paths form

Individual, or path specific delays can be defined on the Ports form Port delays over-write the global delays from the Paths form

Input delay, shown here, arrives 20 ns before the rising edge of the clock.

Synthesis -> Edit Constraints -> Ports

Define Key Port Features (1) Global Buffer defines the type of Clock Distribution network - Use BUFG

for most applications(default)

Resistance specifies use of pullup or pulldown resistor on unused pads Reduces power consumption and noise

Use IO Reg allows use of sequential elements within IO Blocks to minimize Input or Output delay (default)

Dependent on device type

Synthesis -> Edit Constraints -> Ports

Define Key Port Features (2)

Slew Rate can be fast or slow Fast slew rate can cut IO delay up to 50%, but causes more noise Default is slow

Pad Location is used to specify pin number of the IO pad

Synthesis -> Edit Constraints -> Ports

Control the Hierarchy (1) Eliminate (default) or save hierarchical boundaries

Flat designs yield best results because more merging and sharing of boolean logic occurs

However, small blocks are easier to debug Easier to match source HDL code to synthesized design

Synthesis goals (Speed or Area) and Effort level can be defined for each module

Synthesis -> Edit Constraints -> Modules (implemented design)

Control the Hierarchy (2) Hierarchical blocks may be eliminated or saved

By default, hierarchical boundaries are eliminated

Flat designs yield best results because more merging and sharing of boolean logic occurs

Synthesis goals (speed or Area) and Effort level are defined for each module

Synthesis -> Edit Constraints -> Modules (implemented design)

Optimize the Design

Optimization minimizes the design for speed or area

Select the implementation, and then select the Optimize icon

After Optimization, check for errors and warnings again

Main Window

View Results

Select File -> Project Report to generate a report

• Report file contains:– Files and libraries used – Settings for Synthesis – Chip type and speed grade– Estimated Timing– Warning: Circuit timing estimates tend to be optimistic. Run timing analysis after routing for most accurate timing analysis.

Report.txt file

Verify Results (1) After Optimization, open Synthesis -> Edit Constraints to

verify that correct constraints were specified

Results are based on estimated routing delays

Synthesis -> Edit Constraints -> Paths (for an optimized design)

Verify Results (2) Review size of the design

Resource use is displayed for each hierarchical block Resources used per hierarchical block Black Box instantiations cannot be analyzed by Express

Synthesis -> Edit Constraints -> Modules (Optimized Design)

Verify Results (3)

View Details for each block Left click within Area slot -->

Arrow -> Details

Type and number of each Xilinx component are used.

BUFG - Primary or Secondary Buffer BUFGS - Secondary Buffer CY4* - Carry Logic Function DFF - CLB flip-flop FMAP, HMAP - F and H LUTS IBUF - IOB input buffer INFF - IOB flip-flop OBUF - IOB output buffer OSC4 - Internal Oscillator

Synthesis -> Edit Constraints -> Modules

Export Netlist Create the output netlist for use with the Xilinx Design Manager

(Xilinx Implementation Tools) Output File format is XNF

Select the optimized design, then select Synthesis -> Export Netlist to create the file

XNF file format is used

• Enable Export Timing Specifications to include constraints in the output netlist

Synthesis -> Export Netlist