use of hierarchical design methodologies in global infrastructure of the power7+ processor

© 2013 IBM Corporation

Use of Hierarchical Design Methodologies in Global Infrastructure of the POWER7+ Processor

Brian Veraa ([email protected])

Ryan Nett ([email protected])

Ryan Kruse ([email protected])


Introduction

POWER7+ Microprocessor– 567mm2

– 2.1B devices at 4+GHz core frequency– Large global design team

Hierarchical implementation– Divide and Conquer

Certain global structures span hierarchy – Power– Clock– I/O

We will discuss unique PD challenges presented by these structures– Over/Under booking physical resource– Connectivity across hierarchy– Floorplanning around these structures


POWER7+ Chip Core + Cache

CoreLoad/Store Unit

Example of POWER7+ Hierarchy


Global Infrastructure (G.I.)

Implemented at top level of hierarchy– Clock Distribution– Power Distribution– I/O connections

Load/Store Unit example– First design team delivers LSU– Second design team implements clock distribution at top level– Third design team implements power gating at top level– Many G.I. components fall within physical perimeter of child

Challenge: Communicate physical design data across hierarchy

Load/Store Unit(great-grandchild of chip)

Power gating circuits

Clock buffers


Communicating PD data across hierarchy: Parent Covers

Parent CoverChild2

Parent

Child1

Parent cover represents G.I. content interacting with child

Feedback loop to resolve parent/child conflicts

Used by child for – Floorplanning– Routing– Checking

Multi use children get unioned parent cover

Generate new G.I. abstract

Parent resolves floorplan conflicts

Generate parent cover for child

Update child abstract to reflect inverse of

parent cover

Child feeds back change

proposals to G.I. owner

Parent runs G.I. child collision

checking

Child respects parent cover during floorplan and routing

Child runs LVS / DRC


Load/Store Unit (8 copies)

Load/Store Parent CoverChip level Power Gate circuits

POWER7+ Chip

Union 8 copies

Example of Parent Cover Assembly at Chip Level


Challenges with Hierachical Design

Over/Underbooking resource

Connectivity Across Hierarchy

Floorplanning around G.I. Content


Overbooking and Underbooking

To enable parallel design work, initial G.I. abstractions are based on estimates

– Accuracy of estimates improves over time

Overbooking– Cost is suboptimal utilization

Underbooking– Cost is late design change

Late changes to G.I. abstraction can drive floorplanning, routing, and timing efforts at a schedule sensitive time of the project

The POWER7+ chip team generated parent covers regularly throughout the design cycle to reflect higher quality G.I. component abstracts as their designs matured

Child2

Parent

Child1


Connectivity Across HierarchyPower connections to G.I.

Certain G.I. components need power connectivity to children– Clock buffers are connected into child power grid – Power gate circuit supplies power to children

• Power gate circuit inputs hidden from children

Chip

G.I. Component Child Unit

C4via

metalvia

metalvia

metalvia

metalvia

metalvia

metal

Power gate circuit

metalvia

viametal

viametal

viametal

viametal

viametal

viametal

viametal

viametal

viametal

Unit Circuits

Power Path through power gate circuits

Child Unit

Chip

G.I. Component Child Unit

Clock Buffer

Metal (power)via

viametal

viametal

viametal

viametal

viaMetal (power)

viametal

viametal

viametal

viametal

Unit Circuits

Power Path to clock circuits

via

viametal

viametal

viametal

viametal

Unit Circuits


Connectivity Across HierarchyChecking errors encountered in parent

Case 1: Child contacts V1/V2 pin– Problem: LVS short between

V1 and V2 at parent level– Solution: Represent V1/V2

union as blockage, not pins

Parent

Inst 1 of child

Inst 2 of child

GND

V1 V2Area where both V1 and V2 are present in the parent Short in parent if child connects to it!

Unioned shapes

GND exists in only 1 parent instance. Potential DRC or LVS open if child connects to it!

(x1,y1)

(x2,y2)

Case 2: Child contacts GND pin to complete a signal route

– Problem 1: LVS open at parent in Inst 2– Problem 2: DRC error generated at parent in

Inst 2 (min area or notch)– Solution: Don’t permit signal routes to contact

parent cover


Connectivity Across HierarchyFalse checking errors encountered in child

Parent Cover

V2V2 V1

V1

(A)

Child contains two power rails: V1, V2

G.I. content contains only V1

Pin V1 (A) is connected to V1 grid by layout of G.I. component

Child sees V1 (A) as an LVS open

Checking in parent context is LVS Clean

False opens are communicated to parent to refine parent cover


Floorplanning Around G.I. Content

G.I. circuits consumed a large amount of metal resource– Influenced child floorplanning and route planning.

• Congestion analysis – Floorplans were adjusted to minimize the number of flight-lines crossing a particular G.I.

component.– In other cases the G.I. was altered.

Consider grouping tightly coupled circuits on the same side of a G.I. component.

Load/Store Unit


Conclusion

POWER7+ relied on hierarchical methods to close a large design with a global design team– Concurrent design and schedule closure– Flat design of selected components to meet high performance needs

Management of Global Infrastructure components required:– Effective abstraction– Connectivity modeling across hierarchy– Careful floorplanning

Newer generations of processors are likely to demand more global power and clock management features

– More thorough G.I. planning and execution– Better hierarchical interaction management

Techniques and Tools developed by POWER7+ will continue to be leveraged in the future

use of hierarchical design methodologies in global infrastructure of the power7+ processor

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