upcoming technology challenges for ic manufacturing

Upcoming Technology Challenges for IC Manufacturing

Dr. Robert GuernseyDirector of Silicon Technology Strategy

Semiconductor Research and Development Center IBM Microelectronics

RWG CCNY030403.prz 3Apr03

IBM Microelectronics

RWG tcm030415.PRZ 15Apr03

Process Outlook Forum: April 15, 2003

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RWG tcm030415.PRZ 15Apr03Process Outlook Forum: Upcoming Technology Challenges for IC Manufacturing

Three Key Trends in the Worldwide Information Technology Industry

1) Big growth in affordable computing power.

2) Smart networks and almost-free communication.

3) Big growth in mobile data devices and connectivity.

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Semiconductor Technology: The Great Enabler

Continued exponential growth in circuit performance and density.Continued reduction in circuit power.SiGe transistors for very high frequency 350 GHz

Integration of CMOS, SiGe, and DRAM to enable System-On-Chip.Manufacturing on 300mm for increased productivity and reduced cost.

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CMOS Chip Structure

CMOS Transistors

Contact Studs

Copper Wires

Solder Bump or C4

Chip Wiring Insulation

Plastic Package

N P

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CMOS Circuit Performance Trends

1995 2000 2005 2010 2015Year

1

10

Rel

ativ

e Si

licon

Cap

abili

ty G

row

th

Bulk CMOS and aluminum Interconnect, Performance enhancement saturates due to device non-scalability, and interconnect delay

New Transistor Structures

Copper and Low K insulator reduce interconnect delay

SOI devices

Few can do

Many can do

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Oxide thickness is approaching a few atomic layerssilicon bulk field effect transistor (FET)

Fundamental Atomic Limit to Scaling

6



Semiconductor Business: Innovation Driven Industry

70's 80's 90's 00's 10's

Device DesignOptimized voltage scalingCMOS replaces BiCMOS in DP applications

StructureSTI, Planer InterconnectLithography Limited

Copper InterconnectSilicon on Insulator

New Materials and Device Structures

eDRAM in High Perf LogicAnalog / Mixed SignalMRAM

Memory SubsystemSystem on a Chip (SOC)

New Functional Integration

New Architecture / Circuit Concepts

CMOS Scaling, Lithography Driven

Low K, SiLKSiGe

Many can do. Few can do.

7



IBM Semiconductor Research & Development Center

Mission: Provide Leading Edge Cost Competitive Semiconductor Process Technology for Product Applications

ManufacturingSRDCResearch

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IBM Semiconductor Technologies

Most Advanced Lithography, New Materials, & ProcessesLithography

Early access to exposure toolsMask making expertiseResolution enhancement techniquesState of the art resist research

S Technologies Highest performance CMOS

technologyLowest active powerFuture eDRAM integration

SF Technologies Highest performance bulk devices

and interconnectsLow active/standby powerCompetitive density

Copper Metal GateLow k FinFET SOI Strained Si High k Gate Oxide

System-on-ChipeDRAM RF / analog PassivesASIC

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Silicon On Insulator

Enhanced and colorized SEM view of SOI device in cross-section with wiring.

Advantages over Bulk Si:20 to 30% performance increase

One-generation gain at same lithography

Lower power dissipationMinimal added cost (10%)No yield impact

SOI-based structures are key to scaling into sub-100nm generations.SOI is highly appropriate for ultra-low power 1V applications.SOI is the highest performance CMOS technology.

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Strained SiliconSSCMOS: SiGe Microstructure and Thermal Stability of Device Structures

Speeds up electron flow by 70%Improved chip performance 35%Compatible with SOI

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High-k Gate Dielectric and Strained Silicon

Relaxed SiGe

Graded SiGe Buffer

Si substrate

Strained SiChannel

HfO2 or SiO2

~1.

5 µm ~10 nm

PolyGate

poly gate spacer

Relaxed Si0.85Ge0.15

Strained Si channel

HfO2

poly gate spacer


Strained Si channel

HfO2Relaxed SiGe

Graded SiGe Buffer

Si substrate

Strained SiChannel

HfO2 or SiO2

~1.

5 µm ~10 nm

PolyGate

poly gate spacer


Strained Si channel

HfO2

poly gate spacer


Strained Si channel

HfO2Example of a strained Si FET with high-k gate dielectric

Achieve the high performance of strained silicon (30% enhancement) with the low leakage of thicker, high-k gate insulator (1000x lower leakage) for maximum performance with minimum standby power.

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IBM's First FinFET Hardware

First IBM FinFET. Fried et al, 2001 Device Research Conference

Ed Nowak

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Carbon Nanotube FET (1.4nm diameter)

Transconductance = 7 x10-7 A/VHole Mobility comparable to Si MOSFET at 60-100 cm2/VsContact resistance comparable to Si MOSFET

R. Isaac

Carbon Nanotube Voltage Inverter

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FSG

Lower-k

Low-k

Ultra Low-K

Decreasing Effective K

2000 20032002 2004 20062005 200820072001

On-Chip Wiring Technology Roadmap

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On-Chip Wiring Technology Example of IBM Back-End-Of-Line Stack with 8 Wiring Levels

VLM4V3M3V2M2V1M1CA

MC

VQ

LM

VJ2x pitch fatwire

2x pitch fatwire

4x pitch fatwire

MJ

MK

MQ

VK

4x pitch fatwire

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A "No-Fear" Device / Interconnect Migration Roadmap

Time

Perf

orm

ance

Bulk Silicon

Aluminum Wiring

Bulk SiliconCopper Wiring

SOICopper Wiring

Ultra Thin SOI

Copper Wiring/LoK

Ultra Thin SOIStrained Si

Cu/Lo(wer)KUltra Thin SOI

Strained SiHiK

Metal Gate

Cu/UltraLoK FD SOIStrained SiDG-FinFet

HiK Metal Gate

Air GAP BEOL

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220nm180nm

130nm90nm

65nm45nm

35nm

Technology Generation

0

0.5

1

1.5

2(a

t giv

en p

erfo

rman

ce)

Pow

er D

ensi

ty

Bulk

SOI

Strained-Si

Double Gate

Power density flat or decreasing by means of

Bulk SOI Strained Silicon Double Gate

Power Density Trend

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Optical Deep UV (248nm) Use through 180nm - 130nm Litho Generations

Optical Deep UV (193nm)Use through 130nm - 100nm Litho Generations

157nm Optical and/or Next Generation Litho: EUV, E-beam projection, ...

Use for <100nm Litho GenerationsSignificant investmentIndustry consensus required

Sustaining the Lithography Trend

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Exposure tools

Mask TechnologyTools: writers, inspection, & repair.Materials

Photoresist Materials

Resolution Enhancement TechniquesModel-based optical proximity correctionSub-resolution assist featuresAlternating phase shift mask

Elements for Lithography Leadership

Lithography Tool Options

80nm

70nm

60nm

50nm

2002

193nm, 0.75NA

193nm, 0.85NA

193nm, 0.92NA

157nm, 0.85NA157nm, 0.92NA

EPL beta

EPL prod. EUVL prod.

EUVL beta

2003 2004 2005 2006 2007

Res

olut

ion

Lithography Tool OptionsLithography Tool Options

80nm

70nm

60nm

50nm

2002

193nm, 0.75NA

193nm, 0.85NA

193nm, 0.92NA

157nm, 0.85NA157nm, 0.92NA

EPL beta

EPL prod. EUVL prod.

EUVL beta

2003 2004 2005 2006 2007

Res

olut

ion

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CMOS Circuit Density Outlook

Die Sizes up to 400 sq-mm

350nm Litho5 Metal Levels


130 Litho9 Metal Levels



Transistors/chip1E+9

1E+8

1E+7

1E+6

1E+51995 1997 1999 2001 2003

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LogCost/Function

Integration level (# ckts, bits)

.35um

.25um

.18um

Key Question:What functions to integrate?

H/P CMOS, L/C CMOSFlash, DRAMMixed SignalI/O interface mgmt"Passives"

Issues:Migration of designsTechnology conflictsCustomer-supplier relationship & IPSys-on-Chip vs. Sys-in-PackageTest

X

X

X

R C Lange

Optimum Integration Level Leads to System-On-Chip

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IBM SF Technology Platform

eDRAMRFCMOS

! CMOS Logic: ! High-performance (K)! Low active power (MP)! Low standby power (ULP)

! Communication CMOS! Analog & RF CMOS• Passive R/L/C devices• RF models and design kit

! System on a chip! Embedded DRAM! Embedded dense SRAM

Base

HighPerformance

Low Power

AnalogDenseSRAM

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Silicon Germanium Technology

Result:Cost and performance leadership in high frequency device technology.

Re-use present CMOS toolset. Add Silicon Germanium alloy base. 300-500% performance gain. Base contact

Emitter, N+Nitride

Oxide

Collector contact

Subcollector, N+

SIGe BASE, P+ Collector, N+

Bandgap EngineeringBase contact

Emitter, N+NitrideOxide

Collector contact

Subcollector, N+

BASE, P+ Collector, N+

5 years of fundamental research into materials science.

Bipolar transistoron BiCMOS chip Emitter

CollectorBase

E

C

B

EmitterCollector

Base

E

C

B

Now running at 350 GHz.

Also need high Q passives and design kits.

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System-on-Chip ExampleOpportunity for system integration

of digital CMOS, memory, radio frequency IC & intermediate

frequency bipolar/CMOS

Substantial system functionality, cost, power & density improvements achievable with technology integration10X cost : 5X power

1998

100 - 200 components

R/F

Baseband I/F

CMOS BiPolar GaAs

Baseband

RF / IF

2000

~ 10 components 2003

1 component

Opportunity for system integration of digital CMOS, memory, radio, frequency IC & intermediate frequency SiGe BiCMOS.

Substantial system functionality, cost, power & density improvements achievable with technology integration.

Achieve 1/10 the cost and 1/5 the power.

1998

2000

2003

CMOS Bipolar GaAs100-200 Components

10 Components

1 Component

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Long lead time for new materialsAverage of 10 years from research to manufacturing.Reliability learningYield learningMust have options for risk mitigation

Need industry-wide acceptance and infrastructure build-up to realize manageable cost.

Need early involvement of equipment makers and material suppliers.

Key Challenges for the Introduction of New Materials, Processes, and Tools

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The semiconductor industry focus is shiftingFrom performance alone To performance-power-flexibility.

We are entering an era of differentiation by innovationMoving from traditional scaling that many can do.To new materials and transistor structures that few can do, andTo greater functional integration.

Early involvement by equipment and material suppliers is required to achieve a successful semiconductor ecosystem.

Summary

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upcoming technology challenges for ic manufacturing

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