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TRANSCRIPT
External Use
TM
Using the Inter-Processor
Communication (IPC) Interface On
the MPC57xx Family Devices
FTF-AUT-F0240
A P R . 2 0 1 4
Randy Dees
TM
External Use 1
Objective
• Many of the MPC57xx MCUs include an optional high-speed
communication interface specifically designed for
communication between two MCUs on a single board or a
single MCU with a smart peripheral. This session explores the
320 Mbps Zipwire Inter-processor Communication Interface
(IPC), including hardware requirements and the available
software driver. Zipwire consists of a Serial Inter-processor
Interface (SIPI) that handles the high-level software protocol
for communication and the LVDS Asynchronous Serial
Transmission Interface (LFAST) that handles the hardware
layer physical interface.
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External Use 2
Agenda
• Zipwire Overview
• Serial Inter-processor Interface (SIPI)
• LVDS Fast Asynchronous Serial Transmission
Interface (LFAST)
• Zipwire Software Driver
• Summary
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External Use 3
What is Zipwire?
• Zipwire is a communication interface intended to be used to
connect two processors or an MCU with a smart peripheral together
at a high speed.
• The Zipwire interface consists of two sub-blocks
− Serial Inter-processor Interface (SIPI)
− LVDS Fast Asynchronous Serial Transmission Interface (LFAST)
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External Use 4
Why Zipwire (SIPI/LFAST)?
• Simple high speed, full duplex, flexible
interface
• Allows two capable devices to directly
access memory of a second device.
• Timeout protection
• Fixed priority
• CRC for data integrity
• MPC57xx devices: Either can be defined as
the master or slave
Zipwire devices
MPC5744P
MPC5746M
MPC5746R
MPC5775K
MPC5777C
MPC5777M
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External Use 6
Zipwire ISO OSI model
OSI Model
Protocol Name
Data Unit Layer Function
Host Layers
Data
7. Application Network process to application SIPI
Software
Zipwire
6. Presentation
Data representation, encryption and decryption, convert machine dependent data to machine independent data
SIPI Hardware 5. Session
Interhost communication, managing sessions between applications
Segment 4. Transport End-to-end connections, reliability and flow control
Media Layers
Packet 3. Network Path determination and logical addressing
LFAST Frame 2. Data Link Physical addressing
Bit 1. Physical Media, signal and binary transmission
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External Use 7
Typical Zipwire system
• Interfacing two Zipwire devices together only requires a termination
resistor for board matching for the clock signal.
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External Use 8
Zipwire clocking
• Clock source for the Zipwire interface
− XOSC
− Output of PLL0 (PLL0:PHI)
− External pin (provided by the Zipwire slave)
• Clock frequency is typically 20 MHz
• The 20 MHz clock may be used in the following ways:
− Shared between the MCUs using a dedicated reference clock pin on each MCU
− Divided by 2 and shared as a 10 MHz reference
− Shared as the fundamental clock for the MCU system clock and the LFAST reference clock
• The LFAST PLL for generating the 320 MHz clock is shared between LFAST for SIPI.
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External Use 11
What is SIPI?
• Up to 4 channels of data access, including 1 channel of streaming information
• SIPI provides LFAST physical medium
• Up to 2 outstanding requests are supported by the initiator
• Master or slave can be the initiator of a transaction
• Each channel has a payload of 32 bits
• Steaming channel allows 256 bits
• Accesses the Crossbar bus when the SIPI is the target
• Can use DMA when SIPI is the initiator
• Common tag pool for assigning sequential transfer IDs to new transfers
• Target node contains a set of nine 32-bit internal registers for command storage
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External Use 12
SIPI Block Diagram
• Channel 0 has the highest priority for transmission, and Channel 2 is the only channel that is capable of data streaming.
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External Use 14
SIPI Frame Format (continued)
• Trigger transfer, ID transfer, write acknowledge
• Streaming write request
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External Use 15
SIPI Header
• SIPI Header Coding
• Commands
− Read 8,16,32 bits
− Write 8,16,32 bits with acknowledge
− Acknowledge – Ok
− Acknowledge - Fault
− Read Answer – OK
− Trigger communication with acknowledge
− ID Register Read Request
− Stream Data with acknowledge (32 bytes)
Transaction
ID Command Channel #
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External Use 16
SIPI Commands b[12:8] (hex) Command Payload
Size
0x00 Read 8 bits 64
0x01 Read 16 bits 64
0x02 Read 32 bits 64
0x03 Reserved --
0x04 Write 8 bits with Acknowledge 96
0x05 Write 16 bits with Acknowledge 96
0x06 Write 32 bits with Acknowledge 96
0x07 Reserved --
0x08 Acknowledge – OK 32
0x09 Acknowledge – Fault 32
0x0A Read Answer – OK 64
0x0B Reserved --
0x0C Trigger command with Acknowledge 32
0x0D – 0x11 Reserved --
0x12 ID Register read request 32
0x13 – 0x16 Reserved
0x17 Stream Data with Acknowledge 288
0x18 – 0x1F Reserved
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External Use 17
SIPI Channel coding
SIPI Channel Name Channel Coding Comment
SIPI Channel Coding Select
Code Table 1 Code Table 2
0 (Channel A) 0b000 0b100 Supported
1 (Channel B) 0b001 0b101 Supported
2 (Channel C) 0b010 0b110 Supported
3 (Channel D) 0b011 0b111 Supported
4 (Channel E) 0b100 0b000 Reserved
5 (Channel F) 0b101 0b001 Reserved
6 (Channel G) 0b110 0b010 Reserved
7 (Channel H) 0b111 0b011 Reserved-
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External Use 19
What is LFAST?
• LFAST (LVDS Fast Asynchronous Serial Terminal) is a low pin
count, high bandwidth interface
• Consists of 2 LVDS pairs and clock
• It is the physical interface that transports the SIPI frames from one
device to another.
• Supports slow and fast data rates
− Starts in Slow – 6.5/5.0 Mbps
− Fast – 312/320 Mbps
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External Use 20
LFAST – Main Features
• Dual mode operation (Register configurable Master/Slave)
• Asynchronous data transfer rates up to a maximum of 320 Mbps
• Transmit and receive data, Clear to Send (CTS), Interface Control
Logical Channel (ICLC), and unsolicited frames
• Provision of five interrupts for Transmit and Receive channels
• Configurable frame length and payload sizes
• Configurable PLL for high speed mode
• LVDS configuration
• Multiple loopback modes for testing
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External Use 25
Zipwire software driver
• A driver will be available from Freescale to implement the Zipwire
interface.
− Scheduled for release this summer, a beta version is available
• Application note “Introduction to MPC57xx Zipwire Interface” to be
published as well
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External Use 26
Software Driver Functions
Type Name Arguments
uint8_t SIPI_ID uint32_t * id_arrayused
CHANNEL_t channel
uint8_t SIPI_Trigger void
uint32_t SIPI_get_initiator_event void
uint8_t SIPI_init_INITIATOR void
uint8_t SIPI_init_TARGET void
uint8_t SIPI_init_channel void
uint8_t SIPI_module_mode void
uint8_t SIPI_multiple_read read_array[]
uint16_t array_length
CHANNEL_t channel
uint8_t injected_error
uint32_t * read_temp
uint8_t SIPI_multiple_write void
uint8_t SIPI_read void
uint32_t SIPI_read_channel_data CHANNEL_t channel
uint8_t SIPI_reset void
uint8_t SIPI_stream_transfer void
uint8_t SIPI_write DATA_TEMPLATE_t write_data
CHANNEL_t channel
uint8_t injected_error
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External Use 28
FTF Resources
Session ID Title When
FTF-AUT-F0235 Overview of the eTPU Engine Control Library for
Qorivva 32-bit MCUs
Friday 10:30 AM
FTF-AUT-F0338 Hands-On Workshop: Performance Optimization
Hints and Tips for Power Architecture® (Reserved
Seat Required)
Tuesday 1:00 PM
FTF-AUT-F0339 Hands-On Workshop: Low-Power Techniques for
Power Architecture® (Reserved Seat Required)
Tuesday 3:15 PM
FTF-AUT-F0344 An Introduction to the MPC57xx Nexus Aurora
Interface
Wednesday 10:30 AM
FTF-AUT-F0345 MPC57xx e200zx Core Differences Wednesday 11:30 AM
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External Use 29
Summary The Zipwire interface provides a fast, simple, full duplex communication interface between 2 microcontrollers or a microcontroller and a smart peripheral.
Reliable, Robust Interface CRC with acknowledge responses, timeout protection
Fixed priority and streaming mode supported Allows for reliable data transfer for high priority information and for lower priority, continuous data..
320 MHz transfer rate Fast data transfers
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© 2014 Freescale Semiconductor, Inc. | External Use
www.Freescale.com