universität dortmund laboratory exercise...
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Universität Dortmund
Laboratory Exercise 6
Davide Rossi
DEI University of Bologna
AA 2017-2018
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Universität Dortmund
Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by:
• Microprocessor– 8,16,32 bit architecture– Usually “simple” in-order
microarchitecture, no FPU
Example: STM32F101 MCU
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Universität Dortmund
Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by:
• Microprocessor– 8,16,32 bit architecture– Usually “simple” in-order
microarchitecture, no FPU
• Memory– RAM (from 512B to 256kB)– FLASH (from 512B to 1MB)
Example: STM32F101 MCU
![Page 4: Universität Dortmund Laboratory Exercise 6courses.eees.dei.unibo.it/LABMPHSENG/wp-content/uploads/2018/0… · Laboratory Exercise 6 Davide Rossi DEI University of Bologna AA 2017-2018](https://reader034.vdocuments.us/reader034/viewer/2022042920/5f66130fd5cd4702f5482e53/html5/thumbnails/4.jpg)
Universität Dortmund
Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by:
• Microprocessor– 8,16,32 bit architecture– Usually “simple” in-order
microarchitecture, no FPU
• Memory– RAM (from 512B to 256kB)– FLASH (from 512B to 1MB)
• Peripherals– DMA– Timer– Interfaces
• Digital• Analog
Example: STM32F101 MCUDMAs
Interfaces
Timer
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Universität Dortmund
Microcontroller System Architecture
Each MCU (micro-controller unit) is characterized by:
• Microprocessor– 8,16,32 bit architecture– Usually “simple” in-order
microarchitecture, no FPU
• Memory– RAM (from 512B to 256kB)– FLASH (from 512B to 1MB)
• Peripherals– DMA– Timer– Interfaces
• Digital• Analog
• Interconnect– AHB system bus (ARM-based MCUs)– APB peripheral bus (ARM-based MCUs)
Example: STM32F101 MCU
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Universität Dortmund
Memory-Mapped Peripherals
Peripherals such as external interfaces in a microcontroller system are
accessible via memory-mapped registers:• for peripheral configuration
• for I/O
Cortex-M3
MCU core
memory mapped
load/store
addresses Memory Map
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Universität Dortmund
GPIOC_LED0_ADDR
Memory-Mapped Peripherals
Suppose our purpose is to blink a LED (i.e., a GPIO pin):
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Universität Dortmund
GPIOC_LED0_ADDR
Suppose our purpose is to blink a LED (i.e., a GPIO pin):
Memory-Mapped Peripherals
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Universität Dortmund
GPIOC_LED0_ADDR
STORE GPIOC_LED0_ADDR,0x1
Suppose our purpose is to blink a LED (i.e., a GPIO pin):
Memory-Mapped Peripherals
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Universität Dortmund
GPIOC_LED0_ADDR
STORE GPIOC_LED0_ADDR,0x1
Suppose our purpose is to blink a LED (i.e., a GPIO pin):
Memory-Mapped Peripherals
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Universität Dortmund
GPIOC_LED0_ADDR
STORE GPIOC_LED0_ADDR,0x1
Suppose our purpose is to blink a LED (i.e., a GPIO pin):
Memory-Mapped Peripherals
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Universität Dortmund
APB BUS
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Universität Dortmund
APB BUS SIGNALS
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Universität Dortmund
APB BUS: SLAVE INTERFACE
APB PERIPHERAL
PCLK
PRESETn
PADDR
PSEL
PENABLE
PWRITE
PWDATA
PRDATA
PREADY
PSLVERR
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Universität Dortmund
15
APB state machine• IDLE
– Default APB state
• SETUP– When transfer required– PSELx is asserted– Only one cycle
• ACCESS– PENABLE is asserted– Addr, write, select, and
write data remain stable– Stay if PREADY = L– Goto IDLE if PREADY = H
and no more data– Goto SETUP is PREADY = H
and more data pending
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Universität Dortmund
APB BUS: WRITE TRANSFER
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Universität Dortmund
APB BUS: READ TRANSFER
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Universität Dortmund
Exercise (1)Pulse-width modulation (PWM), is a modulation technique used to encodea message into a pulsing signal. Although this modulation technique can beused to encode information for transmission, its main use is to allow thecontrol of the power supplied to electrical devices, especially to inertialloads such as motors, and is a typical application for embedded electronicdevices such as low-power microcontrollers.
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Universität Dortmund
Exercise (2)The goal of this exercise is to design an programmable PWM controller.The PWM controller has to be programmed from an APB interface, and itfeatures the following pinout:
module APB_PWM
(
input logic PCLK,
input logic PRESETn,
input logic PADDR,
input logic PSEL,
input logic PENABLE,
input logic PWRITE,
input logic [31:0] PWDATA,
output logic PREADY,
output logic [31:0] PRDATA,
output logic PSLAVEERR,
output logic [7:0] PWM
)
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Universität Dortmund
Exercise (3)REGISTERDESCRIPTION
REGISTERADDRESS
REGISTER WIDTH
TYPE
PWM PERIOD (CLK CYCLES) 0x0 32-bit READ/WRITE
PWM PULSE (CLK CYCLES) 0x4 32-bit READ/WRITE
PWM SIZE (0-255) 0x8 8-bit READ/WRITE
PWM ENABLE (0=OFF, 1=ON) 0xC 1-bit READ/WRITE
PWM PERIOD
PWM PULSE
PWM
SIZE
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Universität Dortmund
Exercise (4)
1) Design a block diagram of the digital circuit2) Design the memory mapped APB registers using
system verilog hardware description3) Design the PWM FSM using system verilog
hardware description language4) Design a testbench to validate the functionality
of the designed digital circuit
Design the digital circuit in a modular way (i.e. Design every digital block in a separate system
verilog module)