Universal Verification Methodology (UVM) BenefitsMustafa KhairallahBoost Valley B

oost

Vall

ey

Con

sult

ing

1

Outline

Verification Needs UVM Benefits Example: I2S Conclusion

Boost

Vall

ey

Con

sult

ing

2

Verification Needs

Boost

Vall

ey

Con

sult

ing

3

Code ReuseTest Cases &

Scenarios Modification

Functional Coverage

Calculation

Generating & Managing Reports

Debugging Communication

Verification Needs - Development

Boost

Vall

ey

Con

sult

ing

4

Code ReuseTest Cases &

Scenarios Modification

Functional Coverage

Calculation

Generating & Managing Reports

Debugging Communication

Verification Needs - Compilation

Boost

Vall

ey

Con

sult

ing

5

Code ReuseTest Cases &

Scenarios Modification

Functional Coverage

Calculation

Generating & Managing Reports

Debugging Communication

Verification Needs - Runtime

Boost

Vall

ey

Con

sult

ing

6

Code ReuseTest Cases &

Scenarios Modification

Functional Coverage

Calculation

Generating & Managing Reports

Debugging Communication

Verification Needs - Debugging

Boost

Vall

ey

Con

sult

ingCode Reuse

Test Cases &Scenarios

Modification

Functional Coverage

Calculation

Generating & Managing Reports

Debugging Communication7

Verification Methodologies

Do the same things the same way: Ease of communication.

Test/Test-bench separation: Compile once, run many times.

Utilities: Functional coverage – reporting

mechanisms - … etc.

Boost

Vall

ey

Con

sult

ing

8

UVM Benefits

Boost

Vall

ey

Con

sult

ing

9

UVM Adoption

Boost

Vall

ey

Con

sult

ing

10

Test/Test-bench separation

• Test Writer:• Selects sequences,• Configures the

environment(s)• Runs test.

Test

Test

Environment

Bus Agent

Active Agent

Passive Agent

Analysis Agent Register Model

Environment

Configurations

DUT

• UVC User: Integrates UVCs into environment to test different designs.

Env(Test-

bench)

• Developer: UVC Design

• Complication phase.UVCs B

oost

Vall

ey

Con

sult

ing

11

Test/Test-bench separation

Test Environment

Bus Agent

Active Agent

Passive Agent

Analysis Agent Register Model

Environment

Configurations

Boost

Vall

ey

Con

sult

ing

13

Configurability

Controlled by the test writer.

Configurations can be: Structural configurations. Runtime configurations.

Provides topological flexibility: Components can be overridden, removed or

configured.

Boost

Vall

ey

Con

sult

ing

14

Block 2’

TLM 2.0

UVM is compatible with the TLM 2.0 standard. Uses port/export communication. Hides communication details (pin level activities) Eases customization using configurations & overrides.

Block 1 Block 2 Boost

Vall

ey

Con

sult

ing

15

Constrained Randomization

Boost

Vall

ey

Con

sult

ing

16

Coverage Collector

Boost

Vall

ey

Con

sult

ing

17

Checker (Reference Model)

Boost

Vall

ey

Con

sult

ing

18

Checker (Assertions)

Boost

Vall

ey

Con

sult

ing

19

Built-in reporting mechanisms.

Boost

Vall

ey

Con

sult

ing

20

Built-in reporting mechanisms.

Boost

Vall

ey

Con

sult

ing

21

Practical Example :I2S

Boost

Vall

ey

Con

sult

ing

22

Introduction I2S stands for Inter-IC Sound, DUT is a slave I2S transceiver. It is around 2000 gates.

I2S Bus Purpose: Communicate PCM audio data between integrated circuits.

Characteristics Separates clock and serial data signals. Lower Jitter. Can recover clock from data stream.

Boost

Vall

ey

Con

sult

ing

23

UVM Test-Bench Architecture

Boost

Vall

ey

Con

sult

ing

24

Runtime Comparison

2 20 200 2000 20000 200000 20000000

5

10

15

20

25

VHDL Test-BenchUVM Test-Bench

No. of test cases

> 10 Times

Reduction!!

Boost

Vall

ey

Con

sult

ing

26

Time in minutes

VHDL UVM

Summary

Conventional Test-bench UVM Test-Bench

• Mainly simulation-based • Limited assertion-based

capabilities

• Simulation based• Advanced assertion-based

in System Verilog & UVM

Mostly directed testing Constrained random testing & directed testing

Boost

Vall

ey

Con

sult

ing

27

Summary

Conventional Test-bench UVM Test-Bench

Can’t automatically guarantee full functional coverage Supports functional coverage

Boost

Vall

ey

Con

sult

ing

28

Summary

Conventional Test-bench UVM Test-Bench

Strongly coupled with DUT Loosely coupled with DUT

Requires longer development time

Reusability reduces development time B

oost

Vall

ey

Con

sult

ing

29

Thank YouQuestions?

Boost

Vall

ey

Con

sult

ing

30