united states patent and trademark office before the … · 2017-05-25 · continental automotive,...

Exhibit 1002

1

UNITED STATES PATENT AND TRADEMARK OFFICE _______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD

_____________

BROADCOM CORPORATION Petitioner

v.

TESSERA ADVANCED TECHNOLOGIES, INC. Patent Owner.

Patent No. 6,954,001 Issue Date: October 11, 2005

Title: SEMICONDUCTOR DEVICE INCLUDING A DIFFUSION LAYER _______________

Inter Partes Review No. Unassigned

____________________________________________________________

DECLARATION OF DR. JEFFREY C. SUHLING

Exhibit 100200001

Exhibit 1002

2

CONTENTS

I. Introduction And Qualifications ..........................................................................................5

II. Understanding of the Governing Law and Perspectives Applied ......................................10A. Types Of Claims – Independent And Dependent ..................................................10B. Unpatentability By Anticipation Or Obviousness .................................................10C. Secondary Or Objective Evidence Of Non-obviousness .......................................11D. Interpreting Patents Claims Before The Patent Office ..........................................12E. Relevant Time Period For Analysis .......................................................................13F. Bases For My Opinion ...........................................................................................13G. Level Of Ordinary Skill In The Art In The Relevant Timeframe ..........................14

III. Introduction To The ‘001 patent ........................................................................................16A. Content of the ‘001 patent ......................................................................................16B. Written Record At the Patent Office ......................................................................21C. Background of WLCSP Technology at the Time of the ‘001 Patent ....................25D. Background on Soldering at the Time of the ‘001 Patent ......................................27

IV. Detailed Explanation Of Claim Terms ..............................................................................28A. “electrode” (claims 1-18) .......................................................................................29B. “electrode portion” (claims 1-18) ..........................................................................29C. “metal component” (claims 1-18) ..........................................................................30D. “diffusion layer formed between said first electrode portion and said second

electrode portion” (claims 1-18) ............................................................................30E. “said first electrode portion and said diffusion layer have a combined thickness in

the range of 10 m to 20 m” (claims 10-18) ........................................................32F. “flush with or higher than a surface of the insulating film” (claims 5 and 14) ......33G. Preamble of Independent Claims 1 and 10 ............................................................34

V. Analysis of the Prior Art ....................................................................................................34A. PCT Publication No. WO00/52755 (“Narizuka”) .................................................34B. Narizuka Describes The Content Of Claims 1-18 .................................................37

1. Narizuka: Independent Claim 1 .................................................................372. Narizuka: Dependent Claim 2 (The semiconductor device of claim 1,

wherein said first metal component includes copper and said second metal component includes tin) .............................................................................47

3. Narizuka: Dependent Claim 3 (The semiconductor device of claim 1, further comprising a third electrode portion formed on a surface of the semiconductor element and a metal wiring formed on the semiconductor element, said metal wiring electrically connecting the first electrode portion to the third electrode portion) ........................................................47

4. Narizuka: Dependent Claim 4 (The semiconductor device of claim 3, wherein the first and third electrode portion are horizontally spaced apart with respect to the semiconductor element) ...............................................49

5. Narizuka: Dependent Claim 5 ....................................................................50

Exhibit 100200002

Exhibit 1002

3

6. Narizuka: Dependent Claim 6 (The semiconductor device of claim 3, wherein the metal wiring includes copper) ................................................53

7. Narizuka: Dependent Claim 7 ....................................................................538. Narizuka: Dependent Claim 8 (The semiconductor device of claim 3,

wherein the metal wiring has a thickness in the range of 0.01 m to 8 m)569. Narizuka: Dependent Claim 9 (The semiconductor device of claim 1,

further comprising a substrate having a wiring electrode, wherein said wiring electrode is electrically connected to said second electrode portion)57

10. Narizuka: Independent Claim 10 ...............................................................5811. Narizuka: Dependent Claim 11 ..................................................................6012. Narizuka: Dependent Claim 12 ..................................................................6113. Narizuka: Dependent Claim 13 ..................................................................6114. Narizuka: Dependent Claim 14 ..................................................................6115. Narizuka: Dependent Claim 15 ..................................................................6116. Narizuka: Dependent Claim 16 ..................................................................6117. Narizuka: Dependent Claim 17 (The semiconductor device of claim 12,

wherein the metal wiring has a thickness in the range of 0.01 m to 8 m)6218. Narizuka: Dependent Claim 18 ..................................................................62

C. German Patent Publication No. DE 100 11 368 (“Takizawa”) .............................63D. Takizawa Describes The Content Of Claims 1-7, 9-16, and 18 ............................66

1. Takizawa: Independent Claim 1 ................................................................662. Takizawa: Dependent Claim 2 (The semiconductor device of claim 1,

wherein said first metal component includes copper and said second metal component includes tin) .............................................................................72

3. Takizawa: Dependent Claim 3 (The semiconductor device of claim 1, further comprising a third electrode portion formed on a surface of the semiconductor element and a metal wiring formed on the semiconductor element, said metal wiring electrically connecting the first electrode portion to the third electrode portion) ........................................................73

4. Takizawa: Dependent Claim 4 (The semiconductor device of claim 3, wherein the first and third electrode portion are horizontally spaced apart with respect to the semiconductor element) ...............................................74

5. Takizawa: Dependent Claim 5 ...................................................................746. Takizawa: Dependent Claim 6 (The semiconductor device of claim 3,

wherein the metal wiring includes copper) ................................................797. Takizawa: Dependent Claim 7 ...................................................................798. Takizawa: Dependent Claim 9 (The semiconductor device of claim 1,

further comprising a substrate having a wiring electrode, wherein said wiring electrode is electrically connected to said second electrode portion)83

9. Takizawa: Independent Claim 10 ..............................................................8310. Takizawa: Dependent Claim 11 .................................................................8511. Takizawa: Dependent Claim 12 .................................................................8512. Takizawa: Dependent Claim 13 .................................................................8513. Takizawa: Dependent Claim 14 .................................................................8514. Takizawa: Dependent Claim 15 .................................................................8615. Takizawa: Dependent Claim 16 .................................................................86

Exhibit 100200003

Exhibit 1002

4

16. Takizawa: Dependent Claim 18 .................................................................86E. Takizawa Combined with Narizuka For Claims 8 and 17 .....................................86F. Takizawa Combined with Hashimoto For Claims 7 and 16 ..................................89

VI. Secondary or Objective Evidence of Non-obviousness .....................................................90

VII. Overall Conclusion ............................................................................................................91

Exhibit 100200004

Exhibit 1002

5

1. I, Jeffrey C. Suhling, a resident of Opelika, Alabama, hereby declare

as follows:

2. I have been retained by Foley & Lardner LLP to provide certain

opinions concerning the validity of the claims of U.S. Pat. No. 6,954,001 (“the

‘001 patent”) (Ex. 1001).

3. I am being compensated for my time at a rate of $300 per hour. I am

not receiving any other form of compensation. I have no interest in the outcome of

this proceeding, and my compensation is not dependent on the content of my

opinions or the outcome of this proceeding.

I. Introduction And Qualifications

4. My technical background and experience are summarized in my

resume (Exhibit A to this declaration). In summary, I earned a Bachelor of

Science in Applied Mathematics, Engineering, and Physics (AMEP) from the

University of Wisconsin in 1980. I earned a Master of Science in Engineering

Mechanics from the University of Wisconsin in 1981, and a Doctorate in

Engineering Mechanics from the University of Wisconsin in 1985.

5. I am currently employed as a Quina Distinguished Professor and

Department Chair at the Department of Mechanical Engineering at Auburn

University in Auburn, Alabama. I have been on the faculty at Auburn University

Exhibit 100200005

Exhibit 1002

6

since 1985. I am a member of the American Society for Mechanical Engineers

(ASME) and the Institute of Electrical and Electronics Engineers (IEEE), and

currently serve on several boards.

6. My primary areas of expertise and research are semiconductor

packaging and solid mechanics. I have over 30 years of experience in each of

these fields. In the area of semiconductor packaging, I have extensive experience

in electronics assembly and packaging technologies and processes, stress and strain

analysis of electronic products, on-chip silicon sensors, solder joint reliability,

material testing and mechanical behavior of solders and microelectronic

encapsulants, and finite element modeling (FEA) and reliability modeling of

electronic products. I have regularly taught undergraduate-level and graduate-level

courses on electronics packaging technology for the past 25 years. I have

published and presented over 425 technical papers in various international journals

and conferences.

7. I co-founded the Center for Advanced Vehicle Electronics or

“CAVE” in 1998. This organization is a research center for semiconductor

packaging that has been continuously funded for the past 18 years by the National

Science Foundation and over 50 member companies. The CAVE Center

specializes in the assembly, packaging, mechanics, thermal, and reliability aspects

Exhibit 100200006

Exhibit 1002

7

of semiconductor packaging in harsh environments such as automotive and

aerospace electronics, computer servers, cellular phones and portable electronics,

among other devices. I served as Center Director of CAVE from 2002-2008, and

Center Associate Director from 1998-2008. I have continued to direct two CAVE

research areas (Lead Free Soldering, and Flip Chip and Underfills) since being

promoted in 2008 to Department Chair of the Department of Mechanical

Engineering

8. I have received over 100 contracts and grants to support my research,

the bulk of which is focused on various aspects of semiconductor packaging. In

particular, I have obtained research support from the National Science Foundation,

Semiconductor Research Corporation, NASA, Department of Defense - Army, Air

Force, Navy, and over 50 companies including Texas Instruments, ST

Microelectronics, Freescale Semiconductor, NXP, Cookson Electronics, Henkel

Corporation, Schlumberger, John Deere Electronics, Chrysler Corporation,

Continental Automotive, Siemens, LG, General Dynamics Corporation, and others.

I have received several awards including being elected a Fellow of the American

Society of Mechanical Engineers, as well as receiving the Electronic Packaging

Division Mechanics Research Award from the same society.

Exhibit 100200007

Exhibit 1002

8

9. As evidenced by my resume attached to this declaration, I am well

versed in semiconductor packaging technology and I have been working in that

field for nearly 30 years from 1988-present. I have published and presented over

350 technical papers in the electronic packaging technical area, as well as attending

over 50 technical conferences in the field. I have served as the Conference General

Chair of the 2009 International Conference on Packaging and Integration of

Electronic and Photonic Microsystems (InterPACK), and am currently serving as

the Vice Program Chair for the 2017 Intersociety Conference on Thermal and

Thermomechanical Phenomena in Electronic Systems (ITherm). I have also

served in other leadership roles in the semiconductor packaging area, including my

current appointment as Associate Editor for the ASME Journal of Electronic

Packaging, a leading technical journal in the field.

10. My expertise in the field of semiconductor packaging includes the

design, manufacturing, and reliability of interconnections for semiconductor chips,

which is the technology area addressed in the ‘001 patent. From the chronological

point of view, my experiences in these areas encompass the December 2001

alleged invention date of the ‘001 patent. In fact, over the past 20 years I have

worked extensively with several flip chip technologies as well as a variety of

Wafer Level Chip Scale Packages (WLCSPs). These efforts have involved

semiconductor chips with thin passivation films, redistribution layers (RDLs),

Exhibit 100200008

Exhibit 1002

9

copper wiring (traces), insulating films, encapsulant (resin) layers, copper

plugs/pillars, and Sn-based solder balls, which are all elements discussed in the

technology of the ‘001 patent.

11. My work in these areas continues today. For example, WLCSPs are

currently being studied in my ongoing research project on isothermal aging

induced degradations on solder joint reliability. This work involves surface mount

assembly of several types of Wafer Level Packages to printed circuit boards, and

subsequent isothermal aging and thermal cycling reliability testing of the

assemblies. In addition, material testing has been performed to characterize the

mechanical properties of WLCSP dielectric layers and encapsulants, and finite

element modeling has been performed on WLCSP assemblies to predict their

reliability.

12. I am also very familiar with the soldering techniques used in

semiconductor packaging, including the development of Sn-Cu Intermetallic

Compound (IMC) layers at the interfaces where Sn-based solders are

metallurgically joined to copper contacts (electrodes) or to copper wiring. I have

performed research on soldering and solder joint reliability since the early 1990s,

and I published my first paper on solder joint reliability at the 1994 IEEE

Electronic Components and Technology Conference (ECTC). Over the past 25

Exhibit 100200009

Exhibit 1002

10

years, I have participated in over 50 research projects studying solders,

intermetallic compounds, and solder joint reliability, and I have co-authored over

190 scientific publications on the results of these studies in various international

technical journals and conference proceedings. My current research in this area

involves studying the growth of IMC particles and layers during isothermal aging

of plastic ball grid area (PBGA), WLCSP, and flip chip assemblies.

II. Understanding of the Governing Law and Perspectives Applied

A. Types Of Claims – Independent And Dependent

13. I understand that there are two types of U.S. patent claims: 1)

independent claims and 2) dependent claims. I understand that independent claims

only include the aspects stated in the independent claim. I further understand that

dependent claims include the aspects stated in that dependent claim, and any other

aspects stated in any claim from which that dependent claim depends.

B. Unpatentability By Anticipation Or Obviousness

14. I understand that a claim is not patentable if it is anticipated or

obvious. I understand that anticipation of a claim requires that every element of a

claim is disclosed expressly or inherently in a single prior art reference, arranged

as in the claim, when considered from the perspective of a person of ordinary skill

in the relevant art. I understand that when the structure recited in a reference is

Exhibit 100200010

Exhibit 1002

11

substantially identical to that of the claims, claimed properties or functions are

presumed to be inherent.

15. I further understand that obviousness of a claim requires that the claim

be obvious from the perspective of a person of ordinary skill in the relevant art, at

the time the invention was made. In analyzing obviousness, I understand that it is

important to understand the scope of the claims, the level of skill in the relevant

art, the scope and content of the prior art, the differences between the prior art and

the claims, and any “secondary considerations” (described below). I also

understand that if a technique has been used to improve one device, and a person

of ordinary skill in the art would recognize that it would improve similar devices in

the same way, using the technique is obvious unless its actual application is

beyond his or her skill. There may also be a specific “teaching, suggestion or

motivation” to combine any first prior art reference with a second prior art

reference. Such a “teaching, suggestion, or motivation” to combine the first prior

art reference with the second prior art reference can be explicit or implicit.

C. Secondary Or Objective Evidence Of Non-obviousness

16. I understand that secondary (or objective) considerations are relevant

to the determination of whether a claim is obvious. Such secondary (or objective)

considerations can include evidence of commercial success caused by an invention,

Exhibit 100200011

Exhibit 1002

12

evidence of a long-felt need that was solved by an invention, evidence that others

copied an invention, or evidence that an invention achieved a surprising or

unexpected result. I understand that such evidence must have a nexus, or causal

relationship to the elements of a claim, in order to be relevant to the obviousness or

non-obviousness of the claim. As explained in more detail below in paragraph

161, I am only aware of the alleged unexpected results as explained in the ‘001

patent, but those unexpected results are not tied to any actually claimed features of

claims 1-18. In the event any other secondary or objection evidence of non-

obviousness is identified, I reserve my right to review and respond to such

evidence.

D. Interpreting Patents Claims Before The Patent Office

17. I understand that “inter partes review” is a proceeding before the

United States Patent & Trademark Office (“Patent Office”) for evaluating the

unpatentability of an issued patent claim. Counsel has informed me that claims in

an inter partes review are given their broadest reasonable interpretation that is

consistent with the patent specification. I understand that a patent’s “specification”

includes all the figures, discussion, and claims within the patent document. I

understand that the Patent Office will look to the specification to see if there is a

definition for a claim term, and if not, will apply the broadest reasonable ordinary

meaning from the perspective of a person of ordinary skill in the art. However, I

Exhibit 100200012

Exhibit 1002

13

also understand that if a term has no accepted meaning to those of ordinary skill in

the prior art, its meaning, then, must be found in the patent. I present a more

detailed explanation of certain of the terms in the ‘001 patent in the section entitled

“Detailed Explanation of Claim Terms” below.

E. Relevant Time Period For Analysis

18. I understand that the earliest patent application filing leading to U.S.

Pat. No. 6,954,001 (“the ‘001 patent") (Ex. 1001) was a Japanese application filed

on December 20, 2001, and I have assumed this is the ‘001 patent’s alleged

invention date. I have therefore analyzed the unpatentability of the claims as of

that day or somewhat before (approximately 2000 – December 20, 2001),

understanding that as time passes; the knowledge of a person of ordinary skill in

the art will increase. I may refer to the relevant time period as 2000-2001 in this

declaration, with the understanding that this does not include the time period on or

after the filing date of the first application (December 20, 2001).

F. Bases For My Opinion

19. In forming my opinion, I have relied on the ‘001 patent claims, the

‘001 patent specification, the written record with the U.S. patent office for the ‘001

patent and the ‘001 patent’s related “parent application,” the exhibits to the Petition

for inter partes review of the ‘001 patent, and my own experience and expertise of

Exhibit 100200013

Exhibit 1002

14

the knowledge of the person of ordinary skill in the relevant art in the 2000-2001

timeframe as set forth in more detail below.

G. Level Of Ordinary Skill In The Art In The Relevant Timeframe

20. The relevant time for assessing the level of skill of the hypothetical

person of ordinary skill in the art is the December 20, 2001, filing date of the

Japanese application, to which I understand the ‘001 patent ultimately claims a

benefit for its date of alleged invention. To assess the level of ordinary skill in the

art at that time, I understand that one should consider factors such as: (1) the

educational level of the inventor; (2) the type of problems encountered in the art;

(3) prior art solutions to those problems; (4) the rapidity with which innovations

are made; (5) the sophistication of the technology; and (6) the educational level of

active workers in the field.

21. Considering all of these factors, it is my opinion that one of ordinary

skill in the art of the ‘001 patent prior to December 20, 2001, would have been a

person having at least: i) a bachelor-level degree in mechanical engineering,

materials science, electrical engineering, or a related field and at least 3-5 years of

experience in the design/development of semiconductor packages; ii) a Master’s

level degree in mechanical engineering, materials science, electrical engineering,

or a related field and at least 1-3 years of experience in the design/development of

Exhibit 100200014

Exhibit 1002

15

semiconductor packages, or iii) a PhD-level degree in mechanical engineering,

materials science, electrical engineering, or a related field and at least some

experience in the area of semiconductor packaging.

22. I base the foregoing on my own experience as an educator at Auburn

University, where certain of my former students in the relevant 2000-2001 time-

frame were involved in the design and development of semiconductor packages

and associated technology. Further, I have been a frequent attendee at conferences

and conventions, including several within or immediately before the relevant 2000-

2001 time-frame, at which I interacted with engineers working in the industry.

Some examples include the 1999, 2000, and 2001 IEEE Electronic Components

and Technology Conferences, the 1999 and 2001 ASME InterPACK Conferences,

the 1999 IMAPS annual conference, the 2000 NEPCON West Conference and

Exhibition, and the 2001 SMTA Surface Mount International Conference.

23. Along those lines, I have identified Ex. 1003 (Lau, J. H., “Integrated

Circuit Packaging Trends,” Chapter 1, Low Cost Flip Chip Technologies for DCA,

WLCSP, and PBGA Assemblies, 2000), which demonstrates the high speed of

semiconductor package development in the relevant 2000-2001 time frame, as well

as the continuously occurring reduction of semiconductor package footprint. This

demonstrates that with the above-noted average skill in the art, engineers were able

Exhibit 100200015

Exhibit 1002

16

to quickly make improvements and were well versed in the technology and the

various design choices available to them. For example, a person of ordinary skill

in the art at the time of the alleged invention of the ‘001 patent would have had

been generally familiar with the copper redistribution wiring and interconnect

structures used in the latest flip chip and WLCSP technologies in the relevant

2000-2001 time frame as discussed in sections 1.2.4, 1.3.1, and 1.3.6 in Chapter 1

(Ex. 1003) of the Lau reference book published in the year 2000.

24. My statements in this declaration are given from the perspective of a

person of ordinary skill in the art at the time of the December 2001 filing, and for

some time before then, unless otherwise specifically indicated. This is true even if

my statements are given in the present tense.

III. Introduction To The ‘001 patent

A. Content of the ‘001 patent

25. As explained in its “Background of the Invention” section, the ‘001

patent “relates to a semiconductor device in which a metal wiring is formed so as

to be electrically connected to an electrode of a semiconductor element and a part

of the metal wiring is used as an external electrode, and method of manufacturing

the same. More particularly, the present invention relates to a semiconductor

device having excellent junction reliability between a metal wiring and a ball

Exhibit 100200016

Exhibit 1002

17

electrode mounted to an external electrode portion of the metal wiring.” (Ex. 1001,

1:8-17.) Put simply, the ‘001 Patent relates to wiring of a semiconductor element,

where the wiring is connected to an external electrode allowing connection of the

internal circuitry to the outside world, through a solder ball, as an example. The

‘001 patent includes a number of examples, which are discussed below.

26. The first example of the ‘001 Patent’s “semiconductor device” is

shown in Fig. 2. Fig. 2 shows an electrode 12 on a semiconductor element 11,

wiring 14 connected to the electrode 12, an external electrode portion 14a, an

insulating film 15 formed on wiring 14 with an opening to expose the external

electrode portion 14a, and a solder ball electrode 16 connected to the external

electrode portion 14a through the opening. (See Ex. 1001, 8:12-38.) The ‘001

patent explains that the external electrode portion 14a shown in Fig. 2 is the

portion of the wiring 14 connected to solder ball electrode 16, including the

“metal-material embedded portion” formed in the opening of the insulating film

15. (See Id. at 8:23-26 (“The insulating film 15 has openings in order to expose a

portion of each metal wiring 14 which functions as an external electrode

(hereinafter, referred to as ‘external electrode portion 14a’)”); 8:51-55 (“the

thickness of the external electrode portion 14a is equal to the total thickness of the

metal wiring 14 and the portion filled with the metal material (hereinafter, referred

to as ‘metal-material embedded portion’)”.)

Exhibit 100200017

Exhibit 1002

18

27. The wiring 14, including its external electrode portion 14a, is

described as containing Copper (Cu). (Id. at 8:43-50.) The solder ball electrode 16

is described as containing Tin (Sn). (Id. at 8:64-65.) The ‘001 patent further

explains that when the wiring portions (14 and 14a) contain Cu, and the solder ball

electrode 16 contains Sn, a Sn-Cu alloy layer is formed. (Id. at 8:63-9:1 (“Sn

contained in solder of the ball electrode 16 diffuses into Cu contained in the metal

wiring 14, whereby a Sn—Cu alloy layer having low strength grows in the

thickness direction of the external electrode portion 14a”).) 1 The ‘001 patent also

explains how the electrodes 12 of the semiconductor element in Fig. 2 are

connected to a substrate (e.g. to a printed circuit board) (not shown in the figure) as

follows: “The electrodes 12 of the semiconductor element 11 and the wiring

electrodes of the substrate are thus respectively connected to each other through

the metal wirings 14 and the ball electrodes 16.” (Id. at 8:35-38.)

28. In addition, the insulating film 15 shown in Fig. 2 is described as

“flush” or “equal” with the exposed surface of the external electrode 14a, which

the ‘001 patent explains means “approximately flush” or “approximately equal.”

(See Id. at 10:22-29.) The insulating film 15 is described as “a resin film formed

from solder resist or the like” (Id. at 8:25-26), which makes logical sense given its

1 In this declaration, all emphasis to quotations is added unless noted

otherwise.

Exhibit 100200018

Exhibit 1002

19

location adjacent to solder ball electrode 16 which is connected to external

electrode 14a.

29. A second example is shown in Fig. 5, and adds an insulating resin

layer 17 to the first example. (Id. at 11:54-57.) The added insulating resin layer 17

is formed between the wiring 14 and the semiconductor element 11. (Id. at 12:16-

22.) The ‘001 patent explains the insulating resin layer 17 may be formed of an

“epoxy resin having low elasticity or the like,” which the ‘001 patent states can

result in the following effects:

“when the temperature is varied to melt the ball electrodes 16 in the

process of mounting the semiconductor device to the substrate,

stresses are generated due to the difference in thermal expansion

coefficient between the semiconductor device and the substrate.

However, these stresses can be absorbed by the insulating resin

layer 17. As a result, the stresses are reduced, whereby the external

electrode portion 14a of the metal wiring 14 to which the ball

electrode 16 is connected can be prevented from being broken by the

stresses.” (Id. at 12:16-36.)

30. Fig. 8B shows a third example, which differs from the first example in

the composition of its wiring 14 and “metal-material embedded portion” 18A –

where the wiring 14 is described as a combination of Titanium Tungsten (TiW)

and Cu (Id. at 14:28-31), and the “metal-material embedded portion” 18A is

Exhibit 100200019

Exhibit 1002

20

described as a combination Titanium (Ti) and Cu (Id. at 14:53-54). The portion of

the wiring 14, including “metal-material embedded portion” 18A, connected to

solder ball electrode 16 is described as the external electrode portion in the third

example. (Id. at 15:39-46.) Similar to the second example, the ‘001 patent

suggests an insulating resin layer can be used with its third example. (See Id. at

17:44-58.)

31. The ‘001 patent includes additional examples in its Figs. 10C, 12C,

and 13D, which are similar to the other examples, but with different wiring and

“metal-material embedded portion” materials. Notably, in all of these additional

examples, just like all of the others in the ‘001 patent, the portion of the wiring 14,

including the “metal-material embedded portion” (or portions), connected to a

solder ball electrode is described as the external electrode portion. (See Id. at 19:4-

10 (regarding Fig. 10C); 21:31-34 (regarding Fig. 12C); 24:65-25:4 (regarding Fig.

13D).)

32. Along those lines, I also noted in my review of the ‘001 patent that

where a thickness is defined, it is always in connection with the wiring, the “metal-

material embedded portion”, or together as the external electrode portion, and

never with respect to an intermetallic layer. (See Id. at 4:21-22 (thickness of

external electrode portion of “10μm to 20μm”); 8:39-42 (thickness of external

Exhibit 100200020

Exhibit 1002

21

electrode portion of 14μm); 9:25-35 (thickness of wiring is preferably in the range

of 0.01 μm to 8 μm); 9:36-10:14 (thickness of external electrode portion of “10μm

to 20μm” and other specific thicknesses); 18:32-34 (thickness of wiring of 5 μm);

20:14-17 (thickness of external electrode of “10μm to 20μm”); 23:34-40 (thickness

of external electrode of “10μm to 20μm”); 24:26-27 (thickness of a “metal-

material embedded portion of 20 μm”).) I also note that the claim term “diffusion

layer” does not appear in the specification.

33. In view of that, one of skill in the art would have difficulty discerning

the boundaries of claim 10, which claims the “combined thickness” of the “first

electrode portion” and the “diffusion layer,” as explained in more detail below.

B. Written Record At the Patent Office

34. My understanding is that the ‘001 patent issued from a U.S.

application with serial no. 10/919,402 (“the ‘402 application”), filed Aug. 17,

2004. My further understanding is that the ‘402 application is related to another

earlier U.S. application with serial no. 10/307,450 (“the ‘450 application”), filed

Dec. 2, 2002, that includes the same specification.

35. To further inform myself as to the content of the ‘001 patent, I

reviewed the written record between the applicants and the U.S. patent office in

both the ‘402 and ‘450 applications. Of particular interest was what was said about

Exhibit 100200021

Exhibit 1002

22

the limitation of claim 10 of “said first electrode portion and said diffusion layer

have a combined thickness in the range of 10 m to 20 m,” since the ‘001 patent

is silent on any thickness of a “diffusion layer,” as noted above, and instead only

discusses thicknesses of the wiring and the external electrode portion (i.e., “first

electrode portion”).

36. In reviewing the written record of the ‘402 application, it only had one

office action where the Examiner rejected the claims. (See Ex. 1004 at pp. 90-100.)

The applicants made two arguments in response to that office action, neither of

which are factually correct in my opinion.

37. First, with respect to what ultimately issued as independent claim 1,

the applicants argued that the Mune prior art cited by the Examiner, provided as

Ex. 1005, is “completely silent as to the materials of the outer electrodes 31 and

solder ball 26, let alone suggest [sic] a diffusion layer comprising their respective

metal component [sic].” (See Ex. 1004, at p. 82.) That is factually incorrect, in my

opinion, as Mune states its outer electrodes 31 are preferably made of Copper (Cu)

(Ex. 1005, ¶ [0044]), and Mune refers to solder balls 26 which one of skill would

have appreciated is a reference to at least a Tin (Sn)-based solder. As noted in the

section I provide below on the details of microelectronics soldering, one of skill in

the art would have appreciated that when you have an interface of Copper (Cu)

Exhibit 100200022

Exhibit 1002

23

with a Tin (Sn)-based solder ball, you will have an intermetallic Sn-Cu alloy layer,

which the applicants argued is the “diffusion layer” claimed in the ‘001 patent.

(See Ex. 1004, at p. 82 (“a diffusion layer (e.g. Sn-Cu alloy layer)”).)

38. The second argument the applicants made was in connection with the

limitation of claim 10 of “said first electrode portion and said diffusion layer have

a combined thickness in the range of 10 m to 20 m.” (See Id. at 83-84.) That

argument is interesting as it focuses on what I noted before, in that it only refers to

the portions of the ‘001 patent’s specification relating to any range of “10 m to 20

m”, which are the portions describing the external electrode portion (i.e., the “first

electrode portion.” (See Id (“As discussed in detail on page 16, line 10 – page 17,

line 15 of Applicants’ specification, Applicants have discovered that an electrode

thickness less than 10 m is susceptible to being disconnected while a thickness of

more than 20 m can lead to greater pattern deformation…. Only Applicants’ have

discovered the dual benefits set at both ranges for the electrode thickness”).) In

my view, the arguments made by the applicants do not apply to the claimed

feature, which is a “combined thickness” of both the “first electrode portion” and

the “diffusion layer,” as the specification only talks about one portion of that

equation, and there are a variety of different variables that dictate the thickness of

any “diffusion layer.” As I explained before, there is nothing in the ‘001 patent

regarding the thickness of any “diffusion layer.” So, the written record with the

Exhibit 100200023

Exhibit 1002

24

patent office confirms my initial conclusion based on review of the ‘001 patent

itself, that one of skill in the art would have difficulty discerning the boundaries of

claim 10.

39. I also found the source of the claim 10 limitation enlightening, as it

was not part of the original set of claims that were filed in the earlier ‘450

application, and only first appeared in response to a first office action from the

Examiner rejecting the claims. (Ex. 1006, pp. 216-219 (original claims); p. 29

(claim 23).) My understanding is that the applicants ultimately did not pursue that

claim in the ‘450 application. (See Ex. 1006, at 14-17 (restriction requirement), and

13 (election without claim 23).) However, the ‘450 application as the older

application actually included a claim specific to the thickness of a “first electrode

portion”, and the applicants made similar arguments as discussed above with

respect to the external electrode discussion in specification. (Id. at 27 (claim 14 –

“wherein said first electrode portion has a thickness in the range of 10 μm to 20

μm”) and at 31-33 (applicants’ argument) (“One of the features of the present

invention resides in that an electrode portion has a thickness in the range of 10 m

to 20 m”) (emphasis added).) Here, those arguments made at least some logical

sense, as the discussion in the common specification related to at least the claim

specific to the “first electrode portion” thickness, and the claim did not include any

“diffusion layer” language. By contrast, the same cannot be said of the same

Exhibit 100200024

Exhibit 1002

25

arguments that were made with respect what ultimately issued as the limitation of

claim 10, relating to the “combined thickness,” which further highlights that one of

skill in the art would have difficulty discerning the boundaries of that claim, as

discussed below.

C. Background of WLCSP Technology at the Time of the ‘001 Patent

40. The approaches described in the ‘001 patent are examples of Wafer

Level Chip Scale Package (WLCSP) technologies. As described by Lau in his

reference book from the year 2000 (Ex. 1003, Section 1.3.6), WLCSPs typically

feature the use of metal layers (wiring) to redistribute fine pitch peripheral

pads/contacts on the semiconductor chip to larger area-array pads attached to

solder balls (external electrodes). These solder balls are subsequently used to form

solder joints that connect the WLCSP to a printer circuit board (PCB).

41. WLCSP technologies were first developed in the 1990s, and

numerous variations were available and publically disclosed by the year 2000

(before the filing of the ‘001 patent) as explained by Lau (Ex. 1007) (Lau, J. H.,

“Wafer Level Packaging,” Chapter 10, Low Cost Flip Chip Technologies for DCA,

WLCSP, and PBGA Assemblies, 2000). As illustrated with several examples in

Ex. 1007 (e.g. Figures 10.2, 10.3, 10.4, 10.8, 10.20, 10.25, 10.49), several WLCSP

technologies were already in existence in the year 2000 that involved

Exhibit 100200025

Exhibit 1002

26

semiconductor chips that were processed to include thin passivation films,

redistribution layers (RDLs), copper wiring (traces), insulating films, encapsulant

(resin) layers, copper plugs/pillars, and Sn-based solder balls, which are all

elements discussed in the technology of the ‘001 patent.

42. As illustrated by the figures below, additional examples of WLCSP

configurations similar to those illustrated in Figure 2 of the ‘001 patent were given

in 1999, e.g. (Figure 30.1 from Ex. 1008, Lau, J. H. and Lee, S. W. R. “EPIC’s

Chip Scale Package,” Chapter 30, Chip Scale Package Design, Materials. Process,

Reliability, and Applications, 1999) and (Figure 32.1 from Ex. 1009, Lau, J. H.

and Lee, S. W. R. “Fujitsu’s SuperCSP (SCSP),” Chapter 32, Chip Scale Package

Design, Materials. Process, Reliability, and Applications, 1999).

Exhibit 100200026

Exhibit 1002

27

43. Another common feature in many WLCSP technologies is the use of

an Under Bump Metallization (UBM), which typically consisted of 1-3 thin layers

of metal used as intermediate layers when connecting one conducting metal

element to another (e.g connecting copper wiring to the aluminum bond pads on a

semiconductor chip, or connecting Sn-based solders to aluminum bond pads on a

semiconductor chip). Typical purposes of the UBM layers included improving

adhesion/bonding and/or establishing a diffusion barrier to prevent undesirable

chemical reactions. In all cases, the use of an UBM had the purpose to improve

the reliability of the WLCSP when exposed to elevated temperatures or thermal

cycling.

D. Background on Soldering at the Time of the ‘001 Patent

44. Soldering and the use of solder balls/bumps as the external

interconnects for WLCSPs were well established at the time of the Dec 2001 filing

of the ‘001 patent related Japanese application (e.g., Ex. 1007, Lau, J. H., “Wafer

Exhibit 100200027

Exhibit 1002

28

Level Packaging,” Chapter 10, Low Cost Flip Chip Technologies for DCA,

WLCSP, and PBGA Assemblies, 2000). When Sn-based solders are reflowed

directly to copper surfaces, Sn-Cu Intermetallic Compound (IMC) layers form at

the interface between the remaining copper and Sn-based material.

45. The presence and growth of IMC layers has been well understood in

the field semiconductor packaging for at least forty years, e.g. (Ex. 1010,

Zakraysek, “Intermetallic Growth in Tin-Rich Solders,” pp. 536s-541s, Welding

Research Supplement, 1972). It was also well known that IMC/diffusion layers

between Cu and Sn-based materials will be irregular with a non-constant thickness,

(see Id. at p. 539s), and that the chemical composition of the two primary Cu-Sn

compounds making up the IMC layers are Cu6Sn5 and Cu3Sn (see Id. at p. 538s

and p. 541s). The Zakraysek publication also lists typical thicknesses of IMC

layers developed by short term and long term thermal exposures (see Id. at Table 2,

p. 539s). For temperature levels at or less than 125 oC, typical IMC layer

thicknesses were in the range of 1.0 to 2.7 μm for short term exposures up to 8

hours, and from 1.0 to 6.5 μm for long term thermal exposures up to 32 days.

IV. Detailed Explanation Of Claim Terms

46. As noted above, I understand that claims in an inter partes review are

given their broadest reasonable interpretation that is consistent with the patent

Exhibit 100200028

Exhibit 1002

29

specification, and the understanding of one of skill in the art (as I defined above).

In this regard, counsel asked me to provide certain information to assist in

determining the legal scope of certain of the ‘001 patent’s terms, which I provide

below. In the absence of a specific further explanation in this declaration of any

term found in any of claims 1-18, I presumed the term to take on its broadest

ordinary meaning to a person of ordinary skill in the art.

A. “electrode” (claims 1-18)

47. As a matter of clarification, it is my opinion that the term “electrode”

to one of skill in the art at the time of the ‘001 patent, would mean “a conductor

used to establish electrical contact with a nonmetallic portion of a circuit.” (Ex.

1011 at page 4.) In the context of the ‘001 patent, the nonmetallic portion of the

electrical circuit is the semiconductor element itself, and each of the three

"electrodes" are used to establish contact with the semiconductor element in the

claims. Nothing in the specification would change my understanding of that term,

and I apply this understanding of that claim term in my analysis below.

B. “electrode portion” (claims 1-18)

48. As distinct from “electrode,” the ‘001 patent claims also refer to a

number of “electrode portions” (first, second, and third “electrode portions”).

Here again, as a matter of clarification, one of skill in the art at the time of the ‘001

Exhibit 100200029

Exhibit 1002

30

patent would consider this term to refer to any portion of a first, second, or third

electrode, or all of it. The ‘001 patent confirms this, as its specification

consistently refers to its wiring 14, including the “metal-material embedded

portion” (or portions), connected to a solder ball electrode, as an external electrode

portion which is claimed in the ‘001 patent as a “first electrode portion.” I apply

this understanding of that claim term in my analysis below.

C. “metal component” (claims 1-18)

49. As a matter of clarification, it is my opinion that the term “metal

component” would have been understood by one of skill in the art at the time of

the ‘001 patent to mean “an element of the periodic table considered a metal.”

Nothing in the specification would change my understanding of that term, and I

apply this understanding of that claim term in my analysis below.

D. “diffusion layer formed between said first electrode portion and said second electrode portion” (claims 1-18)

50. In the context of the ‘001 patent, a “diffusion layer” refers to an

intermetallic layer formed between two metals. As used in the claims, it is an

intermetallic layer formed between the first electrode portion and the second

electrode portion, which are comprised of first and second metal components,

respectively.

Exhibit 100200030

Exhibit 1002

31

51. The ‘001 patent provides an example of an intermetallic compound

that constitutes a “diffusion layer” in the context of Tin(Sn)-containing solder that

is applied to an electrode that contains copper (Cu). (Ex. 1001, 8:63-9:1 (“Sn

contained in solder of the ball electrode 16 diffuses into Cu contained in the metal

wiring 14, whereby a Sn—Cu alloy layer having low strength grows in the

thickness direction of the external electrode portion 14a”).) As set forth above, Sn-

Pb solder, as a Tin(Sn)-containing solder, was previously used widely in the

microelectronics industry, but more recently has been largely replaced by various

lead free solders. It was commonly known and understood that intermetallic

compounds are formed when molten Sn-Pb solder is applied to and reacts with a

surface containing Cu. The reaction results in Sn-Cu compounds at the interface of

the remaining Sn-based solder and copper materials.

52. In view of the foregoing, counsel has informed me that if an

appropriate “broadest reasonable interpretation” can be applied to “diffusion

layer,” it would be “an intermetallic compound formed between said first electrode

portion and said second electrode portion.” I apply this understanding of that

claim term in my analysis below.

Exhibit 100200031

Exhibit 1002

32

E. “said first electrode portion and said diffusion layer have a combined thickness in the range of 10 m to 20 m” (claims 10-18)

53. The ‘001 patent only describes intermetallic compound formation in

the direction of its external electrode (i.e., its first electrode portion), and there is

no discussion of such intermetallic formation in the solder ball electrode (i.e.,

second electrode portion), even though a person of skill in the art would

understand that intermetallic compounds would also form in the solder ball. (See

e.g., Ex. 1001, 8:63-9:1.) With that in mind, it would be unclear to one of skill in

the art where the “diffusion layer” actually starts and ends, which is significant

when attempting to identify the “combined thickness” that is claimed.

54. Along the same lines, as discussed extensively in the background

section I provided, the ‘001 patent offers no discussion of the claimed “combined

thickness,” and instead all of its discussion of thicknesses in the range of “10 m to

20 m” are solely to the external electrode portion (i.e., “first electrode portion”).

(See e.g., Ex. 1001, 4:19-20 (“Preferably, the thickness of the external electrode

portion is in the range of “10 m to 20 m”), 8:39-42, 9:36-40, and 20:14-17).)

There is no discussion of the thickness of the “diffusion layer” anywhere in the

‘001 patent, except for in claim 10 itself.

55. Further, as discussed above in the background I have provided, the

intermetallic layers themselves are irregular in all dimensions, and have non-

Exhibit 100200032

Exhibit 1002

33

uniform thickness. So, one of skill in the art would have to guess what was meant

by “combined thickness” when considering the intermetallic.

56. Accordingly, if an appropriate “broadest reasonable interpretation”

can be applied here, it would be “said first electrode portion and said diffusion

layer have a combined thickness in the range of 10 m to 20 m, measuring the

maximum and minimum thickness.” I apply this understanding of that claim term

in my analysis below.

F. “flush with or higher than a surface of the insulating film” (claims 5 and 14)

57. The ‘001 patent itself offers an explanation of what is meant by the

term “flush with” in stating that “in the specification, the term ‘flush’ also includes

‘approximately flush.’” (Ex. 1001, 10:24-25.) In addition, the ‘001 patent explains

that its “insulating film” may be a solder resist. (See e.g., Ex. 1001, 11:65-67.)

One of skill in the art would have appreciated that solder resist is typically formed

slightly higher than the pad onto which a solder ball is intended to be attached, to

assist in directing that solder ball material to the pad prior to reflow. (See e.g., Ex.

1007 at Fig. 10.20 (at right side of Fig. 10.20 noting “10 μm MIN (over copper)”

where copper refers to the pad).

Exhibit 100200033

Exhibit 1002

34

58. In view of the foregoing, counsel has informed me that a “broadest

reasonable interpretation” of this term would be “approximately flush with or

higher than a surface of the insulating film.” I apply this understanding of that

claim term in my analysis below.

G. Preamble of Independent Claims 1 and 10

59. I am informed that interpretation of the “preamble” or introductory

phrase of a “semiconductor device” of independent claims 1 or 10 is a legal issue

that depends on whether it would be considered a limitation of the claims.

However, because all of the prior art I have analyzed shows the feature of the

common “preamble,” this issue has no ultimate effect on my analysis presented

below

V. Analysis of the Prior Art

60. Below, I provide my analysis of the prior art against claims 1-18 of

the ‘001 patent. All emphasis is added to quotations, unless stated otherwise.

A. PCT Publication No. WO00/52755 (“Narizuka”)

61. Narizuka is provided as Ex. 1012, which includes a translation of that

publication from Japanese to English. References below are to the English

translation. The corresponding U.S. Patent (‘372 patent) is provided as Ex. 1013.

Exhibit 100200034

Exhibit 1002

35

62. Narizuka describes a semiconductor device with a semiconductor

element that includes an electrode connected to a solder ball through an offset

wiring configuration. In particular, Narizuka states: “Next, as shown in FIG. 4, a

connection structure between a wiring and a solder, which is one example of

embodiment of a semiconductor device according to the present invention will be

described. Assume that the substrate 11 is a Si wafer, the insulating layer 15 is a

polyimide layer, the wiring 13 consists of three layers of Cr thin film layer 13b

(about 0.1 m in thickness), a Cu layer 13 a, and a Cr thin film layer 13c (about

0.05 m), the protective film 16 is a polyimide film, and the solder is a Pb-free Sn-

3Ag type solder.” (Ex. 1012, 12:6-10.) Fig. 4 is provided below.

63. Fig. 3(d) shows another view of Narizuka’s wiring and solder ball

configuration, which is provided below.

Exhibit 100200035

Exhibit 1002

36

64. Narizuka also describes a “diffusion layer” in the form of a Sn-Cu

intermetallic compound: “the connection can basically be achieved by the alloy

17a of Sn and Cu (Sn-Cu intermetallic compound), and the solder can reach the

under layer 13b of Cr or Ti and the solder can connect to the under layer 13b of Cr

or Ti, thereby the connection strength and reliability can be secured.” (Ex. 1012,

11:18-12:2.) The intermetallic compound of Narizuka is illustrated in Fig. 1,

which is provided below.

Exhibit 100200036

Exhibit 1002

37

B. Narizuka Describes The Content Of Claims 1-18

65. It is my opinion that Narizuka alone describes the content of each of

claims 1-18. Below, I explain the correlation between aspects of Narizuka and

those claims of the ‘001 patent.

1. Narizuka: Independent Claim 1

66. Independent claim 1 includes four parts (designated (a) through (d))

and a “preamble,” and I address each of those parts in turn below.

(1) Claim 1: Preamble: (A semiconductor device)

67. Narizuka describes and illustrates a “semiconductor device,” by way

of Fig. 4 and its accompanying explanation. (Ex. 1012, 12:6-10 (“Next, as shown

in FIG. 4, a connection structure between a wiring and a solder, which is one

example of embodiment of a semiconductor device according to the present

invention will be described. Assume that the substrate 11 is a Si wafer, the

insulating layer 15 is a polyimide layer, the wiring 13 consists of three layers of Cr

thin film layer 13b (about 0.1 m in thickness), a Cu layer 13 a, and a Cr thin film

layer 13c (about 0.05 m), the protective film 16 is a polyimide film, and the

solder is a Pb-free Sn-3Ag type solder”.) Narizuka also explains that its

description and figures are in relation to both a wiring board and a semiconductor

Exhibit 100200037

Exhibit 1002

38

device, so its descriptions are all applicable to a semiconductor device such as the

one shown in Fig. 4. (See Ex. 1012, 6:18-19.)

(2) Claim 1: Element (a): (a semiconductor element)

68. The semiconductor device of Narizuka includes a “semiconductor

element” as Si wafer 11. (Ex. 1012, 12:6-10 (quoted above).) An annotated

version of Fig. 4 is provided below identifying the semiconductor element.

(3) Claim 1: Element (b): (a first electrode portion formed on the semiconductor element, said first electrode portion comprising a first metal component)

69. The semiconductor device of Narizuka also includes a “first electrode

portion” formed on its semiconductor element that is made of a “first metal

component,” in two different configurations. To show the first configuration,

Exhibit 100200038

Exhibit 1002

39

annotated versions of Figs. 1 and 3(d)2 are provided below highlighting its “first

electrode portion.”

2 Notably, there is an error in Figs. 3(c) and 3(d) of Ex. 1012 insofar as the

last portion of the wiring, Cr portion 13c, is drawn, even though the specification

makes clear that portion of the wiring is removed so the solder ball 17 contacts Cu

portion 13a. When the last Cr layer 13c is removed, it allows the Sn-containing

solder ball 17 to contact the Cu layer 13a. (See Ex. 1012, 10:19-20 (“…the upper

layer of the Cr film 13c is removed only for the portion of the opening 19 of the

protective film 16 to expose the Cu layer 13a.”); see also 5:11-14.) The error was

fixed in the corresponding U.S. Patent. (See Ex. 1013 at 3(c) and 3(d)).

Exhibit 100200039

Exhibit 1002

40

70. In this first configuration, Narizuka’s first electrode portion is the

portion of its wiring 13 (13a and 13b) that is located under the solder ball (second

electrode portion). As stated by Narizuka: “Next, as shown in FIG. 4, a connection

structure between a wiring and a solder, which is one example of embodiment of

a semiconductor device according to the present invention will be described.

Assume that the substrate 11 is a Si wafer, the insulating layer 15 is a polyimide

layer, the wiring 13 consists of three layers of Cr thin film layer 13b (about 0.1

m in thickness), a Cu layer 13 a, and a Cr thin film layer 13c (about 0.05 m),

the protective film 16 is a polyimide film, and the solder is a Pb-free Sn-3Ag type

solder.” (Ex. 1012, 12:6-11; see also 5:12-14 (discussing exposing outer Cu

portion for connection to solder ball 17), and 8:14-17 (discussing Cr or Ti for layer

13b.). So, the Cr/Cu or Ti/Cu (13b and 13a) portion of Narizuka’s wiring where

the outer layer of Cu is exposed for connection to solder ball 17 is its “first


Exhibit 100200040

Exhibit 1002

41

71. Narizuka explains that its Cr/Cu or Ti/Cu wiring portion is considered

a type of “UBM” or “Under Bump Metal,” at the portion of the wiring where the

solder ball is attached to the Cu. (Ex. 1012, 12:12-13 (“…as shown by the

sectional structure of a UBM (under bump metal) end, the solder diffuses

through the Cu layer and reaches the Cr (Ti) layer 13b”).) Thus, in addition to the

configuration shown in Figs. 1 and 3(d), Narizuka also includes a configuration

where its “UBM” (Cr/Cu or Ti/Cu) can be placed atop an existing wire as an

electrode. As explained by Narizuka: “Although the case where the solder 17 is

directly connected to the wiring 13 connected to the electrode 12 in the above-

mentioned embodiment has been described, another wiring layer that connects

between the electrode 12 and the wiring 13 may also be provided. In this case, the

wiring 13 is formed in the form of an electrode. However, providing another

wiring layer increases the process for that portion.” (Ex. 1012, 14:11-14.) Fig. 8

shows in-part what Narizuka describes where its Cr/Cu or Ti/Cu “UBM” is placed

atop an existing wire for connection to a solder ball, as reproduced below (portion

of Fig. 8).

Exhibit 100200041

Exhibit 1002

42

72. Here, the illustration in Fig. 8 is for “when an electrode 12 is formed

in advance on a substrate in an arrangement suitable for its connection, it is not

necessary to form a wiring 13” (Ex. 1012, 14:16-17), and not the offset

arrangement referred to in the passage above, which is why I stated Fig. 8 only

shows in-part what Narizuka describes where its Cr/Cu or Ti/Cu “UBM” is placed

atop an existing wire. To further clarify what Narizuka actually explains to one of

skill in the art, I have prepared the following modification of Fig. 3(c), illustrating

what Narizuka is stating by “another wiring layer that connects between the

electrode 12 and the wiring 13 may also be provided. In this case, the wiring 13 is

formed in the form of an electrode.” The modification includes addition of the

Cr/Cu or Ti/Cu “UBM” to the existing wiring along with a solder ball. The “first

electrode portion” in the second configuration is the “UBM” in combination with

the portion of the existing wire underneath the “UBM.” Although not shown in the

Fig. presented below, the last Cr portion of wiring 13c underneath the added

“UBM” would not be present, consistent with Narizuka’s explained existing

process to remove that layer during processing. (See Ex. 1012, 10:19-20 (“…the

upper layer of the Cr film 13c is removed only for the portion of the opening 19 of

the protective film 16 to expose the Cu layer 13a.”).)

Exhibit 100200042

Exhibit 1002

43

73. So, Narizuka describes two different configurations of a “first

electrode portion” including Cu as its “first metal component.” Notably, the

composition of Narizuka’s Cr/Cu/Cr or Ti/Cu/Cr wiring correlates directly with

what the ‘001 patent states about the composition of its wiring. (See e.g., Ex. 1001,

12:57-63 (“Note that, in the second embodiment, the material of the metal wirings

14 is not specifically limited. For example, a material mainly containing Cu, Ti, W,

Cr, Al or the like may be used. Alternatively, another conductive metal material

may be used”).)

Exhibit 100200043

Exhibit 1002

44

(4) Claim 1: Element (c): (a second electrode portion formed on the semiconductor element and electrically connected to said first electrode portion, said second electrode portion comprising a second metal component different from said first metal component)

74. In Narizuka, the “second electrode portion” is solder ball 17.

Annotated versions of Fig. 1 and modified Fig. 3(c) (introduced directly above)

show that “second electrode portion” relative to the “first electrode portion,” in

both configurations of Narizuka.

Exhibit 100200044

Exhibit 1002

45

75. Narizuka explains that its solder ball 17 includes Sn as the “second

metal component.” (See Ex. 1012, 4:7-8 (“The solder for the outer connection of

the wiring board in the present invention is characterized by being formed with a

solder containing Sn.”); see also 10:21-11:2, 12:3-5, and 12:10.)

(5) Claim 1: Element (d): (a diffusion layer formed between said first electrode portion and said second electrode portion, wherein said diffusion layer comprises said first metal component and said second metal component)

76. In Narizuka, a “diffusion layer” (i.e., an intermetallic compound) is

formed between the solder ball 17 and the Cu portion of the wiring (portion 13a).

This diffusion is found in both the first of Narizuka’s configurations where the

solder ball 17 is directly connected to wiring 13, and in the second configuration

where the wiring “UBM” is placed atop to an existing wire as an electrode and the

solder ball 17 is attached to that “UBM” (as discussed above for claim limitation

Exhibit 100200045

Exhibit 1002

46

1(a)). Fig. 1 of Narizuka shows the formation of the intermetallic compound after

the solder ball 17 is reflowed, and Narizuka explains the intermetallic formation as:

“the connection can basically be achieved by the alloy 17a of Sn and Cu (Sn-Cu

intermetallic compound), and the solder can reach the under layer 13b of Cr or Ti

and the solder can connect to the under layer 13b of Cr or Ti, thereby the

connection strength and reliability can be secured.” (Ex. 1012, 11:18-12:2; see also

Abstract; 5:8-14.) Here, one of skill in the art would have appreciated that at least

some Cu remains in Narizuka’s “first electrode portion” in non-intermetallic form,

even if its solder ball 17 is reflowed to “reach and connect with the under layer 13b

of Cr or Ti.” Indeed, Narizuka explains that during a shorter reflow, where the

solder diffuses through the Cu layer and reaches the Cr (Ti) layer 13b, a portion of

Cu remains. (See Ex. 1012, 12:12-17 (“When the reflow temperature is about

250ºC, and the reflow time is one minute, as shown by the sectional structure of a

UBM (under bump metal) end, the solder diffuses through the Cu layer and

reaches the Cr (Ti) layer 13b, but since the Cu layer still remains, a large amount

of Sn, which is the main component of the solder, can be seen adjacent to the

position that shows the peak of Cr, and on the contrary, only a small amount of Cu

in the Cu layer 13a remains according to EDX (energy dispersive X-ray

spectroscopy) line analysis”).)

Exhibit 100200046

Exhibit 1002

47

2. Narizuka: Dependent Claim 2 (The semiconductor device of claim 1, wherein said first metal component includes copper and said second metal component includes tin)

77. I explained above how Narizuka describes the features of independent

claim 1. As discussed, Narizuka’s wiring, in either configuration as a “first

electrode portion” includes Cu as its “first metal component.” (See Ex. 1012, 12:6-

11; 5:8-14.) As also explained above, Narizuka’s solder ball 17 (i.e., the “second

electrode portion”) includes Sn as its “second metal component.” (See Ex. 1012,

4:7-8 and 12:10.)

3. Narizuka: Dependent Claim 3 (The semiconductor device of claim 1, further comprising a third electrode portion formed on a surface of the semiconductor element and a metal wiring formed on the semiconductor element, said metal wiring electrically connecting the first electrode portion to the third electrode portion)


claim 1. In addition, Narizuka includes a “third electrode portion” and “metal

wiring” electrically connecting the first electrode portion to the third electrode

portion as its electrode 12 on the surface of its semiconductor element (Si wafer

11) which is connected to wiring 13. The portion of wiring 13 not included in the

“first electrode portion,” in either of Narizuka’s configurations (solder ball 17

directly on wiring or attached to wiring “electrode” “UBM”), connects electrode

12 (third electrode portion) to the first electrode portion. As stated by Narizuka:

Exhibit 100200047

Exhibit 1002

48

“The solder for the outer connection of the wiring board in the present invention is

configured so as to be directly connected to the wiring layer connected to the

electrode on a substrate.” (Ex. 1012, 4:11-13; see also 5:8-14 (wiring, electrode,

and solder specific to “semiconductor device”), Abstract, and 8:5-11.)

79. Annotated versions of Figs. 1 and 3(d) provided below illustrate

Narizuka’s third electrode portion and metal wiring electrically connecting it to

Narizuka’s first electrode portion, in the first Narizuka configuration where solder

ball 17 is directly connected to the wiring.

Exhibit 100200048

Exhibit 1002

49

80. In addition to the figures above, I have also similarly annotated the

modification of Fig. 3(c) showing the second configuration of Narizuka, which

includes addition of the Cr/Cu or Ti/Cu “UBM” to the existing wiring to form the

first electrode portion underneath the solder ball.

4. Narizuka: Dependent Claim 4 (The semiconductor device of claim 3, wherein the first and

Exhibit 100200049

Exhibit 1002

50

third electrode portion are horizontally spaced apart with respect to the semiconductor element)

81. As shown directly above with respect to claim 3, in either of

Narizuka’s configurations (solder ball 17 directly on wiring or solder ball attached

to “UBM” on top of wiring), the first and third electrode portions are horizontally

spaced apart with respect to its semiconductor element.

5. Narizuka: Dependent Claim 5

82. Dependent claim 5 includes three parts, which I have designated as

parts (a) through (c), and I address each of those parts in turn below.

(1) Claim 5: Element (a): (The semiconductor device of claim 3, further comprising an insulating film formed on said metal wiring)

83. I explained above how Narizuka describes the features of dependent

claim 3. In addition, Narizuka also describes an “insulating film” over its wiring

13 as its protective or insulation film 16. As stated by Narizuka: “a protective

film covering the wiring and having a hole for a solder connection opened

therein, and a solder for the outer connection mounted on a hole for a solder

connection opened in the protective film and formed by diffusing (diffusion-

alloying) the Cu layer in the wiring and bringing it to reach the Cr or Ti layer to

establish a connection.”) (Ex. 1012, 5:11-14; see also 10:18-20 (“In this state, the

protective film (insulation film) 16 serves as a mask when immersed in the

Exhibit 100200050

Exhibit 1002

51

etching solution of Cr, and as shown in FIG. 3(c), the upper layer of the Cr film

13c is removed only for the portion of the opening 19 of the protective film 16 to

expose the Cu layer 13a”.) The protective film (insulation film) 16 is also

described as a polyimide film (Ex. 1012, 12: 9-10). One of ordinary skill in the art

would have appreciated that the protective film described by Narizuka is an

organic material such as a polyimide, and thus must be an insulator, and thus

performs the same function as the insulating film in the ‘001 patent, particularly

given its location over wiring 13.

84. I have annotated the modification of Fig. 3(c) to demonstrate

Narizuka’s insulating film location in the second configuration, which includes

addition of the Cr/Cu or Ti/Cu “UBM” to the existing wiring to form the first

electrode portion underneath the solder ball. Narizuka’s second configuration

shows the features of this claim 5, including the requirement of element (c) that the

“first electrode” be “flush with or higher than a surface of the insulating film.”

Exhibit 100200051

Exhibit 1002

52

(2) Claim 5: Element (b): (wherein an opening of said insulating film exposes a surface of the first electrode portion)

85. Narizuka’s insulating film includes an opening to expose a surface of

its first electrode portion. As stated by Narizuka: “a protective film covering the

wiring and having a hole for a solder connection opened therein, and a solder

for the outer connection mounted on a hole for a solder connection opened in the

protective film and formed by diffusing (diffusion-alloying) the Cu layer in the

wiring and bringing it to reach the Cr or Ti layer to establish a connection.”) (Ex.

1012, 5:11-14; see also 10:18-20, and Abstract.)

86. In Narizuka’s second configuration, the “UBM” as an electrode is

placed within the opening made in Narizuka’s insulating film, thus exposing the

surface of its first electrode portion. I have annotated the modification of Fig. 3(c)

to show that opening.

Exhibit 100200052

Exhibit 1002

53

(3) Claim 5: Element (c): (and wherein said surface of the first electrode portion is flush with or higher than a surface of the insulating film)

87. In Narizuka’s second configuration, its first electrode portion is higher

than a surface of its insulating film 16, as shown in the annotation of the

modification of Fig. 3(c), below.

6. Narizuka: Dependent Claim 6 (The semiconductor device of claim 3, wherein the metal wiring includes copper)


claim 3. In addition, Narizuka explains that its metal wiring includes Cu. (See Ex.

1012, 5:8-14; 12:6-11.)

7. Narizuka: Dependent Claim 7

89. Dependent claim 7 includes two parts, which I have designated as

parts (a) and (b), and I address each of those parts in turn below.

Exhibit 100200053

Exhibit 1002

54

(1) Claim 7: Element (a): (The semiconductor device of claim 3, further comprising an insulating resin layer formed between the surface of the semiconductor element and the metal wiring)


claim 3. In addition, Narizuka also describes an “insulating resin layer” between

the surface of its semiconductor element and its metal wiring in the form of its

insulation layer 15. As explained by Narizuka: “The insulating layer 15 relaxes

the stress added to the portion of the solder 17 due to a difference in the thermal

expansion, etc., between the substrate 11 and a package board, which is an external

circuit.” (Ex. 1012, 8:12-13; see also 5:16-17 (“Furthermore, the present invention

is also characterized in that the insulating layer of the semiconductor device

contains an organic resin layer.”); Fig. 1 (“Stress Relaxation Layer” 15), Abstract,

5:8-14 (explanation specific to “semiconductor device”), 8:5-11, and 12:6-11

(explanation specific to “semiconductor device”).) Thus, Narizuka’s insulating

layer 15 as an “insulating resin layer” performs the same function of stress

absorption/relaxation as the ‘001 patent’s “insulating resin layer,” and is also

described as being made of an “organic resin layer.” (See Ex. 1001, 12:16-36

(discussing ‘001 patent “insulating resin layer” alleged “effects”).)

Exhibit 100200054

Exhibit 1002

55

91. Annotated versions of Figs. 1 and 3(d) provided below illustrate

Narizuka’s insulating resin layer, in the first configuration where solder ball 17 is

directly connected to the wiring.

92. I have similarly annotated the modification of Fig. 3(c) to demonstrate

Narizuka’s insulating resin layer location in the second configuration, which

Exhibit 100200055

Exhibit 1002

56

includes addition of the Cr/Cu or Ti/Cu “UBM” to the existing wiring to form the

first electrode portion underneath the solder ball.”

(2) Claim 7: Element (b): (wherein the metal wiring is formed along a surface of the insulating resin layer)

93. As shown by the annotated Figs. directly above, Narizuka’s metal

wiring (the portion of the wiring that is not part of the “first electrode portion”) is

formed along a surface of its insulating resin layer, in both configurations.

94. The fact that Narizuka as prior art discloses such an “insulating resin

layer” is confirmed by the ‘001 patent itself, which states that an insulating resin

layer and metal wiring formed along a surface of that insulating resin layer is prior

art, and known in conventional semiconductor devices. (See Ex. 1001, prior art

Fig. 15C and 2:1-3.)

8. Narizuka: Dependent Claim 8 (The semiconductor device of claim 3, wherein the metal wiring has a thickness in the range of 0.01 m to 8 m)

Exhibit 100200056

Exhibit 1002

57


claim 3. In addition, Narizuka explains that its metal wiring may have a thickness

within the range of “0.01 m to 8 m.” As stated by Narizuka: “The wiring 13

according to the present invention is formed by laminating a Cu layer 13a with a

thickness of about 0.1-10 m, which is practically the lowest resistance material,

into the portion that connects to an external circuit; a Cu or Ti thin film layer 13b

with a thickness of about 0.05-1.0 m on the under layer 15 side; a Cr thin film

layer 13c with a thickness of about 0.01-0.3 m thick on the protective film 16

side.” (Ex. 1012, 8:14-17; see also 4:8-9.) The “metal wiring” in both

configurations of Narizuka is the portion of wiring 13, including each of 13a, 13b,

and 13c, that is not the first electrode portion. Here, neither claim 8, nor any claim

from which it depends, claims any particular significance to the claimed range.

9. Narizuka: Dependent Claim 9 (The semiconductor device of claim 1, further comprising a substrate having a wiring electrode, wherein said wiring electrode is electrically connected to said second electrode portion)


claim 1. In addition, Narizuka explains that its semiconductor device is connected

to a package or wiring board (substrate) through its solder balls (second electrode

portion) to electrodes on that package or wiring board. (See Ex. 1012, 8:12-13

(“The insulating layer 15 relaxes the stress added to the portion of the solder 17

Exhibit 100200057

Exhibit 1002

58

due to a difference in the thermal expansion, etc., between the substrate 11 and a

package board, which is an external circuit”; 16:14-18 (“By connecting and

mounting the solder of the wiring board or the semiconductor device according to

the present invention described above to the electrode of a substrate, etc., an

electronic apparatus or semiconductor device package structure can be

constituted. Even if a further finer wiring and advanced multi-layering are

strongly desired along with the need for higher performance and multi-functioning

of electronic apparatuses and semiconductor device package structures, it is

possible to secure the function of the connection part with the outside”).)

10.Narizuka: Independent Claim 10

97. The text of independent claim 10 is identical to that of independent

claim 1 except for the additional element of “said first electrode portion and said

diffusion layer have a combined thickness in the range of 10 m to 20 m.” So, I

incorporate by my earlier analysis provided in paragraphs 66-76 here, without

repeating it.

98. As to the additional element, Narizuka explains that the Cu portion of

its wiring 13a ranges in thickness between 0.1 to 10 microns, and the Cr or Ti

portion of its wiring 13b ranges in thickness between 0.05 and 1 microns. (See Ex.

1012, 8:14-15.)

Exhibit 100200058

Exhibit 1002

59

99. In the first Narizuka configuration, where the solder ball 17 is

connected directly to the wiring, if the Cu portion 13a has a thickness of 10 m ,

and the Cr or Ti portion 13b has any thickness between 0.05 and 1 m, then

thickness of the wiring alone would be in the range of 10-11 m. Thus, the

“combined thickness” of the “diffusion layer” (i.e., the intermetallic formed

between the Cu portion of the wiring 13a and the solder ball) and the “first

electrode portion” (wiring portions 13a and 13b together) would be at least 10-11

m.

100. As discussed above in paragraph 45, one of ordinary skill in the art

would also have appreciated that any intermetallic layer (diffusion layer) present

would be irregular in shape, as also illustrated in exaggerated form in Narizuka’s

Fig. 1. One of skill would also recognize that the thickness of such an intermetallic

layer (diffusion layer) would typically be just a few microns for typical thermal

exposures used in assembling a WLCSP. (e.g., see Ex. 1010, Table 2, where Cu-

Sn IMC thicknesses were below 3 m for short thermal exposures (hours) at

temperatures up to 125 oC, and were below 6 m for longer thermal exposures

(days) at temperatures up to 125 oC ). Using an upper bound IMC layer thickness

of 6 m, the combined thickness of the first electrode portion (wiring, 10-11 m)

and diffusion layer (IMC layer, 0-6 m) in the first Narizuka configuration would

Exhibit 100200059

Exhibit 1002

60

be in the range of 10-17 m, which falls within the 10 m to 20 m range in

independent claim 10.

101. The same type of analysis can be performed for Narizuka’s second

configuration, where its wiring “UBM” is placed atop an existing wire as an

electrode, and the solder ball is attached to that “UBM.” In that configuration, the

existing wire would not include the last Cr layer 13c, as discussed above in relation

to the “first electrode portion” and the introduction of the second configuration. In

the second configuration, where the Cu portions 13a of the existing wire and the

wiring “UBM” electrode have a total thickness of 5 + 5 = 10 m, and the Cr or Ti

portions 13b of the existing wire and the wiring “UBM” electrode have a total

thickness between 0.1 and 2 m, the thickness of the wiring and wiring UBM

together would be in the range of 10-12 m. Again using an upper bound IMC

layer thickness of 6 m, the combined thickness of the first electrode (wiring and

wiring UBM, 10-12 m) and the diffusion layer (IMC layer, 0-6 m) in the second

Narizuka configuration would be in the range of 10-18 m, which again falls

within the 10 m to 20 m range in independent claim 10.

11.Narizuka: Dependent Claim 11

102. The text of dependent claim 11 is the same as dependent claim 2, so I

incorporate my earlier analysis provided in paragraph 77, without repeating it here.

Exhibit 100200060

Exhibit 1002

61



incorporate my earlier analysis provided in paragraphs 78-80, without repeating it

here.







here.







here.

Exhibit 100200061

Exhibit 1002

62

17.Narizuka: Dependent Claim 17 (The semiconductor device of claim 12, wherein the metal wiring has a thickness in the range of 0.01 m to 8 m)

108. The text of claim 12, from which this claim depends, is the same as

claim 3, so I incorporate my earlier analysis provided in paragraphs 78-80. As to

the thickness of the metal wiring, Narizuka explains that the Cu portion of its

wiring 13a ranges in thickness between 0.1 to 10 m, the Cr or Ti portion of its

wiring 13b ranges in thickness between 0.05 and 1 m, and the last Cr portion 13c

ranges in thickness between 0.01 to 0.3 m. (See Ex. 1012, 8:14-17)

109. As discussed extensively above, in Narizuka’s second configuration,

its wiring “UBM” is placed atop an existing wire as an electrode and the solder ball

is attached to that “UBM.” As also explained above, the “metal wiring” in that

configuration of Narizuka is the full portion of wiring 13, including each of 13a,

13b, and 13c, that is not the first electrode portion. Here, I set forth an example

within the explained thickness ranges of Narizuka in my discussion of claim 10, in

which the existing wire as the “metal wiring” would have a thickness of 5 m for

portion 13a, and any thickness between 0.05 and 1 m for portion 13b. Now,

adding the Cr portion 13c, even at the maximum thickness, the total maximum

thickness in that example is just over 6 m, which is within the range of claim 17.


Exhibit 100200062

Exhibit 1002

63



C. German Patent Publication No. DE 100 11 368 (“Takizawa”)

111. Takizawa is provided as Ex. 1014, which includes a translation of that

publication from German to English. References below are to the English

Translation.

112. Takizawa describes a semiconductor device with a semiconductor

element that includes an electrode connected to a solder ball through an offset

wiring configuration. (Ex. 1014, 4:38 (“As illustrated in FIG. [5]A3, the

semiconductor device is comprised of a semiconductor chip 1”).) While Takizawa

does not illustrate its offset wiring configuration, it explicitly states that “[i]t is not

3 There is a typographical error in Takizawa, where it references Fig. 1A and

not Fig. 5A on page 4 at line 38. It is clear to one of skill in the art reading

Takizawa from the surrounding text the reference should be to Fig. 5A. Similar

typographical errors occur on page 4 line 36, which should read “FIGS 5A to 5C

illustrate a semiconductor device in accordance with the first embodiment of the

present invention.”

Exhibit 100200063

Exhibit 1002

64

always necessary that the solder ball [11]4 is located just above the electrode 12.”

when discussing the configuration shown in Fig. 5A. (Ex. 1014, 4:49) One of skill

in the art would have appreciated Takizawa’s statement to refer to an offset wiring

configuration.

113. In order to illustrate that alternative configuration where Takizawa’s

wiring 2 is provided in an offset configuration relative to its electrode 12, a

modified version of Fig. 5A is provided below.

4 There are typographical errors in Takizawa, where it references solder ball

101 and not solder ball 11 on page 4 lines 41, 42, 46, 48, 49, and 51. It is clear to

one of skill in the art reading Takizawa from the surrounding text the reference

should be to Fig. 5A and solder ball 11. These errors are not present beginning

with line 52 on page 4.

Exhibit 100200064

Exhibit 1002

65

114. Takizawa also describes a “diffusion layer” in the form of a Sn-Cu

alloy layer 21 (i.e. an intermetallic) between its wiring 2 and solder ball 11: “As

mentioned earlier, the Cu-Sn alloy layer 21 is sandwiched between the solder ball

11 and the wiring layer 2 in the first embodiment. The Cu-Sn alloy layer 21

makes it possible to prevent occurrence of breakage and cracking across the solder

ball 11 and the wiring layer 2, preventing that the solder ball 11 is separated from

the wiring layer 2 due to the breakage and/or cracking across the solder ball 11 and

the wiring layer 2. As a result, it would be possible to enhance a fabrication yield

of the semiconductor device.” (Ex. 1014, 4:61-5:3.) Annotated Figs. 5B and 6B

are provided below, highlighting the Cu-Sn alloy layer 21.

Exhibit 100200065

Exhibit 1002

66

D. Takizawa Describes The Content Of Claims 1-7, 9-16, and 18

115. It is my opinion that Takizawa alone describes the content of each of

claims 1-7, 9-16, and 18 of the ‘001 patent. Below, I explain the correlation

between aspects of Takizawa and those claims.

1. Takizawa: Independent Claim 1

116. Independent claim 1 includes four parts (designated (a) through (d))

and a “preamble,” and I address each of those parts in turn below.

(1) Claim 1: Preamble: (A semiconductor device)

117. Takizawa describes and illustrates a “semiconductor device,” by way

of Fig. 5A and prior art Fig. 1A and their accompanying explanations. (Ex. 1014,

4:38 (“As illustrated in FIG. [5]A, the semiconductor device is comprised of a

semiconductor chip 1”); 2:13 (“With reference to FIG. 1A, the conventional

semiconductor device is comprised of a semiconductor chip 1”).)

(2) Claim 1: Element (a): (a semiconductor element)

118. The semiconductor device of Takizawa includes a “semiconductor

element” as semiconductor chip 1 in both Fig. 5A and the prior art Fig. 1A

examples. (Ex. 1014, 4:38 (“As illustrated in FIG. [5]A, the semiconductor device

is comprised of a semiconductor chip 1”); 2:13 (“With reference to FIG. 1A, the

Exhibit 100200066

Exhibit 1002

67

conventional semiconductor device is comprised of a semiconductor chip 1”).) As

noted above, while Takizawa does not illustrate its offset wiring configuration, it

explicitly states that “[i]t is not always necessary that the solder ball [11] is located

just above the electrode 12” when discussing the configuration shown in Fig. 5A.

(Ex. 1014, 4:49)

119. In order to illustrate that alternative configuration where Takizawa’s

wiring 2 is provided in an offset configuration relative to its electrode 12, a

modified version of Fig. 5A is provided below highlighting the semiconductor

element. Takizawa’s statement about the location of the solder ball 11 relative to

the electrode 12 is equally applicable to prior art Fig. 1A, but I have not prepared a

modification of that figure, because figures 5A and 1A are essentially identical

except for the numerical designation of the solder ball.5

5 Fig. 1A includes a reference number 8 to a layer of Gold (Au) not included

in Fig. 5A.

Exhibit 100200067

Exhibit 1002

68

(3) Claim 1: Element (b): (a first electrode portion formed on the semiconductor element, said first electrode portion comprising a first metal component)

120. The semiconductor device of Takizawa also includes a “first electrode

portion” formed on its semiconductor element that is made of a “first metal

component.” In particular, Takizawa in both Fig. 5A and prior art Fig. 1A include

wiring 2, the portion of which below the solder ball is a “first electrode portion.”

Wiring 2 is made of Cu as its “first metal component.” As stated by Takizawa:

“The wiring layer 2 is in electrical connection with the semiconductor chip 1, and

contains copper (Cu) therein. The solder ball [11] contains tin (Sn) therein.” (Ex.

1014, 4:45-46; see also 5:14 and 2:19 (regarding Fig. 1A).)

121. The modified version of Fig. 5A showing Takizawa’s offset

configuration is annotated below to highlight its “first electrode portion.”

Exhibit 100200068

Exhibit 1002

69

(4) Claim 1: Element (c): (a second electrode portion formed on the semiconductor element and electrically connected to said first electrode portion, said second electrode portion comprising a second metal component different from said first metal component)

122. In Takizawa, the “second electrode portion” is its solder ball 11 in

Fig. 5A and 101 in prior art Fig. 1A. The modified version of Fig. 5A showing

Takizawa’s offset configuration is annotated below to highlight its “second


Exhibit 100200069

Exhibit 1002

70

123. Takizawa explains that its solder ball 11 in Fig. 5A and 101 in prior

art Fig. 1A includes Sn as the “second metal component.” (Ex. 1014, 4:52-53

(“FIG. 6A is an enlarged view of the wiring layer 2 and the solder ball 11, wherein

the solder ball 11 is composed of Sn-Pb eutectic solder containing tin 22 at 65%

and lead at 35%.”); see also 2:26-27 (regarding Fig. 1A solder ball 101 containing

63% tin).)

(5) Claim 1: Element (d): (a diffusion layer formed between said first electrode portion and said second electrode portion, wherein said diffusion layer comprises said first metal component and said second metal component)

124. Takizawa explains the existence of a “diffusion layer” in the form of

its Sn-Cu alloy layer 21 for Fig. 5B, and Sn-Cu alloy layer 81 for its prior art Fig.

1B. As explained by Takizawa: “As mentioned earlier, the Cu-Sn alloy layer 21

Exhibit 100200070

Exhibit 1002

71

is sandwiched between the solder ball 11 and the wiring layer 2 in the first

embodiment. The Cu-Sn alloy layer 21 makes it possible to prevent occurrence of

breakage and cracking across the solder ball 11 and the wiring layer 2, preventing

that the solder ball 11 is separated from the wiring layer 2 due to the breakage

and/or cracking across the solder ball 11 and the wiring layer 2. As a result, it

would be possible to enhance a fabrication yield of the semiconductor device.”)

(Ex. 1014, 4:61-5:3; see also 2:28-29 (discussing Cu-Sn alloy layer 81 for prior art

Fig. 1A).) Notably, both Takizawa and the ‘001 patent use the same “Sn-Cu alloy

layer” terminology to describe their respective “diffusion layers.” (See Ex. 1001,

8:63-9:1 (“Sn contained in solder of the ball electrode 16 diffuses into Cu

contained in the metal wiring 14, whereby a Sn—Cu alloy layer having low

strength grows in the thickness direction of the external electrode portion 14a”).)

125. Annotated Figs. 5B and 6B are provided below, highlighting the Cu-

Sn alloy layer 21 that is the “diffusion layer” of the ‘001 patent claims.

Exhibit 100200071

Exhibit 1002

72

2. Takizawa: Dependent Claim 2 (The semiconductor device of claim 1, wherein said first metal component includes copper and said second metal component includes tin)

126. I explained above how Takizawa describes the features of

independent claim 1. As explained, Takizawa’s wiring 2 in both Fig. 5A and the

prior art Fig. 1A is made of Cu, a portion of which is the “first electrode portion”

as discussed above. (Ex. 1014, 4:45-46; see also 5:19 and 1:19 (regarding Fig.

1A).) Also, the solder ball 11 of Fig. 5A and the solder ball 101 of prior art Fig.

1A as a “second electrode portion” includes Sn as its “second metal component.”

(Ex. 1014, 4:52-53 (“FIG. 6A is an enlarged view of the wiring layer 2 and the

solder ball 11, wherein the solder ball 11 is composed of Sn-Pb eutectic solder

Exhibit 100200072

Exhibit 1002

73

containing tin 22 at 65% and lead at 35%.”); see also 2:26-27 (regarding Fig. 1A

solder ball 101 containing 63% tin).)

3. Takizawa: Dependent Claim 3 (The semiconductor device of claim 1, further comprising a third electrode portion formed on a surface of the semiconductor element and a metal wiring formed on the semiconductor element, said metal wiring electrically connecting the first electrode portion to the third electrode portion)

127. I explained above how Takizawa describes the features of

independent claim 1. In addition, Takizawa also includes a “third electrode

portion” as its electrode 12 on the surface of its semiconductor element

(semiconductor chip 1) which is connected to wiring (metal 5 and wiring 2). In

both Fig. 5A and the prior art Fig. 1A, the metal wiring (metal 5 and wiring 2)

electrically connects the third electrode portion (electrode 12) to the first electrode

portion (portion of wiring 2 under the solder ball). As stated by Takizawa: “In the

semiconductor device in accordance with the first embodiment, the through-hole 4

is formed just above an electrode 12 of the semiconductor chip 12. The solder ball

[11] is electrically connected to the electrode 12 through the metal 5 filled in the

through-hole 4.” (Ex. 1014, 4:47-49; see also 2:17-18 (regarding prior art Fig.

1A).)

Exhibit 100200073

Exhibit 1002

74


configuration is annotated below to highlight its “third electrode portion” and

“metal wiring.” As stated previously, the offset configuration is equally applicable

to prior art Fig. 1A, which is essentially identical.

4. Takizawa: Dependent Claim 4 (The semiconductor device of claim 3, wherein the first and third electrode portion are horizontally spaced apart with respect to the semiconductor element)

129. As shown directly above with respect to claim 3, in the offset

configuration explained by Takizawa, the first and third electrode portions are

horizontally spaced apart with respect to its semiconductor element.

5. Takizawa: Dependent Claim 5

Exhibit 100200074

Exhibit 1002

75

130. Dependent claim 5 includes three parts, which I have designated as

parts (a) through (c), and I address each of those parts in turn below.

(1) Claim 5: Element (a): (The semiconductor device of claim 3, further comprising an insulating film formed on said metal wiring)

131. I explained above how Takizawa describes the features of dependent

claim 3. In addition, Takizawa also describes an “insulating film” of solder resist

32 over its “metal wiring” (wiring 2 as part of its “metal wiring”), in both the Fig.

5A and prior art Fig. 1A examples. As stated by Takizawa: “As illustrated in FIG.

[5]A, the semiconductor device is comprised of a semiconductor chip 1, a film

substrate 3, a polyimide adhesive layer 31 adhering the film substrate 3 to the

semiconductor chip 1, a resist 32 covering the wiring layer 2 therewith and

formed with a land 7 which is a recess formed at a surface thereof, a wiring

layer 2 formed on the film substrate 3, a solder ball [11] mounted on the wiring

layer 2 in the land 7, a layer 21 (see FIG. [5]B) made of copper-tin alloy and

sandwiched between the solder ball [11] and the wiring layer 2, a metal 5 filled in a

through-hole 4 formed through both the film substrate 3 and the polyimide

adhesive layer 31, and a gold (Au) layer 6 covering therewith the metal 5 at a top

surface thereof.” (Ex. 1014, 4:38-44; see also 2:14-15 (similar disclosure for prior

art Fig. 1A).) One of skill in the art would have appreciated that the reference to

Exhibit 100200075

Exhibit 1002

76

“resist 32” is to a non-conducting (insulating) solder resist used to protect the

wiring from contacting a solder alloy during soldering processes.


configuration is annotated below to highlight its “insulating film.” As stated

previously, the offset configuration is equally applicable to prior art Fig. 1A, which

is essentially identical.

(2) Claim 5: Element (b): (wherein an opening of said insulating film exposes a surface of the first electrode portion)

133. Takizawa’s insulating film includes an opening to expose a surface of

its first electrode portion, as shown in the annotation below. (See Ex. 1014, Fig. 7G

and 5:26-27 (“Then, as illustrated in FIG. 7G, the resist 32 is formed with the land

Exhibit 100200076

Exhibit 1002

77

7 above the wiring layer 2. In later steps, the solder ball 11 is mounted on the

wiring layer 2 in the land 7.”); Fig. 3G and 2:45-46 (regarding prior art Fig. 1A).)

(3) Claim 5: Element (c): (and wherein said surface of the first electrode portion is flush with or higher than a surface of the insulating film)

134. As shown in the annotated Fig. provided directly below, Takizawa’s

first electrode portion is flush with a surface of its insulating film. As to that

illustration, one of skill in the art would have appreciated that the resist is drawn in

an exaggerated form to show its protection of other portions of wiring 2 to which

the solder ball will not be attached. Thus, one of skill in the art would have

appreciated that Takizawa’s first electrode portion is at least approximately flush

with a surface of its insulating film, also demonstrated by the portion of Fig. 10.20

provided below. (See e.g., Ex. 1007 at Fig. 10.20 (at right side of Fig. 10.20 noting

Exhibit 100200077

Exhibit 1002

78

“10 μm MIN (over copper)” where copper refers to the pad (first electrode

portion)).)

Exhibit 100200078

Exhibit 1002

79

6. Takizawa: Dependent Claim 6 (The semiconductor device of claim 3, wherein the metal wiring includes copper)


claim 3. In addition, Takizawa explains that its metal wiring (metal 5 and portion

of wiring 2) includes Cu, for both Fig. 5A and the prior art Fig. 1A examples (Ex.

1014, 4:45-46 (regarding Fig. 5A); 5:24 (regarding Fig. 5A); 2:19 (regarding prior

art Fig. 1A); 2:43 (regarding prior art Fig. 1A).)

7. Takizawa: Dependent Claim 7

136. Dependent claim 7 includes two parts, which I have designated as

parts (a) and (b), and I address each of those parts in turn below.

(1) Claim 7: Element (a): (The semiconductor device of claim 3, further comprising an insulating resin layer formed between the surface of the semiconductor element and the metal wiring)


claim 3. In addition, Takizawa also describes an “insulating resin layer” between

the surface of its semiconductor element and its metal wiring (wiring 2 as part of

its “metal wiring”) in the form of its film substrate 3 made of a polyimide as well

as an adhesive layer 31 also made of a polyimide, in both Fig. 5A and the prior art

Fig. 1A. As stated by Takizawa: “As illustrated in FIG. [5]A, the semiconductor

device is comprised of a semiconductor chip 1, a film substrate 3, a polyimide

Exhibit 100200079

Exhibit 1002

80

adhesive layer 31 adhering the film substrate 3 to the semiconductor chip 1, a

resist 32 covering the wiring layer 2 therewith and formed with a land 7 which is a

recess formed at a surface thereof, a wiring layer 2 formed on the film substrate 3,

a solder ball [11] mounted on the wiring layer 2 in the land 7, a layer 21 (see FIG.

[5]B) made of copper-tin alloy and sandwiched between the solder ball 101 and the

wiring layer 2, a metal 5 filled in a through-hole 4 formed through both the film

substrate 3 and the polyimide adhesive layer 31, and a gold (Au) layer 6 covering

therewith the metal 5 at a top surface thereof.” (Ex. 1014, 4:38-44; 5:15-19

(content of film substrate 3 and adhesive 31 as polyimides), and 2:34-37 (similar

disclosure for prior art Fig. 1A).)

138. Here, one of skill in the art would have appreciated that the

polyimides of the film substrate 3 and adhesive layer 31 of both Fig. 5A and prior

art Fig. 1A were resins prior to being cured, forming a “resin layer.” In addition,

Takizawa describes the use of an epoxy resin 42 when connecting the completed

substrates of Fig. 5A and prior art Fig. 1A to semiconductor chip 1, which itself or

in combination with film substrate 3 or adhesive 31, would also be an “insulating

resin layer.” (See Ex. 1014, 3:1-3 (with regard to Fig. 1A…“resin 42 is applied

between tape substrate 93 and the semiconductor chip 1…The resin 42 is

composed of epoxy resin liquid, for instance”); 5:42-44 (with regard to Fig.

Exhibit 100200080

Exhibit 1002

81

5A…“resin 42 is applied between tape substrate 33 and the semiconductor chip

1…The resin is composed of epoxy resin in liquid, for instance”).)

139. Further, one of skill in the art would also have appreciated that the

polyimides of the film substrate 3 and adhesive layer 31, and the epoxy resin 42 of

both Fig. 5A and the prior art Fig. 1A examples would be compliant, and would

provide stress absorption/relaxation similar to the alleged effect of the ‘001

patent’s “insulating resin layer.” (See Ex. 1001, 12:16-36 (discussing ‘001 patent

“insulating resin layer” alleged “effects”).) That understanding is explained by

PCT Publication No. WO99/49511 (“Hashimoto”), provided as Ex. 1015, which

explains the compliant qualities of such materials as: “Here, the intermediate layer

16 is made of an insulating resin, for example, a polyimide resin, and when the

semiconductor device 10 is mounted to a circuit board (not shown), this layer can

relax the stress occurred due to the difference in the coefficient of thermal

expansion between the semiconductor chip 12 and the mounted circuit board.” (Ex.

1015, 8:9-13; see also 8:14-25 (discussing “low Young’s modulus” and other

features of described “intermediate layer 16”).)


configuration is annotated below to highlight its “insulating resin layer.” As stated

Exhibit 100200081

Exhibit 1002

82

previously, the offset configuration is equally applicable to prior art Fig. 1A, which

is essentially identical.

(2) Claim 7: Element (b): (wherein the metal wiring is formed along a surface of the insulating resin layer)

141. As shown by the annotated Figure directly above, Takizawa’s metal

wiring (portion of wiring 2) is formed along a surface of its insulating resin layer.

142. The fact that Takizawa as prior art discloses such an “insulating resin

layer” is confirmed by the ‘001 patent itself, which states that an insulating resin

layer and metal wiring formed along a surface of that insulating resin layer is prior

art, and known in conventional semiconductor devices. (See Ex. 1001, prior art

Fig. 15C and 2:1-3.)

Exhibit 100200082

Exhibit 1002

83

8. Takizawa: Dependent Claim 9 (The semiconductor device of claim 1, further comprising a substrate having a wiring electrode, wherein said wiring electrode is electrically connected to said second electrode portion)


claim 1. In addition, Takizawa explains how its semiconductor device in both Fig.

5A and prior art Fig. 1A is attached to a printed wiring board (a substrate) by

connecting of the solder balls (second electrode portion) to the wiring of the

printed wiring board. (See Ex. 1014, 3:15-16 (“Then, as illustrated in FIG. 4H, the

solder balls 101 are caused to reflow to thereby physically connect the solder balls

101 to the printed wiring board 34. Thus, there is completed a semiconductor

device as a final product.”); 5:58-59 (“Then, as illustrated in FIG. 8I, the solder

balls 11 are caused to reflow to thereby physically connect the solder balls 11 to

the printed wiring board 34. Thus, there is completed a semiconductor device as a

final product”).)

9. Takizawa: Independent Claim 10

144. The text of independent claim 10 is identical to that of independent

claim 1 except for the additional element of “said first electrode portion and said

diffusion layer have a combined thickness in the range of 10 m to 20 m.” So, I

incorporate my earlier analysis provided in paragraphs 116-125 here, without

repeating it.

Exhibit 100200083

Exhibit 1002

84

145. As to that specific element, Takizawa explains that its wiring 2 is 18

microns thick for both Fig. 5A and prior art example Fig. 1A (Ex. 1014, 5:16 (with

respect to Fig. 5A “the wiring layer 2 has a thickness of 18 micrometers”) and 2:35

(with respect to prior art Fig. 1A “the wiring layer 2 has a thickness of 18

micrometers”).) This discussion covers the portion of the “combined thickness” in

relation to the “first electrode portion” as that is the portion of wiring 2 beneath the

solder ball, as I previously explained.

146. With respect to the claimed “diffusion layer,” Takizawa explains that

the Cu-Sn alloy layer 21 of Figs. 5B and 6B has a thickness of 1.87 microns, and

the Cu-Sn alloy layer 81 in prior art Figs. 2A and 2B has a thickness of 1.0 micron.

(Ex. 1014, 6:32-33 (“Thus, the Cu-Sn layer 21 is required to have a thickness equal

to 1.87 micrometers at smallest in order to prevent the solder ball 11 from being

separated from the wiring layer 2.”) and 6:29-30 (“In contrast, most of the Cu-Sn

alloy layers [81]6in the conventional semiconductor device illustrated in FIGS. 2A

and 2B have a thickness in the range of 1.0 micrometers to 1.5 micrometers”).)

This additional discussion covers the portion of the “combined thickness” in

relation to the diffusion layer, as I explained previously.

6 There is another typographical error in Takizawa where it refers to 21

instead of 81 in reference to the prior art Cn-Sn alloy layer, which one of ordinary

skill would have appreciated in view of the surrounding discussion.

Exhibit 100200084

Exhibit 1002

85

147. So, taking the two together, the “combined thickness” of the first

electrode portion of Fig. 5A and the diffusion layer (layer 21) of Fig. 5B is 18 m

+ 1.87 m = 19.87 m. A similar calculation for the prior art in Figs 2A and 2B

yields a combined thickness of 18 m + 1.0 m = 19 m. Both of these combined

thicknesses from Takizawa are in the range of “10 m to 20 m” required by claim

10.

10.Takizawa: Dependent Claim 11


incorporate my earlier analysis provided in paragraph 126, without repeating it

here.



incorporate my earlier analysis provided in paragraphs 127-128, without repeating

it here.




here.


Exhibit 100200085

Exhibit 1002

86



it here.




here.




it here.




here.

E. Takizawa Combined with Narizuka For Claims 8 and 17

155. In paragraphs 111-114, 116-125, 127-128, 144-147, and 149. I

provided an introduction to Takizawa, and an explanation as to how that patent

describes the features of dependent claims 3 and 12. Each of claims 8 and 17

Exhibit 100200086

Exhibit 1002

87

depend from dependent claims 3 and 12, respectively, and claim “The

semiconductor device of claim 3 [or 12], wherein the metal wiring has a thickness

in the range of 0.01 m to 8 m.” Significantly, these claims state “a thickness of

the metal wiring.” Thus, my analysis focuses on the portion of Takizawa’s wiring

2 that is part of its “metal wiring” (i.e., the portion that is not the “first electrode

portion”).

156. As I noted above, Takizawa states that its wiring 2 is 18 μm thick for

the Fig. 5A example, but that thickness is only provided as an example. (See Ex.

1014, 5:14-16 (regarding Fig. 5A – “as illustrated in Fig. 7A…the wiring layer 2

has a thickness of 18 micrometers”).) The focus of Takizawa is its preferred

thickness of the Sn-Cu alloy layer (i.e., “diffusion layer”) of at least 1.87 microns,

which is claimed by Takizawa up to 3 microns or more, without any reference to

any particular thickness of its wiring 2. (See Ex. 1014, claims 1-3.)

157. Here, selection of a thickness of the metal wiring was simply a

design choice, as supported by Takizawa’s own description, and one of skill in the

art would have known to create wiring within the claimed range using industry

standard techniques and processes at the time of the ‘001 patent. As an example,

Narizuka, the first patent I discussed, shows an offset wiring configuration similar

to that of Takizawa which also includes copper, where the copper portion ranges

Exhibit 100200087

Exhibit 1002

88

from “about 0.1 m to about 10 [ ]m,” and its overall wiring is within the claimed

range. (See Ex. 1012, 4:8-9 (“Furthermore, in the wiring of the wiring board in the

present invention, the thickness of the Cu layer is from about 0.1 m to about 10

m.”); 8:14-17 (“The wiring 13 according to the present invention is formed by

laminating a Cu layer 13a with a thickness of about 0.1-10 m, which is

practically the lowest resistance material, into the portion that connects to an

external circuit; a Cu or Ti thin film layer 13b with a thickness of about 0.05-

1.0 m on the under layer 15 side; a Cr thin film layer 13c with a thickness of

about 0.01-0.3 m thick on the protective film 16 side”).)

158. Further consideration must be given to claim 17, since that claim

depends from claim 10, which includes the requirement that “said first electrode

portion and said diffusion layer have a combined thickness in the range of 10 m

to 20 m.” Copper wiring of 8 μm in thickness was well within the abilities of one

of skill in the art, as just explained, and as shown by the Narizuka reference.

Further, Takizawa states that its Sn-Cu alloy layer, for the Fig. 5A example, is

“1.87 micrometers or greater, more preferably of 2 micrometers or greater, and

most preferably of 3 micrometers or greater.” (See Ex. 1014, 5:4-5.) Thus, when

selecting a wiring thickness of 8 μm, the “combined thickness” of the “first

electrode portion” (portion of wiring 2 under the solder ball) and the “diffusion

Exhibit 100200088

Exhibit 1002

89

layer” would be at least 10μm and preferably 11μm or more, which is in the range

of “10 m to 20 m” required by claim 10.

F. Takizawa Combined with Hashimoto For Claims 7 and 16

159. As I explained above in paragraphs 90-94, it is my opinion that

Takizawa discloses an “insulating resin layer” by its polyimide substrate 3 and

adhesive 31, as well as its epoxy resin 42, for both Fig. 5A and prior art Fig. 1A.

Nevertheless, if the description in the Takizawa patent taken from the perspective

of one of skill in the art as shown by the explanation of Hashimoto regarding

known compliancy of its materials is deemed insufficient, it would have been

obvious to one of skill in the art to use the “insulating resin” material disclosed in

Hashimoto, the compliant benefits of which are expressly explained in that

reference. (Ex. 1015, 8:9-13 (“Here, the intermediate layer 16 is made of an

insulating resin, for example, a polyimide resin, and when the semiconductor

device 10 is mounted to a circuit board (not shown), this layer can relax the stress

occurred due to the difference in the coefficient of thermal expansion between the

semiconductor chip 12 and the mounted circuit board.”; see also 8:14-25

(discussing “low Young’s modulus” and other features of described “intermediate

layer 16”).)

Exhibit 100200089

Exhibit 1002

90

160. That “insulating resin” material of Hashimoto would be used by one

of skill in the art to construct the substrate 3 (in both Fig. 5A and Fig. 1A), which

is already disclosed as being comprised of a polyimide, and the benefits of that

material would be imparted to the existing semiconductor device of Takizawa.

Use of Hashimoto’s “insulating resin” material would not change the existing

structure of the semiconductor device of Fig. 5A or prior art Fig. 1A, which shows

the claimed features as discussed above.

VI. Secondary or Objective Evidence of Non-obviousness

161. As initially discussed above in paragraph 16, I am only aware of the

alleged unexpected results that the ‘001 patent itself discusses that the applicants

argued as potential “secondary considerations.” However those unexpected results

(while not expressed as “unexpected” or “surprising”) are only discussed in the

context of the selection of the thickness of the external electrode (i.e. the first

electrode portion), and there are no claims specific to that thickness. (See e.g., Ex.

1001, 9:36-10:14, 17:3-38, 23:34-39.) This is consistent with the ‘001 patent’s

failure to describe anything other than the thickness of the external electrode (i.e.,

the first electrode portion), which also offers no discussion of the thickness of the

“diffusion layer,” as I previously explained. So, if Tessera attempts to highlight

the ‘001 patent’s “unexpected results,” there is no technical connection or “nexus”

between those “unexpected results” and the element of claim 10 of “said first

Exhibit 100200090

Exhibit 100200091

Exhibit 1002

Appendix

CV of Jeffrey C. Suhling

Exhibit 100200092

Exhibit 1002

JEFFREY C. SUHLING Quina Distinguished Professor and Department Chair

Department of Mechanical Engineering Auburn University

Auburn, AL 36849-5341 USA

Office: +1-334-844-3332 FAX: +1-334-844-3124

E-Mail: [email protected]

Resume

EDUCATION

B.S. Applied Mathematics, Engineering, and Physics University of Wisconsin, Graduated with Highest Distinction, 1980

M.S. Engineering Mechanics, University of Wisconsin, 1981 Ph.D. Engineering Mechanics, University of Wisconsin, 1985

RESEARCH INTERESTS

Solid Mechanics, Advanced and Composite Materials, Experimental Mechanics, Finite Element Analysis and Computational Mechanics, Continuum Modeling, Electronics Assembly and Packaging, Stress and Strain Analysis of Electronic Packaging, Silicon Sensors, Solder Joint Reliability, Mechanical Behavior of Solders and Microelectronic Encapsulants, and Mechanics of Paper Materials.

EXPERIENCE

Graduate Research Assistant and Graduate Teaching Assistant, Department of Engineering Mechanics, University of Wisconsin, 1980-1985.

Assistant Professor, Department of Mechanical Engineering, Auburn University, 1985-1990.

Associate Professor, Department of Mechanical Engineering, Auburn University, 1990-2001

Quina Distinguished Professor, Department of Mechanical Engineering, Auburn 2001-Present.

Center Director, NSF Center for Advance Vehicle Electronics (CAVE), Auburn University, 2002-2008.

Department Chair, Department of Mechanical Engineering, Auburn University, 2008-Present.

Exhibit 100200093

Exhibit 1002

HONORS AND AWARDS

Dean's Honor List, University of Wisconsin, 1976-1980

Sophomore Honors, University of Wisconsin, 1978

Phi Eta Sigma Honor Society, 1977

Phi Kappa Phi Honor Society, 1979

Phi Beta Kappa Honor Society, 1979

Graduated with Highest Distinction, University of Wisconsin, 1980

National Science Foundation Graduate Fellowship, 1980-1983

Sigma Xi Honorary Scientific Society, 1985

Tau Beta Pi Lecturer, 1988-1991

Outstanding Faculty Member, Department of Mechanical Engineering, Auburn University, 1989-90

Pi Tau Sigma Teacher of the Year, Department of Mechanical Engineering, Auburn University, 1989-90

ASME Regional Faculty Advisor Award, 1992

Birdsong Superior Teaching Award, College of Engineering, Auburn University, 1994

Pulp and Paper Associate Professor, College of Engineering, Auburn University, 1995-96

Pulp and Paper Associate Professor, College of Engineering, Auburn University, 1997-98

Best Paper of Conference Award, 1999 International Conference on MultichipModules and High Density Packaging, Denver, CO, April 6-9, 1999

Quina Distinguished Professorship, Endowed/Named/Titled Faculty Position, Auburn University, 2001-Present

Senior Faculty Research Award, Auburn University, Alumni Engineering Council, 2001

Exhibit 100200094

Exhibit 1002

HONORS AND AWARDS (Continued)

Best Paper of Conference Award, 2002 IMAPS International Symposium on Microelectronics, Denver, CO, September 4-6, 2002.

Commendable Paper Award (Runner-up to Best Paper Award), Soldering and Surface Mount Technology Journal, 2004.

Best Paper of Conference Award, 2005 IEEE Electronic Components and Technology Conference (ECTC), Orlando, FL, June 1-3, 2005.

Best Poster of Conference Award, InterPACK ’07, Vancouver, BC, Canada, 2007.

Best Paper of Conference Award, 2008 SMTA International, Orlando, FL, August 17-21, 2008.

ASME Fellow, 2009.

ASME Excellence in Mechanics Research Award, For Outstanding Contributions in the Area of Engineering Mechanics Applications to the Field of Electronic and Photonic Packaging, ASME, 2009.

Best Poster of Conference Award, InterPACK ’09, San Francisco, CA, 2009.

Best Paper of Conference Award, 2010 IEEE Electronic Components and Technology Conference (ECTC), Las Vegas, NV, June 2-4, 2010.

Best Paper of Conference Award, Mechanics Area, InterPACK ’13, San Francisco, CA, 2013.

Best Poster of Conference Award, Mechanics Area, InterPACK ’13, San Francisco, CA, 2013.

Best Paper of Conference Award, 2014, IEEE Electronic Components and Technology Conference (ECTC), Orlando, FL, May 28-30, 2014.

Outstanding Poster of Conference Award, Mechanics Area, InterPACK ’15, San Francisco, CA, 2015.

Exhibit 100200095

Exhibit 1002

TEACHING (Courses Taught)

University of Wisconsin (Semester System, 1980-1985)

UndergraduateEM 202, Dynamics EM 303, Mechanics of Materials EM 321, Mechanics of Materials Laboratory

Auburn University (Quarter System, 1985-2000)

UndergraduateME 205, Applied Mechanics - Statics ME 207, Mechanics of Materials I ME 211, Engineering Methods ME 230, Mechanics of Materials II ME 233, Mechanics of Materials ME 235, Dynamics ME 309, Mechanics of Materials Laboratory ME 316, Mechanics of Materials II ME 321, Dynamics I ME 360, Mechanical Design I ME 533, Experimental Stress Analysis ME 534, Photoelastic Stress and Strain Analysis ME 591, Electronic Packaging Stress Analysis

GraduateME 631, Theory of Elasticity I ME 632, Theory of Elasticity II ME 633, Advanced Experimental Stress Analysis ME 636, Mechanics of Composite Materials ME 637, Theory of Plates ME 639, Variational Mechanics EE 668, Electronic Packaging

Exhibit 100200096

Exhibit 1002

TEACHING (Courses Taught) – Continued

Auburn University (Semester System, 2000-Present)

UndergraduateMECH 3130, Mechanics of Materials MECH 6310, Mechanics of Electronic Packaging ENGR 1100, Engineering Orientation ENGR 3510, Business and Engineering

GraduateMECH 7330, Experimental Mechanics MECH 7340, Inelastic Stress Analysis MECH 7360, Mechanics of Composite Materials MECH 7370, Theory of Plates and Shells

Exhibit 100200097

Exhibit 1002

TEACHING (Graduate Students)

Graduate Students (Served as Advisor / Major Professor)

Name Degree Year Position(s) After Graduation1. Charng-Phong Liu M.M.E. 1988 Engineer, Taiwan 2. Richard Wartman M.M.E. 1989 Engineer, USA 3. Yu-Pin Wu M.S. 1989 Engineer, Japan 4. Cheng-Hsiung Lin M.S. 1989 Ph.D. Student, University of Wisconsin; Goodyear Research, Akron, OH 5. Shun-Tien Lin M.S. 1989 Ph.D. Student, University of Wisconsin; United Technologies, Hartford, CT 6. Che-Ning Fan M.M.E. 1990 Engineer, CETRA, Taiwan 7. Gary G. Genge M.S. 1990 NASA, Huntsville, AL 8. David A. Bittle M.S. 1990 US Army MICOM, Huntsville, AL 9. Chu-Kuei Chien M.M.E. 1990 Engineer, Taiwan 10. Shuliang Luo M.S. 1991 Engineer, Taiwan 11. Hung-Peng Li M.S. 1991 Ph.D. Student, Virginia Polytechnic Institute; Goodyear Research, Akron, OH 12. Larry J. Pearce M.S. 1991 PDA Engineering (PATRAN) 13. Sung-Ching Hung M.S. 1991 Ph.D. Student, University of Texas-Austin; Engineer, Taiwan 14. Chii-Der Suh M.S. 1991 Ph.D. Student, Texas A&M University; Professor, Texas A&M University 15. Kuang-Chung Wan M.M.E. 1991 Ph.D. Student, Lehigh University; Outboard Marine, Carbondale, IL 16. Kang-Chang Yeh Ph.D. 1991 James River Research Center, Neenah, WI 17. Blaise Czekalski M.M.E. 1992 NASA, Huntsville, AL 18. Kenneth Patrick M.M.E. 1992 Engineer, Gadsden, AL 19. Donnie W. Curington M.S. 1992 Stress Engineering Services, Houston, TX 20. Patrick K. Rogers M.M.E. 1993 NASA, Huntsville, AL 21. Janet M. Wilhelm M.M.E. 1993 NASA, Huntsville, AL 22. Jon C. Vance M.S. 1993 Alabama Power Company, Birmingham, AL 23. Bryan Lynchard, M.M.E. 1995 McDonnel-Douglas Aerospace, Huntsville, AL 24. Peter Draheim M.M.E. 1995 USAF, Fort Worth, TX

Exhibit 100200098

Exhibit 1002

Graduate Students (Served as Advisor) Continued

Name Degree Year Position(s) After Graduation25. Robert Cordes M.S. 1995 IBM, Watson Research Center, Yorktown, NY 26. Andrew A. Anderson M.S. 1995 Texas Instruments, Dallas, TX 27. Andrea C. Gilchrist M.S. 1995 Engineer, Huntsville, AL 28. Jeffery D. White M.S. 1995 HKS, Inc. (ABAQUS), Providence, RI 29. Jianhua Pu M.M.E. 1995 Ph.D. Student, Auburn University 30. Shihua Liang Ph.D. 1996 Beloit Corporation, Rockton, IL 31. Ramanathan Ramani Ph.D. 1996 Texas Instruments, Dallas, TX 32. Cynthia Stewart M.S. 1997 NASA, Huntsville, AL 33. Ramon J. Moral M.S. 1997 Raltron, Miami, FL 34. Yanling Kang Ph.D. 1997 Motorola, Northbrook, IL 35. Raymond McDonald M.M.E. 1998 Great Dane Trailers, Savannah, GA 36. Arthur T. Bradley Ph.D. 1999 Professor, University of Tennessee, Knoxville, TN 37. Yida Zou Ph.D. 1999 Nokia Research, Dallas, TX 38. Ahsan Mian Ph.D. 2000 Professor, University of Montana 39. Gregory L. Johnson M.M.E. 2000 US Army SMDC, Huntsville, AL 40. Srikanth Ragam M.S. 2000 Intel Corporation, Portland, OR 41. Charles T. Bowen M.S. 2000 IBM, Austin, TX 42. Jianping Xu Ph.D. 2000 On Semiconductor, Warwick, RI 43. James Nelson M.M.E. 2002 Great Dane Trailers, Savannah, GA 44. Shahanoor Rahaman M.S. 2002 Ph.D. Student, University of Connecticut 45. Yonggang Chen M.S. 2003 Ph.D. Student, Auburn University 46. M. Kaysar Rahim M.S. 2004 Maxim Semiconductor, Dallas, TX 47. M. Nokibul Islam M.S. 2004 Amkor Technology, Phoenix, AZ 48. Hechem Abdel-Hady M.M.E. 2004 Goodrich Corporation, Hartford, CT 49. Sameera Neela M.S. 2004 Engineer, India 50. Tushar Shete M.S. 2004 Tyco Electronics, Dallas, TX 51. M. Saiful Islam M.S. 2005 Intel Corporation, Phoenix, AZ 52. Baohua Xu M.S. 2005 Engineer, Memphis, TN 53. Yasser Elkady Ph.D. 2005 Professor, Metro College, Canada 54. M. Kaysar Rahim Ph.D. 2005 Maxim Semiconductor, Dallas, TX 55. M. Saiful Islam Ph.D. 2006 Intel Corporation, Phoenix, AZ 56. Kapil D. Gore M.S. 2006 Engineer, VA Semiconductor Co. 57. Yonggang Chen Ph.D. 2006 Integrated Device Technologies, Atlanta, GA 58. Hongtao Ma Ph.D. 2007 Cisco Systems, San Jose, CA 59. Chun-Hyung Cho Ph.D. 2007 Professor, Hongik University, Korea 60. Jordan Roberts M.S. 2008 Ph.D. Student, Auburn University

Exhibit 100200099

Exhibit 1002

Graduate Students (Served as Advisor) Continued

Name Degree Year Position(s) After Graduation61. Kanth Kurumaddali M.S. 2009 Microsoft Corporation, Redmond, WA 62. Chang Lin Ph.D. 2010 Intel Corporation, Hillsboro, OR 63. Yifei Zhang Ph.D. 2010 Chinese Aerospace, Shanghai, China 64. Scott J. Hebert M.M.E 2011 NASA MSFC, Huntsville, AL 65. Kun-Yan Wang M.S. 2012 Mando Corporation, Opelika, AL 66. Zijie Cai Ph.D. 2012 Broadcom Corporation, Irvine, CA 67. Ivelisse D. Figueroa M.M.E. 2012 Knowles Corporation, Chicago, IL 68. Jing Zou M.S. 2013 iBaby Labs, Inc., Fremont, CA 69. Mohammad Motalab Ph.D. 2013 Professor, BUET, Bangladesh 70. Jordan Roberts Ph.D. 2014 Professor, Auburn Univ., Auburn, AL 71. Muhannad Mustafa Ph.D. 2014 Applied Materials Inc., San Jose, CA 72. Safina Hussain Ph.D. 2015 Intel Corporation, Hillsboro, OR 73. Nusrat Chhanda Ph.D. 2015 Applied Materials Inc., San Jose, CA 74. Munshi Basit Ph.D. 2015 Micron Corporation, Boise, ID 75. Md Hasnine Ph.D. 2015 National Energy Tech. Laboratory, Corvallis, OR 76. David S. Copeland Ph.D. Current 77. Quang Nguyen Ph.D. Current 78. Nianjun Fu Ph.D. Current 79. Chien-Tih Chen Ph.D. Current 80. Promod Chowdhury Ph.D. Current 81. Sudan Ahmed Ph.D. Current 82. Mohammad Alam Ph.D. Current 83. Abdullah Fahim Ph.D. Current 84. Md Chowdhury Ph.D. Current 85. Rafidh Hasan Ph.D. Current 86. Jing Wu Ph.D. Current 87. Jun Chen Ph.D. Current 88. Mohd Aminul Hoque Ph.D. Current

Graduate Students (Served on Committee at Auburn University)

Name Degree Year 1. James O. Burrows M.M.E. 1988 2. An-Pan Chern M.S. 1988 3. Shyi-Ping, Liu M.S. 1988 4. De-Sheng Liu M.S. 1989 5. Fine-Song Tseng M.MFE. 1989 6. Marie E. Quicke M.S. 1989 7. Shao-Qin Zhang Ph.D. 1989 8. Cheng-Jenq Wu M.S. 1990 9. B. S. Sridhara Ph.D. 1991

Exhibit 100200100

Exhibit 1002

Graduate Students (Served on Committee at Auburn University) Continued

Name Degree Year 10. Peter F. Cento M.S. 1991 11. Yunglu Liang M.S. 1991 12. Neil Otte M.M.E. 1991 13. James Pope M.S. 1991 14. Carl Nagel M.M.E. 1992 15. Robert J. Wingate M.M.E. 1992 16. Eric Hawkins M.S. 1992 17. Martin T. Carey M.S. 1992 18. S. Ramaswamy M.S. 1992 19. Douglas E. Fox M.M.E. 1993 20. Robert T. Pernell M.S. 1993 21. Stephen Merryman Ph.D. 1993 22. John Dispenette M.S. 1994 23. Gene Quattlebaum M.S. 1994 24. Michael G. Sessions M.S. 1994 25. Javier F. Garcia M.S. 1994 26. P. Ganeshan M.S. 1994 27. Jong-Hee Yim Ph.D. 1995 28. Yi Li M.S. 1995 29. Liming Xu Ph.D. 1996 30. H. Krishnamoorthy M.S. 1997 31. Lisa S. Kalv M.S. 1997 32. David S. Copeland M.M.E. 1998 33. Samuel B. Fowler M.M.E. 1998 34. Andrew Power M.M.E. 1998 35. Jongnam Lee Ph.D. 1999 36. Carl-Ernst Rousseau Ph.D. 2000 37. Venkatesh Talupur M.M.E. 2001 38. Shakib Morshed M.S. 2002 39. Maurice Tucker M.A.E. 2002 40. Levent Onal Ph.D. 2002 41. Medhat El-Hadek Ph.D. 2003 42. Jianhu Pu Ph.D. 2003 43. Michael J. Maleski M.S. 2003 44. M. Chandler McLeod Ph.D. 2004 45. Sandesh Rudrapati M.S. 2004 46. Nikhil Mathur M.S. 2004 47. Kaustubh Godbole M.S. 2004 48. Lynn S. Craft M.M.E. 2005 49. Naveen C. Singh M.S. 2005 50. M. Nokibul Islam Ph.D. 2005 51. Rajesh Kitey Ph.D. 2005

Exhibit 100200101

Exhibit 1002


Name Degree Year 52. Piyush Savalia M.S. 2006 53. Kelly L. Barber M.S. 2006 54. Ganesh Hariharan M.S. 2007 55. Liwei Wang M.S. 2007 56. Taylor Owens M.S. 2007 57. Anthony T. Owens M.S. 2007 58. Jonathan L. Drake M.S. 2007 59. Dhananjay Panchagade Ph.D. 2007 60. Madhu Kirugulige Ph.D. 2007 61. Cai Liang Ph.D. 2007 62. Madhura Hande M.S. 2008 63. Darshan Shinde M.S. 2008 64. Santosh Angadi M.S. 2008 65. Rahul Jhaver M.S. 2008 66. Josh Ridenour M.S. 2008 67. Chandan Bhat M.S. 2008 68. Madhura Hande M.S. 2008 69. Chad L. Rodekohr Ph.D. 2008 70. Jyoti K. Ajitsaria Ph.D. 2008 71. Aniket Shirgaokar M.S. 2009 72. Robert Hinshaw M.S. 2009 73. Douglas Sampson M.M.E. 2010 74. Rebecca Ibrahim M.S. 2010 75. Rahul Vaidya M.S. 2010 76. Vikrant More M.S. 2010 77. Chen Chen Ph.D. 2010 78. Jeffrey Cho M.M.E. 2011 79. Allen Craven M.S. 2011 80. Santosh Angadi Ph.D. 2011 81. Varun Soman M.S. 2012 82. Dineshkumar Arunachalam M.S. 2012 83. William N. Yunker M.S. 2012 84. Geeta Limaye M.S. 2012 85. Chandru Periasamy Ph.D. 2012 86. Ryan Lowe Ph.D. 2012 87. Kewal Patel M.S. 2013 88. Amir Rostami M.S. 2013 89. Oscar E. Sotomayor M.S. 2013 90. Kailash Jajam Ph.D. 2013 91. Sandeep Shantaram Ph.D. 2013 92. Mahendra Harsha Ph.D. 2013 93. Seyed H. Ghasemi Ph.D. 2014

Exhibit 100200102

Exhibit 1002


Name Degree Year 94. Fuxi Zhang M.S. 2015 95. Amith Jain M.S. 2015 96. Jonathan Grupp Ph.D. 2015 97. Robert Bedsole Ph.D. 2015 98. Peter Sakalaukus Ph.D. 2015 99. MariAnne Sullivan Ph.D. 2015 100. Ted Towry M.M.E. Current 101. Sree Mitun Duraisamy M.S. Current 102. Stephen Thornton M.S. Current 103. Prashant Gupta Ph.D. Current 104. Kazi Mirza Ph.D. Current 105. Vijaykumar Krithivasan Ph.D. Current 106. Bala M. Sundaram Ph.D. Current 107. R. K. A. Pasumarthy Ph.D. Current 108. P. Gnanachchelvi Ph.D. Current

Graduate Students (Served on Committee at Another University as External Reviewer) 1. Michael Mayer, Ph.D., Swiss Federal Institute of Technology, Zurich, Switzerland,

2000.2. Timothy Jackson, Ph.D., Monash University, Clayton, Australia, 2000. 3. Yunguang Lu, M.S., Nanyang Technological University, Singapore, 2002. 4. Jan Lif, Ph.D., Royal Institute of Technology, Stockholm, Sweden, 2004. 5. Orlando Girlanda, Ph.D., Karlstad University, Karlstad, Sweden, 2006. 6. Sharon Nai-Mui Ling, Ph.D., National University of Singapore, Singapore, 2008.

Post-Doctoral Fellows (Supervised) 1. Yige Chen, Ph.D., Washington State University, 1992-93 2. Shun-Tien Lin, Ph.D., University of Wisconsin, 1995-97 3. Steve Suh, Ph.D., Texas A&M University, 1997-99 4. M. Kaysar Rahim, Ph.D., Auburn University, 2005-2008

Exhibit 100200103

Exhibit 1002

TEACHING (Other Contributions)

Courses and Curricula Developed

1. ME 636 - Mechanics of Composite Materials. Introduced as a new graduate level course at Auburn University in 1987. This course evolved into the semester course MECH 7360 - Mechanics of Composite Materials. Has been taught 16 times from 1987-2015.

2. ME 591 - Electronic Packaging Stress Analysis. Introduced as a new senior-graduate level course at Auburn University in 1999. This course has evolved to the semester course MECH 6310 - Mechanics of Electronic Packaging.

3. MECH 7340 - Inelastic Stress Analysis. Introduced as a new graduate level course at Auburn University in 2004.

Awards Received for Teaching

1. Outstanding Faculty Member, Department of Mechanical Engineering, Auburn University, 1989-90 2. Pi Tau Sigma Teacher of the Year, Department of Mechanical Engineering, Auburn University, 1989-90. 3. Birdsong Superior Teaching Award, College of Engineering, Auburn University, 1994

Exhibit 100200104

Exhibit 1002

PUBLICATIONS

Books

1. Suhling, J. C. (Editor), Applications of Experimental Mechanics to Electronic Packaging, ISBN: 0-7918-1739-3, EEP - Vol. 13, ASME, 1995.

2. Suhling, J. C., Liechti, K., and Liu, S., (Editors), Applications of Experimental Mechanics to Electronic Packaging - 1997, ISBN: 0-7918-1850-0, EEP - Vol. 22, ASME, 1997.

3. Dally, J. W., Lall, P., and Suhling, J. C., Mechanical Design of Electronic Systems, College House Publishers, 2008.

Book Chapters

1. Suhling, J. C. and Turner, J. L., “Stress and Strain Analysis” in the Manual on Experimental Stress Analysis, 5th Edition, Edited by J. F. Doyle, Prentice Hall, pp. 1-14, 1989.

2. Suhling, J. C. and Lall, P., “Electronic Packaging Applications,” Chapter 36, Handbook of Experimental Solid Mechanics, Springer, pp. 1015-1044, 2008.

3. Lall, P., Islam, S., Tian, G., Suhling, J. C., and Shinde, D., “Nano-Underfills for Fine-Pitch Electronics,” Chapter 14, Nanopackaging – Nanotechnologies and Electronic Packaging, pp. 287-323, Springer, 2008.

4. Hasnine, M., Mustafa, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., and Lall, P., “Nanomechanical Characterization of Lead Free Solder Joints,” Chapter 2, MEMS and Nanotechnology, Volume 5, pp. 11-22, Springer, 2014.

5. Hasnine, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., and Lall, P., “Application of Nanoindentation and Microdiffraction to Study Aging Effects in Lead Free Solder Interconnects,” Chapter 11, MEMS and Nanotechnology, Volume 5, pp. 73-88, Springer, 2016.

Refereed Articles in Archival Periodicals (Journals, Annuals, etc.)

1. Suhling, J. C., Rowlands, R. E., Johnson, M. W. and Gunderson, D. E., “Tensorial Strength Analysis of Paperboard,” Experimental Mechanics, Vol. 25(1), pp. 75-84, 1985.

2. Rowlands, R. E., Gunderson, D. E., Suhling, J. C. and Johnson, M. W., “Biaxial Strength of Paperboard Predicted by Hill-Type Theories,” Journal of Strain Analysis, Vol. 20(2), pp. 121-127, 1985.

3. Suhling, J. C., “Evaluation of Nonlinear Plate Theories Describing the Mechanical Response of Paperboard,” Developments in Theoretical and Applied Mechanics, Vol. 14, pp. 322-329, 1988.

4. Zhang, S. Q., Jang, B. Z., Valaire, B. T. and Suhling, J. C., “A New Criterion for Composite Material Mixed Mode Fracture Analysis,” Engineering Fracture Mechanics, Vol. 34(3), pp. 749-769, 1989.

Exhibit 100200105

Exhibit 1002

Refereed Articles in Archival Periodicals (Journals, Annuals, etc.) (Continued)

5. Lin, C. H., Suhling, J. C. and Turner, J. L., “Detection and Evaluation of Flaws in Composite Materials Using Digital Comparative Holography,” Developments in Theoretical and Applied Mechanics, Vol. 15, pp. 780-788, 1990.

6. Zhang, S. Q., Jang, B. Z., Valaire, B. T. and Suhling, J. C., “A New Criterion for Composites Mode II Fracture Analysis,” Engineering Fracture Mechanics, Vol. 36(1), pp. 49-59, 1990.

7. Valaire, B. T., Wong, Y. W., Suhling, J. C., Jang, B. Z., and Zhang, S. Q., “Application of the J-Integral to Mixed Mode Fracture Analysis of Orthotropic Composites, Engineering Fracture Mechanics, Vol. 36(3), pp. 507-514, 1990.

8. Zhang, S. Q., Valaire, B. T., Suhling, J. C. and Jang, B. Z., “An Energy-Based Mode III Fracture Criterion for Composites,” Engineering Fracture Mechanics, Vol. 38(6), pp. 353-360, 1991.

9. Bittle, D. A., Suhling, J. C., Beaty, R. E., Johnson, R. W., and Jaeger, R. C., “Piezoresistive Stress Sensors for Structural Analysis of Electronic Packages,” Journal of Electronic Packaging, Vol. 113(3), pp. 203-215, 1991.

10. Huang, H. M., Lin, C. H., Suhling, J. C. and Rowlands, R. E., “Determining the Three Individual Stress Components from Measured Isochromatic Fringes,” Experimental Mechanics, Vol. 31(4), pp. 310-318, 1991.

11. Jaeger, R. C., Beaty, R. E., Suhling, J. C., Johnson, R. W. and Butler, R. D., “Evaluation of Piezoresistive Coefficient Variation in Silicon Stress Sensors Using a Four-Point Bending Test Fixture,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 15(5), pp. 904-914, 1992.

12. Liang, S. and Suhling, J. C., “Finite Element Modeling of the Embossing of Paper Sheets,” Products of Papermaking, Vol. 10, pp. 1073-1100, 1993.

13. Jaeger, R. C., Suhling, J. C., Carey, M. T. and Johnson, R. W., “Off-Axis Piezoresistive Sensors for Measurement of Stress in Electronic Packaging,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology (Advanced Packaging), Vol. 16(8), pp. 925-931, 1993.

14. Jaeger, R. C., Suhling, J. C. and Ramani, R., “Errors Associated with the Design, Calibration of Piezoresistive Stress Sensors in (100) Silicon,” IEEE Transactions on Components, Packaging, and Manufacturing Technology (Advanced Packaging), Vol. 17(1), pp. 97-107, 1994

15. Knight, R. W., Johnson, R. W., Suhling, J. C., Evans, J. L., Romanczuk, C. S. and Burcham, S. W., “Thermal Analysis: Modeling the Thermal Performance of an Automotive Powertrain Controller’s Components Mounted on an Insulated Metal Substrate,” Advanced Packaging, Vol. 3(1), pp. 30-34, 1994.

16. Yim, J. H., Jang, B. Z., Suhling, J. C. and Gillespie, J. W., “The Influence of Transverse Shear Deformation on the Damping of 0o Unidirectional Laminated Composites,” Korean Journal of Composite Materials, Vol. 10(4), pp. 26-35, 1997.

17. Zou, Y., Suhling, J. C., Johnson, R. W., Jaeger, R. C., and Mian, A. K. M., "In-Situ Stress State Measurements During Chip-on-Board Assembly," IEEE Transactions on Electronics Packaging Manufacturing, Vol. 22(1), pp. 38-52, 1999.

Exhibit 100200106

Exhibit 1002


18. Yim, J. H., Jang, B. Z., Suhling, J. C., and Gillespie, J. W., “Effects of Interlaminar Stresses on Damping of 0-Degree Unidirectional Laminated Composites,” Polymer Composites, Vol. 20(6), pp. 796-803, 1999.

19. Jaeger, R. C., Suhling, J. C., Ramani, R., Bradley, A. T., Xu, J., “CMOS Stress Sensors on (100) Silicon,” IEEE Journal of Solid State Circuits, Vol. 35(1), pp. 85-95, 2000.

20. Suhling, J. C. and Jaeger, R. C., “Measurement of Stress Distributions on Silicon IC Chips Using Piezoresistive Sensors,” Nontraditional Methods of Sensing Stress, Strain and Damage in Materials and Structures, Vol. 2, pp. 127-152, ASTM (STP 1323), 2000.

21. Suhling, J. C., and Jaeger, R. C., “Silicon Piezoresistive Stress Sensors and Their Application in Electronic Packaging,” IEEE Sensors Journal, Vol. 1(1), pp. 14-30, 2001.

22. Bradley, A. T., Jaeger, R. C., Suhling, J. C., and O’Connor, K. J., “Piezoresistive Characteristics of Short-Channel MOSFETS on (100) Silicon,” IEEE Transactions on Electron Devices, Vol. 48(9), pp. 2009-2015, 2001.

23. Rahim, M. K., Suhling, J. C., Johnson, R. W., and Jaeger, R. C., “Characterization of Die Stress in Flip Chip on Laminate Assemblies,” Advancing Microelectronics, Vol. 30(1), pp. 6-9, 2003

24. Suhling, J. C., Gale, H. S., Johnson, R. W., Islam, M. N., Shete, T., Lall, P., Bozack, M. J., Evans, J. L., Seto, P., Gupta, T., and Thompson, J. R., “Thermal Cycling Reliability of Lead Free Chip Resistor Solder Joints,” Soldering and Surface Mount Technology, Vol. 16(2), pp. 77-87, 2004.

25. Lall, P., Islam, N., Suhling, J. C., and Darveaux, R., “Model for BGA and CSP Reliability in Automotive Underhood Applications,” IEEE Transactions on Components and Packaging Technologies, Vol. 27(3), pp. 585-593, 2004.

26. Rickett, B., Elmgren, P., Flowers, G., Gale, S., and Suhling, J., “Whisker Formation Potential in Pb-Free Electroplated Connector Finishes,” Circuits and Assembly, Vol. 16(2), pp. 52-59, 2005.

27. Rahim, M. K., Suhling, J. C., Copeland, D. S., Islam, M. S., Jaeger, R. C., Lall, P., Johnson, R. W., “Die Stress Characterization in Flip-Chip Assemblies,” IEEE Transactions on Components and Packaging Technologies, Vol. 28(3), pp. 415-429, 2005.

28. Islam, M. S., Suhling, J. C., and Lall, P., “Measurement of the Temperature Dependent Constitutive Behavior of Underfill Encapsulants,” IEEE Transactions on Components and Packaging Technologies, Vol. 28(3), pp. 467-476, 2005.

29. Lall, P., Singh, N., Suhling, J. C., Strickland, M., and Blanche, J., “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” IEEE Transactions on Components and Packaging Technologies, Vol. 28(3), pp. 457-466, 2005.

30. Lall, P., Islam, M. N., and Suhling, J. C., “Damage Mechanics of Electronics on Metal-Backed Substrates in Harsh Environments,” IEEE Transactions on Components and Packaging Technologies, Vol. 29(1), pp. 204-212, 2006.

Exhibit 100200107

Exhibit 1002


31. Mian, A. K. M., Suhling, J. C., and Jaeger, R. C., “The van der Pauw Stress Sensor,” IEEE Sensors Journal, Vol. 6(2), pp. 340-356, 2006.

32. Lall, P., Islam, M. N., Rahim, K., and Suhling, J. C., “Prognostics and Health Management of Electronic Packaging,” IEEE Transactions on Components and Packaging Technologies, Vol. 29(3), pp. 666-677, 2006.

33. Lall, P., Panchagade, D., Liu, Y., Johnson, W., and Suhling, J. C., “Models for Reliability Prediction of Fine-Pitch BGAs and CSPs in Shock and Drop-Impact,” IEEE Transactions on Components and Packaging Technologies, Vol. 29(3), pp. 464-474, 2006.

34. Lall, P., Gupte, S., Choudhary, P., and Suhling, J., “Solder-Joint Reliability in Electronics Under Shock and Vibration using Explicit Finite Element Submodeling,” IEEE Transactions on Electronics Manufacturing, Vol. 30(1), pp. 74-83, 2007.

35. Lall, P. Panchagade, D., Liu, Y., Johnson, W., and Suhling, J., “Smeared Property Models for Shock-Impact Reliability of Area-Array Packages,” Journal of Electronic Packaging, Vol. 129(4), pp. 373-381, 2007.

36. Lall, P., Islam, N, Evans, J., and Suhling, J., “Reliability of Ball Grid Arrays and Chip-Scale Packages on Metal-Backed Printed Circuit Boards in Harsh Environments,” Journal of Electronic Packaging, Vol. 129(4), pp. 382-390, 2007.

37. Lall, P., Hande, M., Bhat, C., Islam, N, Suhling, J., and Lee, J., “Feature Extraction and Damage-Precursors for Prognostication of Lead-Free Electronics,” Microelectronics Reliability, Vol. 47(4), pp. 1907-1920, 2007.

38. Lall, P., Panchagade, D., Choudhary, P., Gupte, S., Suhling, J. C., "Failure-Envelope Approach to Modeling Shock and Vibration Survivability of Electronic and MEMS Packaging," IEEE Transactions on Components and Packaging Technologies, Vol. 31(1), pp. 104-113, 2008.

39. Lall, P., Islam, S., Tian, G., and Suhling, J. C., “Nano-Underfills for High-Reliability Applications in Extreme Environments,” IEEE Transactions on Components and Packaging Technologies, Vol. 31(1), pp. 114-125, 2008.

40. Lall, P., Choudhary, P., Gupte, S., and Suhling, J. C., “Health Monitoring for Damage Initiation and Progression During Mechanical Shock in Electronic Assemblies,” IEEE Transactions on Components and Packaging Technologies, Vol. 31(1), pp. 173-183, 2008.

41. Cho, C. H., Jaeger, R. C., Suhling, J. C., Kang, Y., and Mian, A., “Characterization of the Temperature Dependence of the Pressure Coefficients of n- and p-Type Silicon Using Hydrostatic Testing, IEEE Sensors Journal, Vol. 8(4), pp. 392-400, 2008.

42. Cho, C. H., Jaeger, R. C., and Suhling, J. C., “Characterization of the Temperature Dependence of the Piezoresistive Coefficients of Silicon from -150 C to +125 C,” IEEE Sensors Journal, Vol. 8(8), pp. 1455-1468, 2008.

43. Cho, C. H., Jaeger, R. C., and Suhling, J. C., “The Effect of the Transverse Sensitivity on Measurement of the Piezoresistive Coefficients of Silicon,” Japanese Journal of Applied Physics, Vol. 47(5), pp. 3647-3656, 2008.

Exhibit 100200108

Exhibit 1002


44. Cho, C. H., Jaeger, R. C., and Suhling, J. C., “Evaluation of the Temperature Dependence of the Combined Piezoresistive Coefficients of (111) Silicon Utilizing Chip-on-Beam and Hydrostatic Calibration,” Journal of the Korean Physical Society, Vol. 52(3), pp. 612-620, 2008.

45. Angadi, S. V., Jackson, R. L., Choe, S. Y., Flowers, G. T., Suhling, J. C., Chang, Y. K., and Ham, J. K., “Reliability and Life Study of Hydraulic Solenoid Valve Part 1: A Multi-Physics Finite Element Model,” Engineering Failure Analysis, 2008.

46. Angadi, S. V., Jackson, R. L., Choe, S. Y., Flowers, G. T., Suhling, J. C., Chang, Y. K., Ham, J. K., and Bae, J. I., “Reliability and Life Study of Hydraulic Solenoid Valve Part 2: Experimental Study,” Engineering Failure Analysis, 2008.

47. Lall, P., Shah, M., Drake, L., Moore, T., and Suhling, J., “Thermo-mechanical Reliability Management Models for Area-Array Packages on Cu-Core and No-Core Assemblies,” Journal of Surface Mount Technology, Vol. 21(3), pp. 20-35, 2008.

48. Lall, P., Islam, N., Choudhary, P., Suhling, J. C., "Leading Indicators of Failure for Prognostication of Leaded and Lead-Free Electronics In Harsh Environment," IEEE Transactions on Components and Packaging Technologies, Vol. 32(1), pp. 135-144, 2009.

49. Ma, H., and Suhling, J. C., “A Review of Mechanical Properties of Lead-Free Solders for Electronic Packaging,” Journal of Materials Science, Vol. 44, pp. 1141-1158, 2009.

50. Xie, F., Flowers, G. T., Chen, C., Bozack, M., Suhling, J., Rickett, B. I., Malucci, R. D., and Manlapaz, C., “Analysis and Prediction of Vibration-Induced Fretting Motion in a Blade/Receptacle Connector Pair,” IEEE Transactions on Components and Packaging Technologies, Vol. 32(3), pp. 583-590, 2009.

51. Bozack, M. J., Crandall, E. R., Rodekohr, C. L., Dean, R. N., Flowers, G. T., and Suhling, J. C., “High Lateral Resolution Auger Electron Spectroscopic (AES) Measurements for Sn Whiskers on Brass,” IEEE Transactions on Electronics Packaging Manufacturing, Vol. 33(3), pp. 198-204, 2010.

52. Meng, W., and Suhling, J. C., “Combined Controller for Test System of High Capacity Hydraulic Pump,” Journal of Dynamic Systems, Measurement, and Control, Vol. 132(3), Paper 054502, pp. 1-7, 2010.

53. Bozack, M. J., Suhling, J. C., Zhang, Y., Cai, Z., and Lall, P., Surfaces of Mixed Formulation Solder Alloys at Melting, Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, Vol. 29(4), Paper 041401, pp. 1-9, 2011.

54. Bozack, M. J., Suhling, J. C., Zhang, Y., Cai, Z., Lall, P., “Influence of Surface Segregation on Wetting of Sn-Ag-Cu (SAC) Series and Pb-Containing Solder Alloys,” Journal of Electronic Materials, Vol. 40(10), pp. 2093-2104, 2011.

55. Roberts, J. C., Motalab, M., Hussain, S., Suhling, J. C., Jaeger, R. C., Lall, P., “Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping,” Journal of Electronic Packaging, Vol. 134(3), Paper 031005, pp. 1-17, 2012.

Exhibit 100200109

Exhibit 1002


56. Zhang, J., Hai, Z., Thirugnanasambandam, S., Evans, J. L., Bozack, M. J., Sesek, R., Zhang, Y., Suhling, J. C., “Correlation of Aging Effects on Creep Rate and Reliability in Lead Free Solder Joints,” SMTA Journal, Volume 25(3), pp. 19-28, 2012.

57. Chen, Y., Jaeger, R. C., and Suhling, J. C., “CMOS Sensor Arrays for High Resolution Die Stress Mapping in Packaged Integrated Circuits,” IEEE Sensors Journal, Vol. 13(6), pp. 2066-2076, 2013.

58. Zhang, J., Hai, Z., Thirugnanasambandam, S., Evans, J. L., Bozack, M. J., Zhang, Y., Suhling, J. C., “Thermal Aging Effects on Thermal Cycling Reliability of Lead-Free Fine Pitch Packages,” IEEE Transactions on Components and Packaging Technologies, Vol. 3(8), pp. 1348-1357, 2013.

59. Jaeger, R. C., Motalab, M., Hussain, S., and Suhling, J. C., “Four-Wire Bridge Measurements of Silicon van der Pauw Stress Sensors,” Journal of Electronic Packaging, Vol. 136(4), Paper 041014, pp. 1-10, 2014.

60. Hai, Z., Zhang, J., Shen, C., Snipes, E. K., Suhling, J. C., Bozack, M. J., and Evans, J. L., “Reliability Degradation of SAC105 and SAC305 BGA Packages Under Long-Term, High Temperature Aging,” SMTA Journal, Vol. 27(2), pp. 11-18, 2014.

61. Hai, Z., Zhang, J., Shen, C., Snipes, E. K., Bozack, M. J., Evans, J. L., and Suhling, J. C., “Reliability Performance of Lead–Free SAC Solder Joints on Electroless Ni/Immersion Au and Electroless Ni/Electroless Pd/Immersion Au Subject to Long–Term Isothermal Aging,” Journal of Mechatronics, Vol. 2(2), pp. 100-108, 2014.

62. Lall, P., Shantaram, S., Suhling, J., and Locker, D., “Stress-Strain Behavior of SAC305 at High Strain Rates,” Journal of Electronic Packaging, Vol. 137(1), Paper 011010, pp. 1-16, 2015.

63. Hai, Z., Zhang, J., Shen, C., Evans, J. L., Bozack, M. J., Basit, M. M., and Suhling, J. C., “Reliability Comparison of Aged SAC Fine-Pitch Ball Grid Array Packages Versus Surface Finishes,” IEEE Transaction on Components, Packaging, and Manufacturing Technology, Vol. 5(6), pp. 828-837, 2015.

64. Mustafa, M., Suhling, J. C., and Lall, P., “Experimental Determination of Fatigue Behavior of Lead Free Solder Joints in Microelectronic Packaging Subjected to Isothermal Aging,” Microelectronics Reliability, Vol. 56, pp. 136-147, 2016.

65. Zhao, C., Shen, C., Hai, Z., Basit, M. M., Zhang, J., Bozack, M. J., Evans, J. L., and Suhling, J. C., “Term Aging Effects on the Reliability of Lead Free Solder Joints in Ball Grid Array Packages with Various Pitch Sizes and Ball Arrangements,” SMTA Journal, Vol. 29(2), pp. 37-46, 2016.

66. Gnanachchelvi, P., Jaeger, R. C., Wilamowski, B. W., Hussain, S., Suhling, J. C., and Hamilton, M. C., “Performance Enhancement in Bipolar Junction Transistors Using Uniaxial Stress on (100) Silicon,” IEEE Transactions on Electron Devices, Vol. 63(7), pp. 2643-2649, 2016.

67. Gnanachchelvi, P., Wilamowski, B. W., Jaeger, R. C., Hussain, S., Suhling, J. C., and Hamilton, M. C., “A 1D Numerical Model for Rapid Stress Analysis in Bipolar Junction Transistors, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, to Appear in Vol. 29, pp. 1-18, 2016.

Exhibit 100200110

Exhibit 1002

Conference Proceedings (Full Articles with Various Levels of Review)

1. Johnson, M. W. and Suhling, J. C., “Thin Plate Theories for Orthotropic Nonlinear Elastic Materials,” Proceedings of the XVIth International Congress of Theoretical and Applied Mechanics of IUTAM, pp. 1-6, The Technical University of Denmark, Lyngy, Denmark, August 19-25, 1984.

2. Suhling, J. C., Rowlands, R. E., Johnson, M. W. and Gunderson, D. E., “Evaluation of Strength Predictions for Paperboard,” Proceedings of the 1985 SEM Spring Conference on Experimental Mechanics, pp. 134-141, Las Vegas, NV, June 9-14, 1985.

3. Chambless, D. A., Suhling, J. C., Swinson, W. F. and Turner, J. L., “A New Hybrid Photoelastic-Finite Element Technique for Stress Analysis,” Proceedings of the 1986 SEM Spring Conference Spring Conference on Experimental Mechanics, pp. 991-998, New Orleans, LA, June 8-13, 1986.

4. Suhling, J. C., Swinson, W. F. and Turner, J. L., “Photoelastic Analysis of a Two-Dimensional Structure,” Proceedings of the 1986 SEM Spring Conference Spring Conference on Experimental Mechanics, pp. 180-184, New Orleans, LA, June 8-13, 1986.

5. Suhling, J. C., “Formulation and Application of Nonlinear Constitutive Relations for Paperboard,” Proceedings of the 1986 International Paper Physics Seminar: Solid Mechanics Advances in Paper Related Industries, pp. 353-354, Blue Mountain Lake, New York, August 10-12, 1986.

6. Suhling, J. C., Rowlands, R. E., Johnson, M. W. and Gunderson, D. E., “Analytical-Experimental Investigation of the Constitutive Behavior of Paperboard,” Proceedings of the 1986 SEM Fall Conference on Experimental Mechanics, pp. 150-158, Keystone, CO, November 2-5, 1986.

7. Suhling, J. C., Rowlands, R. E., Johnson, M. W. and Gunderson, D. E., “Analysis of the Burst Test for Paperboard Strength,” Proceedings of the 1987 SEM Spring Conference on Experimental Mechanics, pp. 828-837, Houston, TX, June 15-19, 1987.

8. Suhling, J. C., “Analysis of Paperboard Deformations Using Nonlinear Plate and Membrane Models,” Proceedings of the 1987 International Paper Physics Conference, pp. 139-144, Mont-Rolland, Quebec, Canada, September 15-18, 1987.

9. Suhling, J. C., Considine, J. M., Yeh, K. C. and Gunderson, D. E., “Effects of Moisture on Paperboard Biaxial Strength,” Proceedings of the 19th International Paper Science Symposium (1998 International Paper Physics Seminar), pp. 1-6, Miami University, Oxford, Ohio, May 16-19, 1988.

10. Suhling, J. C., “An Analytical-Experimental Investigation of Nonlinear Orthotropic Sheets Undergoing Large Cylindrical Deformations,” Proceedings of the VIth International Congress on Experimental Mechanics, pp. 312-321, Portland, OR, June 5-10, 1988.

11. Eiland, R., Chambless, D. A., Suhling, J. C., Swinson, W. F. and Turner, J. L., “Hybrid Stress Analysis Techniques Combining the Boundary Element Method and Photoelastic Experimental Data,” Proceedings of the VIth International Congress on Experimental Mechanics, pp. 968-974, Portland, OR, June 5-10, 1988.

Exhibit 100200111

Exhibit 1002

Conference Proceedings (Full Articles with Various Levels of Review) (Continued)

12. Zhang, S. Q., Valaire, B. T., Suhling, J. C. and Jang, B. Z., “A Fracture Criterion for Composites Using an Energy Approach,” Proceedings of the Seventh International Conference on Fracture (ICF-7), Houston, TX, March 20-24, 1989.

13. Lin, C. H., Genge, G. G., Pearce, L. J., Suhling, J. C. and Turner, J. L., "Evaluation of Damage in Composite Materials Using Digital Comparative Holography," Proceedings of the 1989 SEM Spring Conference on Experimental Mechanics, pp. 18-26, Cambridge, MA, May 28-June 2, 1989.

14. Zhang, S. Q., Jang, B. Z., Valaire, B. T. and Suhling, J. C., "A New Energy-Based Criterion for Mixed Mode Fracture Analysis of Composite Materials," Proceedings of the 1989 SEM Spring Conference on Experimental Mechanics, pp. 503-512, Cambridge, MA, May 28-June 2, 1989.

15. Suhling, J. C., Considine, J. M. and Yeh, K. C., "Effects of Moisture on the Biaxial Strength of Wood-Based Composites," Proceedings of the 1989 SEM Spring Conference on Experimental Mechanics, pp. 602-609, Cambridge, MA, May 28-June 2, 1989.

16. Suhling, J. C., Gunderson, D. E., Rowlands, R. E. and Johnson, M. W., "Off-Axis Uniaxial Stress-Strain Behavior of a Nonlinear Composite Material," Proceedings of the 1989 SEM Spring Conference on Experimental Mechanics, pp. 619-631, Cambridge, MA, May 28-June 2, 1989.

17. Suhling, J. C., Johnson, M. W., Rowlands, R. E. and Gunderson, D. E., “A Nonlinear Elastic Constitutive Theory for Cellulosic Materials,” Mechanics of Cellulosic and Polymeric Materials, ASME, AMD - Vol. 99, Edited by R. W. Perkins, pp. 1-13, ASME/ASCE Joint Mechanics Conference, University of California - San Diego, LaJolla, CA, July 9-12, 1989.

18. Lin, S. T. and Suhling, J. C., “Supercomputer Analysis of Paperboard Structures,” Mechanics of Cellulosic and Polymeric Materials, ASME, AMD - Vol. 99, Edited by R. W. Perkins, pp. 113-123, ASME/ASCE Joint Mechanics Conference, University of California - San Diego, LaJolla, CA, July 9-12, 1989.

19. Lin, C. H., Genge, G. G., Pearce, L. J. and Suhling, J. C., “Detection and Evaluation of Flaws in Composite Materials Using Digital Comparative Holography," Proceedings of the 7th International Conference on Composite Materials, Vol. 1, pp. 663-669, Guangzhou, China, November 22-24, 1989.

20. Zhang, S. Q., Jang, B. Z., Valaire, B. T. and Suhling, J. C., "The Z-Criterion for Composite Material Fracture Analysis," in the Proceedings of the 7th International Conference on Composite Materials, Vol. 2, pp. 614-620, Guangzhou, China, November 22-24, 1989.

21. Suhling, J. C., Considine, J. M. and Yeh, K. C., "Application of the Tensor Polynomial Failure Criterion to Wood-Based Composites," Proceedings of the 7th International Conference on Composite Materials, Vol. 4, pp. 226-228, Guangzhou, China, November 22-24, 1989.

Exhibit 100200112

Exhibit 1002


22. Suhling, J. C. and Lin, S. T., "Plane Stress Applications of a Nonlinear Elastic Constitutive Theory for Composite Materials," Proceedings of the 7th International Conference on Composite Materials, Vol. 4, pp. 232-234, Guangzhou, China, November 22-24, 1989.

23. Lin, C. H. and Suhling, J. C., "Nondestructive Evaluation of Vibrating Composite Plates Using Time-Average Digital Comparative Holography," Proceedings of the International Congress on Recent Developments in Air- and Structure-Borne Sound and Vibration, pp. 647-654, Auburn, AL, March 6-8, 1990.

24. Suhling, J. C., “Continuum Models for the Mechanical Response of Paper and Paper Composites: Past, Present, and Future,” Materials Interactions Relevant to the Pulp, Paper and Wood Industries, Materials Research Society Proceedings, Vol. 197, pp. 245-255, 1990 Spring Meeting, San Francisco, CA, April 16-21, 1990.

25. Beaty, R. E., Suhling, J. C., Moody, C. A., Bittle, D. A., Johnson, R. W., Butler, R. D. and Jaeger, R. C., “Calibration Considerations for Piezoresistive-Based Stress Sensors,” Proceedings of the 40th Electronic Components and Technology Conference, pp. 797-806, Las Vegas, NV, May 20-22, 1990.

26. Pearce, L. J. and Suhling, J. C., “Determination of Thermally Induced Stresses and Deformations in Thin Composite Plates by the Finite Element Method,” Proceedings of the 1990 SEM Spring Conference on Experimental Mechanics, pp. 95-103, Albuquerque, NM, June 3-6, 1990.

27. Yeh, K. C., Considine, J. M. and Suhling, J. C., “Effects of Moisture on the Shear Behavior of Wood-Based Composites,” Proceedings of the 1990 SEM Spring Conference on Experimental Mechanics, pp. 193-200, Albuquerque, NM, June 3-6, 1990.

28. Huang, Y. M., Lin, C. H., Suhling, J. C. and Rowlands, R. E., “Determination of the Three Individual Stress Components from Measured Isochromatics Only,” Proceedings of the 1990 SEM Spring Conference on Experimental Mechanics, pp. 665-671, Albuquerque, NM, June 3-6, 1990.

29. Wu, Y. P., Eiland, R. J., Suhling, J. C. and Turner, J. L., “Application of a New Hybrid Stress Analysis Technique Combining the Boundary Element Method and Photoelastic Experimental Data,” Proceedings of the 1990 SEM Spring Conference on Experimental Mechanics, pp. 672-679, Albuquerque, NM, June 3-6, 1990.

30. Pearce, L. J., Li, H. P., Considine, J. M. and Suhling, J. C., "Investigation on the Curl of Partially-Constrained Multilayer Papers," Proceedings of the 1990 International Paper Physics Seminar, pp. 1-44, Kalamazoo, MI, September 30-October 3, 1990.

31. Beaty, R. E., Johnson, R. W., Suhling, J. C., Bittle, D. A., Pope, J. C. and Jaeger, R. C., “Stress Measurement in Electronic Packaging Using Silicon Piezoresistive Sensors,” Proceedings of TECHCON 90, pp. 413-416, San Jose, CA, October 16-18, 1990.

Exhibit 100200113

Exhibit 1002


32. Lin, S. T., Suhling, J. C., Johnson, M. W. and Rowlands, R. E., “A Combined Analytical-Experimental-Numerical Analysis of the Burst Test for Paperboard Strength,” Mechanics of Wood and Paper Materials, ASME, AMD - Vol. 112, pp. 71-84, 1990 ASME Winter Annual Meeting, Dallas, TX, November 25-30, 1990.

33. Yeh, K. C., Considine, J. M. and Suhling, J. C., “Experimental Measurement of the Influence of Moisture on the Shear Behavior of Cellulosic Materials,” Mechanics of Wood and Paper Materials, ASME, AMD - Vol. 112, pp. 9-16, 1990 ASME Winter Annual Meeting, Dallas, TX, November 25-30, 1990.

34. Bittle, D. A., Suhling, J. C., Beaty, R. E., Johnson, R. W., and Jaeger, R. C., “Structural Analysis of Electronic Packages Using Test Chips with Integral Piezoresistive Stress Sensors,” ASME Paper 90-WA/EEP-12, pp. 1-13, Symposium on Structural Analysis of Electronic Packages and Fiber Optics, 1990 ASME Winter Annual Meeting, Dallas, TX, November 25-30, 1990.

35. Yeh, K. C., Considine, J. M. and Suhling, J. C., “Experimental Investigation on the Effects of Moisture on the Poisson’s Ratios of Wood-Based Composites,” Proceedings of the 1991 SEM Spring Conference on Experimental Mechanics, pp. 632-638, Milwaukee, WI, June 9-12, 1991.

36. Suhling, J. C., Beaty, R. E., Jaeger, R. C. and Johnson, R. W., “Piezoresistive Sensors for Measurement of Thermally-Induced Stresses in Microelectronics,” Proceedings of the 1991 SEM Spring Conference on Experimental Mechanics, pp. 683-694, Milwaukee, WI, June 9-12, 1991.

37. Carey, M. T., Suhling. J. C. and Johnson, R. W., “Piezoresistive Stress Sensors for High Temperature Microelectronics,” Transactions of the First International High Temperature Electronics Conference, pp. 159-165, Albuquerque, NM, June 16-20, 1991.

38. Yeh, K. C., Considine, J. M. and Suhling. J. C., “The Influence of Moisture on the Nonlinear Mechanical Behavior of Cellulosic Materials,” Proceedings of the 1991 International Paper Physics Conference, pp. 695-711, Kona, HI, September 22-27, 1991.

39. Suhling, J. C., Carey, M. T., Johnson, R. W. and Jaeger, R. C., “Stress Measurement in Microelectronic Packages Subjected to High Temperatures,” Manufacturing Processes and Materials Challenges in Microelectronic Packaging, ASME, AMD - Vol. 131, pp. 143-152, ASME 1991 Winter Annual Meeting, Atlanta, GA, December 1-6, 1991.

40. Jaeger, R. C., Suhling, J. C. and Ramani, R., “Errors Associated with the Design and Calibration of Piezoresistive Stress Sensors in (100) Silicon,” Advances in Electronic Packaging - Proceedings of the First ASME-JSME Joint Conference on Electronic Packaging, pp. 447-456, San Jose, CA, April 9-12, 1992.

41. Kang, Y. L, Suhling, J. C. and Jaeger, R. C., “Piezoresistive Stress Sensors on (110) Silicon Wafers,” Proceedings of the VIIth International Congress on Experimental Mechanics, pp. 705-712, Las Vegas, NV, June 7-11, 1992.

Exhibit 100200114

Exhibit 1002


42. Liang, S. and Suhling, J. C., “Investigation on the Embossing of Thin Nonlinear Orthotropic Sheets,” Proceedings of the VIIth International Congress on Experimental Mechanics, pp. 732-743, Las Vegas, NV, June 7-11, 1992.

43. Kang, Y. L, Suhling, J. C. and Jaeger, R. C., “Piezoresistive Stress Sensors on Alternative Crystal Planes,” ASME Paper 92-WA/EEP-17, pp. 1-10, 1992 ASME Winter Annual Meeting, Anaheim, CA, November 8-13, 1992.

44. Luo, S., Suhling, J. C., Considine, J. M. and Laufenberg, T. L., “The Bending Stiffnesses of Corrugated Board”, Mechanics of Cellulosic Materials, Edited by R. W. Perkins, ASME, AMD - Vol. 145, pp. 15-26, 1992 ASME Winter Annual Meeting, Anaheim, CA, November 8-13, 1992.

45. Jaeger, R. C., Suhling, J. C., Carey, M. T. and Johnson, R. W., “A Piezoresistive Sensor Chip for Measurement of Stress in Electronic Packaging,” Proceedings of 1993 IEEE Electronic Components and Technology Conference, pp. 686-692, Orlando, FL, June 2-4, 1993.

46. Hung, S. C. and Suhling, J. C., “The Effects of Strain Rate on the In-Plane Shear Modulus of Wood-Based Composites,” Proceedings of the 1993 SEM Spring Conference on Experimental Mechanics, pp. 705-714, Dearborn, MI, June 7-9, 1993.

47. Suhling, J. C., Jaeger, R. C., Kang, Y. L. and Cordes, R. A., “A New Wafer-Level Calibration Procedure for Piezoresistive Stress Sensors,” Proceedings of the 1993 SEM Spring Conference on Experimental Mechanics, pp. 977-987, Dearborn, MI, June 7-9, 1993.

48. Jaeger, R. C., Suhling, J. C. and Ramani, R., “Thermally-Induced Errors in the Calibration and Application of Silicon Piezoresistive Stress Sensors,” Advances in Electronic Packaging 1993 - Proceedings of the 1993 ASME International Electronic Packaging Conference, pp. 457-470, Binghamton, NY, September 29-October 2, 1993.

49. Suhling, J. C., Johnson, R. W., White, J. D., Matthai, K. W., Knight, R. W., Romanczuk, C. S. and Burcham, S. W., “Solder Joint Reliability of Surface Mount Chip Resistors/Capacitors on Insulated Metal Substrates,” Proceedings of the 44th

Electronic Components and Technology Conference, pp. 465-473, Washington, DC, May 1-4. 1994.

50. Jaeger, R. C., Suhling, J. C. and Anderson, A. A., “A (100) Silicon Stress Test Chip with Optimized Piezoresistive Sensor Rosettes,” Proceedings of the 44th Electronic Components and Technology Conference, pp. 741-749, Washington, DC, May 1-4. 1994.

51. Suhling, J. C., Cordes, R. A., Kang, Y. L. and Jaeger, R. C., “Wafer-Level Calibration of Stress Sensing Test Chips,” Proceedings of the 44th Electronic Components and Technology Conference, pp. 1058-1070, Washington, DC, May 1-4. 1994.

Exhibit 100200115

Exhibit 1002


52. Kang, Y. L., Suhling, J. C., Johnson, R. W. and Jaeger, R. C., “Silicon and Silicon Carbide Stress Sensors for Application to Electronic Packaging,” Proceedings of the 1994 SEM Spring Conference on Experimental Mechanics, pp. 311-320, Baltimore, MD, June 6-8, 1994.

53. Luo, S., Suhling, J. C., and Laufenberg, T. L., “Experimental Measurement of the Bending Stiffnesses of Corrugated Board,” Proceedings of the 1994 SEM Spring Conference on Experimental Mechanics, pp. 699-707, Baltimore, MD, June 6-8, 1994.

54. Suhling, J. C., Jaeger, R. C. and Anderson, A. A., “Optimized Stress Sensors for Application to Electronic Packaging,” Proceedings of the International Conference on Advances in Engineering Measurements, Edited by R. Royles, pp. 9-15, Edinburgh, Scotland, August 30-September 1, 1994.

55. Suhling, J. C., Jaeger, R. C. and Ramani, R., “Stress Measurement Using 0-90 Piezoresistive Rosettes on (111) Silicon,” Mechanics and Materials for Electronic Packaging: Volume 1 - Design and Process Issues in Electronic Packaging, ASME, AMD - Vol. 195, pp. 65-73, 1994 ASME International Congress and Exposition, Chicago, IL, November 6-11, 1994.

56. White, J. D., Suhling, J. C., Johnson, R. W., Knight, R. W. and Romanczuk, C. S., “Reliability of Plastic Quad Flat Pack Solder Joints in Potted Automotive Engine Controllers,” Proceedings of ISHM ‘94, pp. 582-589, Boston, MA, November 15-17, 1994.

57. Suhling, J. C., “Nonlinear Finite Element Modelling of Paper and Paperboard,” Proceedings of the International Conference on Moisture-Induced Creep Behaviour of Paper and Board, pp. 205-221, Stockholm, Sweden, December 5-7, 1994.

58. Suhling, J. C., “Nonlinear Modelling of Paper Behavior: Embossing, Curl, Corrugated Board, and the Burst Test,” Proceedings of the Seminar on Constitutive Modelling for Time-Dependent Materials, pp. 1-45, Stockholm, Sweden, December 8-9, 1994.

59. Jaeger, R. C., Ramani, R. and Suhling, J. C., “Effects of Stress-Induced Mismatches on CMOS Analog Circuits,” Proceedings of the International Symposium on VLSI Technology, Systems, and Applications, pp. 354-360, Taipei, Taiwan, May 31-June 2, 1995.

60. Jaeger, R. C., Ramani, R., Suhling, J. C. and Kang, Y., “CMOS Stress Sensor Circuits Using Piezoresistive Field-Effect Transistors (PIFETs),” Proceedings of the 1995 Symposium on VLSI Circuits, pp. 43-44, Kyoto, Japan, June 8-10, 1995.

61. Suhling, J. C. and Lin, S. T., “Applications of Optical Methods to Electronic Packaging,” Proceedings of the 1995 SEM Spring Conference on Experimental Mechanics, pp. 109-114, Grand Rapids, MI, June 11-14, 1995.

62. Luo, S., Suhling, J. C. and Laufenberg, T. L., “Bending and Twisting Tests for Measurement of the Stiffnesses of Corrugated Board,” Mechanics of Cellulosic Materials - 1995, ASME, AMD - Vol. 209, pp. 91-109, ASME Summer Applied Mechanics and Materials Conference, Los Angeles, CA, June 28-30, 1995.

Exhibit 100200116

Exhibit 1002


63. Suhling, J. C. and Lin, S. T., “Applications of Optical Methods to Electronic Packaging,” in the Proceedings of the Symposium on Applications of Experimental Mechanics to Electronic Packaging, ASME, EEP - Vol. 13, pp. 39-45, ASME International Mechanical Engineering Congress and Exposition, San Francisco, CA, November 12-17, 1995.

64. Cordes, R. A., Suhling, J. C., Kang, Y. and Jaeger, R. C., “Application of a Wafer Level Calibration Technique for Stress Sensing Test Chips,” Proceedings of the Symposium on Applications of Experimental Mechanics to Electronic Packaging, ASME, EEP - Vol. 13, pp. 79-94, ASME International Mechanical Engineering Congress and Exposition, San Francisco, CA, November 12-17, 1995.

65. Cordes, R. A., Suhling, J. C., Kang, Y. and Jaeger, R. C., “Optimal Temperature Compensated Piezoresistive Stress Sensor Rosettes,” Proceedings of the Symposium on Applications of Experimental Mechanics to Electronic Packaging, ASME, EEP - Vol. 13, pp. 109-116, ASME International Mechanical Engineering Congress and Exposition, San Francisco, CA, November 12-17, 1995.

66. Johnson, R. W., Knight, R. W. and Suhling, J. C., “Thermo-Mechanical Analysis of Metal Backed Circuit Boards,” Proceedings of STAIF-96 (1st International Conference on Commercial Development of Space), pp. 245-250, Albuquerque, NM, January 7-11, 1996.

67. Lin, S. T., Suhling, J. C. and Johnson, R. W., “A Study on Surface Mount Chip Capacitor Reliability in Automotive Control Modules,” Proceedings of the Advanced Technology Workshop on Automotive Electronics, pp. 1-2, Atlantic Beach, NC, June 2-5, 1996.

68. Liang, S. and Suhling, J. C., “Finite Element and Experimental Study on the Embossing of Low Basis Weight Papers,” Proceedings of the 1996 International Progress in Paper Physics Seminar, pp. 23-26, Stockholm, Sweden, June 9-14, 1996.

69. Lin, S. T., Moral, R. J., Suhling, J. C., Jaeger, R. C. and Johnson, R. W., “Measurement of Die Stresses in Chip on Board Packages Using Piezoresistive Sensors,” Proceedings of the VIIIth International Congress on Experimental Mechanics, pp. 78-79, Nashville, TN, June 10-13, 1996.

70. Mian, A. K. M., Cordes, R. A., Lin, S. T., Suhling, J. C. and Jaeger, R. C., “Design, Calibration, and Application of Optimized (111) Silicon Stress Sensing Chips,” Proceedings of TECHCON ‘96, pp. 1-4, Phoenix, AZ, September 12-14, 1996.

71. Zou, Y., Lin, S. T., Suhling, J. C. And Jaeger, R. C., “Measurement of Die Stresses in Encapsulated Packages,” Proceedings of TECHCON ‘96, pp. 1-4, Phoenix, AZ, September 12-14, 1996.

72. Bradley, A. T., Ramani, R., Jaeger, R. C. and Suhling, J. C., “MOSFET Piezoresistive Stress Sensing on (100) Silicon,” Proceedings of TECHCON ‘96, pp. 1-4, Phoenix, AZ, September 12-14, 1996.

Exhibit 100200117

Exhibit 1002


73. Suhling, J. C., Lin, S. T., Moral, R. J., Johnson, R. W. and Jaeger, R. C., “Measurement of Die Stress in Advanced Electronic Packaging for Space and Terrestrial Applications,” Proceedings of STAIF-97, pp. 819-824, 1997 Space Technology and Applications International Forum, American Institute of Physics Conference Proceedings 387, Albuquerque, NM, January 26-30, 1997.

74. Hung, S. C. and Suhling, J. C., “Rate Dependent Pure Shear Behavior of Linerboard,” Proceedings of the 3rd International Symposium on Moisture and Creep Effects on Paper, Board, and Containers, pp. 69-84, Rotorua, New Zealand, February 20-21, 1997.

75. Evans, J. L., Newberry, R., Bosley, L., McNeal, S. G., Mawer, A., Johnson, R. W. and Suhling, J. C., “PBGA Reliability for Under-the-Hood Automotive Applications,” Proceedings of INTERpack ‘97, pp. 215-219, Kohala, HI, June 15-19, 1997.

76. Lin, S. T., Han, B., Suhling, J. C., Johnson, R. W. and Evans, J. L., “Finite Element and Moiré Interferometry Study of Chip Capacitor Reliability,” Proceedings of INTERpack ‘97, pp. 1687-1694, Kohala, HI, June 15-19, 1997.

77. Suhling, J. C., Jaeger, R. C., Lin, S. T., Mian, A. K. M., Cordes, R. A. and Wilamowski, B. M., “Design and Calibration of Optimized (111) Silicon Stress Sensing Test Chips,” Proceedings of INTERpack ‘97, pp. 1723-1729, Kohala, HI, June 15-19, 1997.

78. Suhling, J. C., Jaeger, R. C., Lin, S. T., Moral, R. J. and Zou, Y., “Measurement of the Complete Stress State in Plastic Encapsulated Packages,” Proceedings of INTERpack ‘97, pp. 1741-1750, Kohala, HI, June 15-19, 1997.

79. Liang, S. and Suhling, J. C., “Finite Element and Experimental Study on the Embossing of Low Basis Weight Papers,” Mechanics of Cellulosic Materials - 1997, ASME, AMD - Vol. 221, pp. 55-68, ASME/ASCE/SES Joint Mechanics Summer Meeting, Evanston, IL, June 29 - July 2, 1997.

80. Jaeger, R. C., Bradley, A. T., Suhling, J. C. and Zou, Y., “FET Mobility Degradation and Device Mismatch Due to Packaging Induced Die Stress,” Proceedings of the 23rd European Solid-State Circuits Conference, pp. 272-275, Southampton, England, September 16-18, 1997.

81. Jaeger, R. J. and Suhling, J. C., “Advances in Stress Test Chips,” Application of Experimental Mechanics to Electronic Packaging - 1997, ASME, EEP - Vol. 22, pp. 1-5, ASME International Mechanical Engineering Congress and Exposition, Dallas, TX, November 16-21, 1997.

82. Zou, Y., Suhling, J. C., Jaeger, R. C., Lin, S. T., Nguyen, L., and Gee, S., “Characterization of Plastic Packages Using (100) Silicon Stress Test Chips,” Application of Experimental Mechanics to Electronic Packaging - 1997, ASME, EEP - Vol. 22, pp. 15-21, ASME International Mechanical Engineering Congress and Exposition, Dallas, TX, November 16-21, 1997.

Exhibit 100200118

Exhibit 1002


83. Kang, Y., Mian, A. K. M., Suhling, J. C., and Jaeger, R. C., “Hydrostatic Response of Piezoresistive Stress Sensors,” in Application of Experimental Mechanics to Electronic Packaging - 1997, ASME, EEP - Vol. 22, pp. 29-36, ASME International Mechanical Engineering Congress and Exposition, Dallas, TX, November 16-21, 1997.

84. Mian, A. K. M., Suhling, J. C., Jaeger, R. C., and Wilamowski, B. M., “Evaluation of Die Stress Using van der Pauw Sensors,” Application of Experimental Mechanics to Electronic Packaging - 1997, ASME, EEP - Vol. 22, pp. 59-67, ASME International Mechanical Engineering Congress and Exposition, Dallas, TX, November 16-21, 1997.

85. Zou, Y., Suhling, J. C., Johnson, R. W. and Jaeger, R. C., “Complete Stress State Measurements in Chip on Board Packages,” Proceedings of the 1998 International Conference on Multichip Modules and High Density Packaging, pp. 425-435, Denver, CO, April 15-17, 1998.

86. Zou, Y., Suhling, J. C., Jaeger, R. C. and Ali, H., “Three-Dimensional Die Surface Stress Measurements in Delaminated and Non-Delaminated Plastic Packaging,” Proceedings of the 48th Electronic Components and Technology Conference, pp. 1223-1234, Seattle, WA, May 25-28, 1998.

87. Suhling, J. C., Jaeger, R. C., Bradley, A. T. and Mian, A. K. M., “FET and VDP Stress Sensors for Experimental Characterization of Die Stress in Electronic Packages,” Proceedings of the 1998 SEM Spring Conference on Experimental Mechanics, pp. 232-234, Houston, TX, June 1-3, 1998.

88. Lin, S. T., Benoit, J. T., Grzybowski, R. R., Zou, Y., Suhling, J. C. and Jaeger, R. C., “Evaluation of Die-Attachment Effects on Die Stresses Using Piezoresistive Sensors,” Proceedings of the 1998 SEM Spring Conference on Experimental Mechanics, pp. 235-236, Houston, TX, June 1-3, 1998.

89. Lin, S. T., Benoit, J. T., Grzybowski, R. R., Zou, Y., Suhling, J. C. and Jaeger, R. C., “High Temperature Die-Attach Effects on Die Stresses,” Proceedings of the 4th

International High Temperature Electronics Conference, pp. 1-8, Albuquerque, NM, June 14-19, 1998.

90. Suhling, J. C., Gilchrist, A. C., Suh, S. and Urbanik, T. J., “Nonlinear Finite Element Modeling of Corrugated Board,” Proceedings of the 1998 International Paper Physics Seminar, pp. 1-4, Vancouver, Canada, August 9-14, 1998.

91. Bradley, A. T., Jaeger, R. C., Suhling, J. C. and Zou, Y., “Die Stress Characterizations Using CMOS FET Sensors,” Proceedings of the 24th European Solid State Circuits Conference, pp. 1-4, Amsterdam, Netherlands, September 1998.

92. Zou, Y., Suhling, J. C. and Jaeger, R. C., “Complete Stress State Measurements in Plastic Packages Using (111) Silicon Stress Test Chips,” Proceedings of TECHCON ’98, pp. 1-4, Las Vegas, NV, September 9-11, 1998.

93. Mian, A. K. M., Suhling, J. C. and Jaeger, R. C., “Theoretical and Experimental Study on the Piezoresistive Behavior of Van Der Pauw Stress Sensors,” Proceedings of TECHCON ’98, pp. 1-4, Las Vegas, NV, September 9-11, 1998.

Exhibit 100200119

Exhibit 1002


94. Bradley, A. T., Suhling, J. C., Jaeger, R. C. and Zou, Y., “Die Stress Characterization Using Arrays of CMOS Sensors,” Proceedings of TECHCON ’98, pp. 1-4, Las Vegas, NV, September 9-11, 1998.

95. Zou, Y., Suhling, J. C., and Jaeger, R. C., Lin, S. T., Benoit, J. T., Grzybowski, R. R., “Die Stress Measurements Using High Temperature Die Attachment Materials,” Thermo-Mechanical Characterization of Evolving Packaging Materials and Structures, ASME, EEP - Vol. 24, pp. 107-117, ASME International Mechanical Engineering Congress and Exposition, Anaheim, CA, November 15-20, 1998.

96. Li, H. P. and Suhling, J. C., “Moisture Induced Deformations of Multilayer Papers and Corrugated Board,” Proceedings of the 4th International Symposium on Moisture and Creep Effects of Paper, Board, and Containers, pp. 57-81, Grenoble, France, March 18-19, 1999.

97. Zou, Y., Johnson, R. W., Suhling, J. C., Jaeger, R. C., Harris, J., Kromis, C., Ahmad, I., Tucker, D., Fathi, Z., “Comparison of Die Level Stresses in Chip-on-Board Packages Processed with Convection and Variable Frequency Microwave Encapsulant Curing,” Proceedings of the 1998 International Conference on Multichip Modules and High Density Packaging, pp. 77-86, Denver, CO, April 6-9, 1999.

98. Bradley, A. T., Jaeger, R. C., Suhling, J. C. and Zou, Y., “Test Chips for Die Characterization Using Arrays of CMOS Sensors, Proceedings of the 1999 IEEE Custom Integrated Circuits Conference, pp. 147-150, San Diego, CA, May 16-19, 1999.

99. Zou, Y., Lin, S. T., Suhling, J. C., and Jaeger, R. C., Lin, S. T., Benoit, J. T., Grzybowski, R. R., “Die Surface Stress Variation During Thermal Cycling and Thermal Aging Reliability Tests,” Proceedings of the 49th Electronic Components and Technology Conference, pp. 1249-1260, San Diego, CA, June 1-4, 1999.

100. Mian, A. K. M., Suhling, J. C. and Jaeger, R. C., “Theoretical and Experimental Analysis of VDP Sensors for Use in Silicon Die Stress Measurements,” Proceedings of the 1999 SEM Spring Conference on Experimental Mechanics, pp. 76-80, Cincinnati, OH, June 7-9, 1999.

101. Mian, A. K. M., Suhling, J. C. and Jaeger, R. C., "Sensitivity of van der Pauw Sensors to Uniaxial Stress," Advances in Electronic Packaging - 1999, Proceedings of InterPACK '99, ASME, EEP - Vol. 26-1, pp. 195-203, Lahaina, HI, June 13-19, 1999.

102. Jaeger, R. C., Suhling, J. C., Bradley, A. T. and Xu, J., "Silicon Piezoresistive Stress Sensors Using MOS and Bipolar Transistors," Advances in Electronic Packaging - 1999, Proceedings of InterPACK '99, ASME, EEP - Vol. 26-1, pp. 219-226, Lahaina, HI, June 13-19, 1999.

103. Gilchrist, A. C., Suhling, J. C. and Urbanik, T. J., “Nonlinear Finite Element Modeling of Corrugated Board,” Mechanics of Cellulosic Materials - 1999, ASME, AMD - Vol. 231, pp. 101-106, ASME Mechanics and Materials Conference, Blacksburg, VA, June 27-30, 1999.

Exhibit 100200120

Exhibit 1002


104. Suhling, J. C., Johnson, R. W., Mian, A. K. M., Rahim, M. K., Zou, Y., Ragam, S., Palmer, M., Ellis, C. D. and Jaeger, R. C., "Measurement of Backside Flip Chip Die Stresses Using Piezoresistive Test Die," Proceedings of IMAPS '99, pp. 298-303, Chicago, IL, October 26-28, 1999.

105. Suhling, J. C., Zou, Y., Johnson, R. W., Jaeger, R. C., Mian, A. K. M., Rahim, M. K. and Ragam, S., “Stress Measurements in Flip Chip on Board Assemblies Using Piezoresistive Test Chips,” Proceedings of NEPCON West 2000, pp. 661-672, Anaheim, CA, February 27 - March 2, 2000.

106. Mian, A. K. M., Suhling, J. C., and Jaeger, R. C., “Sensitivity of (100) Silicon VDP Sensors to Uniaxial And Hydrostatic Loads,” Proceedings of SECTAM XX (CD ROM), Paper SM-127, pp. 1-9, Pine Mountain, GA, April 17-18, 2000.

107. Suhling, J. C., Zou, Y., Johnson, R. W., Jaeger, R. C., Mian, A. K. M., Rahim, M. K. and Ragam, S., “Measurement of Die Stresses in Flip Chip on Laminate Assemblies,” Proceedings of the 9th International Congress on Experimental Mechanics, pp.609-615, Orlando, FL, June 5-8, 2000.

108. Islam, N., Suhling, J. C., Johnson, R. W., Evans, J. L., Thompson, J. R., “Reliability Of Small BGAs in the Automotive Environment,” Proceedings of the 9th

International Congress on Experimental Mechanics, pp. 735-737, Orlando, FL, June 5-8, 2000.

109. Mian, A. K. M., Suhling, J. C., and Jaeger, R. C., “Stress Measurements Using van der Pauw Structures,” Proceedings of the 9th International Congress on Experimental Mechanics, pp. 813-821, Orlando, FL, June 5-8, 2000.

110. Suhling, J. C., and Jaeger, R. C., “Silicon Piezoresistive Stress Sensors and Their Application in Electronic Packaging,” Proceedings of the Festschrift to Honor Professor Millard W. Johnson, pp. 1-38, Madison, WI, September 8-9, 2000.

111. Rahim, M. K., Suhling, J. C., Jaeger, R. C., Bright, W., and Evans, T., “CSP Test Chip Measurements,” Proceedings of the 2001 SEM Spring Conference on Experimental Mechanics, pp. 798-803, Portland, OR, June 4-6, 2001.

112. Xu. J., Jaeger, R. C., and Suhling J. C., “CMOS Stress Sensors on (111) Silicon,” Proceedings of InterPACK '01, ASME, Paper IPACK2001-15617, pp. 1-10, Kauai, HI, July 8-13, 2001.

113. Evans, J. L., Thompson, J. R., Seto, P., McAnally, C., Johnson, R. W., Suhling, J. C., and Liu, J., “Small PBGA Reliability Considerations for Under-hood Automotive Electronics,” Proceedings of the 2001 SMTA International, Paper 042, pp. 1-7, Chicago, IL, September 30 - October 4, 2001.

114. Zou, Y., Suhling, J. C., and Jaeger, R. C., “Piezoresistive Sensors for MEMS Packaging Stress Measurements,” Proceedings of 2002 SEM Conference on Experimental Mechanics, Paper 311, pp. 311-323, Milwaukee, WI, June 10-12, 2002.

115. Islam, S., Xu, B., Suhling, J. C., Johnson, R. W., “Experimental Measurements of the Mechanical Properties of Underfill Encapsulants,” Proceedings of 2002 SEM Conference on Experimental Mechanics, Paper 289, pp. 289-292, Milwaukee, WI, June 10-12, 2002.

Exhibit 100200121

Exhibit 1002


116. Rahim, M. K., Suhling, J. C., Johnson, R. W., and Jaeger, R. C., “Characterization of Die Stress in Flip Chip on Laminate Assemblies,” Proceedings of the IMAPS Workshop on Flip Chip Technology, Austin, TX, June 24-26, 2002.

117. Suhling, J. C., Johnson, R. W., Evans, J. L., Islam, N., Liu, J., Gale, H. S., and Thompson, J. R., “Reliability of Small Ball Grid Arrays in the Automotive Environment,” Proceedings of IMAPS 2002 International Symposium on Microelectronics, pp. 524-532, Denver, CO, September 4-6, 2002.

118. Evans, J. L., Johnson, R. W., Suhling, J. C., Thompson, J. R., and Seto, P., “Reliability of Next Generation Components and Substrates for Under-The-Hood Automotive Electronics,” Proceedings of the 2002 SMTA International, Paper S19P02, pp. 1-7, Chicago, IL, September 22-26, 2002.

119. Suhling, J. C., Johnson, R. W., Evans, J. L., Knight, R. W., Islam, N., Liu, J., Gale, H. S., Elkady, Y., and Thompson, J. R., "Use of Underfill to Enhance the Thermal Cycling Reliability of Small BGAs," Proceedings of APEX 2003, Paper S03-3, pp. 1-10, Anaheim, CA, March 31-April 2, 2003.

120. Tian, G., Liu, Y., Lall, P., Johnson, R. W., Abderrahman, S., Palmer, M., Islam, N., Suhling, J., and Crane, L., “Corner Bonding of CSPs: Processing and Reliability,” Proceedings of the APEX 2003, Paper S02-1, pp. 1-8, Anaheim, CA, March 31- April 2, 2003.

121. Suhling, J. C., “Harsh Environment Challenges for Automotive Electronics,” Proceedings of the NASA/JPL Workshop on Extreme Environment Electronics, pp. 1-50, Pasadena, CA, May 14-16, 2003.

122. Lall, P., Islam, N, Suhling, J., Darveaux, R., “Model for BGA and CSP Reliability in Automotive Underhood Environments,” Proceedings of the 53rd Electronic Components and Technology Conference, pp. 189-196, New Orleans, LA, May 27-30, 2003.

123. Rahim, M. K., Suhling, J. C., Copeland, S., Jaeger, R. C., Lall, P., and Johnson, R. W., “Characterization of Die Stresses in Flip Chip on Laminate Assemblies Using (111) Silicon Stress Test Chips,” Proceedings of the 53rd Electronic Components and Technology Conference, pp. 905-919, New Orleans, LA, May 27-30, 2003.

124. Islam, M. S., Suhling, J. C., Lall, P., Xu, B., and Johnson, R. W., “Measurement and Modeling of the Temperature Dependent Material Behavior of Underfill Encapsulants,” Proceedings of the 53rd Electronic Components and Technology Conference, pp. 1636-1643, New Orleans, LA, May 27-30, 2003.

125. Rahim, M. K., Suhling, J. C., Copeland, S., Jaeger, R. C., and Lall, P., “Stress and Delamination Measurements in Flip Chip on Laminate Assemblies,” Proceedings of the 2003 SEM Annual Conference, Paper 342, pp. 1-14, Charlotte, NC, June 2-4, 2003.

126. Islam, S., Suhling, J. C., and Lall, P., “Measurement of Underfill to Soldermask Adhesion Strength,” Proceedings of the 2003 SEM Annual Conference, Paper 328, pp. 1-6, Charlotte, NC, June 2-4, 2003.

Exhibit 100200122

Exhibit 1002


127. Suhling, J. C., Islam, M. S., Lall, P., Xu, B., and Johnson, R. W., “Accurate Measurement of the Material Behavior Of Underfill Encapsulants,” Proceedings of the 2003 IMAPS Workshop on Flip Chip Technology, pp. 1-8, Austin, TX, June 16-18, 2003.

128. Lall, P., Islam, N, Suhling, J., and Darveaux, R., “BGA Reliability in Automotive Underhood Applications,” Proceedings of InterPACK ‘03, Paper 35243, pp. 1-8, Lahaina, HI, July 6-11, 2003.

129. Jaeger, R. C., Suhling, J. C., Chen, Y., Rahaman, S., and Islam, M. N., “A Chip-On-Beam Calibration Technique For Piezoresistive Stress Sensor Die,” Proceedings of InterPACK ‘03, Paper 35276, pp. 1-8, Lahaina, HI, July 6-11, 2003.

130. Tian, G., Liu, Y., Lall, P., Johnson, R. W., Abderrahman, S., Palmer, M., Islam, N., Suhling, J., and Crane, L., “Drop Reliability of Corner Bonded CSP in Portable Products,” Proceedings of InterPACK ‘03, Paper 35318, pp. 1-9, Lahaina, HI, July 6-11, 2003.

131. Rahim, M. K., Suhling, J. C., Copeland, S., Jaeger, R. C., and Lall, P., “Measurement of Stress and Delamination in Flip Chip on Laminate Assemblies,” Proceedings of InterPACK ‘03, Paper 35319, pp. 1-15, Lahaina, HI, July 6-11, 2003.

132. Islam, M. S., Suhling, J. C., and Lall, P., “Measurement of the Constitutive Behavior of Underfill Encapsulants,” Proceedings of InterPACK ‘03, Paper 35321, pp. 1-9, Lahaina, HI, July 6-11, 2003.

133. Johnson, R. W., Suhling, J. C., Evans, J. L., and Lall, P., “Electronic Packaging Reliability for Automotive and Non-Automotive Electronic Modules,” Proceedings of the SMTA/CAVE Workshop on Harsh Environment Electronics, pp. 1-35, Dearborn, MI, June 24-25, 2003.

134. Tian, G., Gale, S., Islam, S., Xu, B., Suhling, J., Ghosh, K., McCabe. M., Gilbert, K., and Tirpak, R., “Studies of the Thermo-Mechanical Properties and Reliability of Flip Chip Underfill Encapsulants for Applications in High Temperature Environments,” Proceedings of the SMTA/CAVE Workshop on Harsh Environment Electronics, pp. 1-34, Dearborn, MI, June 24-25, 2003.

135. Lall, P., Islam, N, Suhling, J., and Darveaux, R., “Damage Relationships For BGA And CSP Reliability in Automotive Underhood Applications,” Proceedings of the 2003 SMTA International, pp. 318-325, Chicago, IL, September 21-35, 2003.

136. Islam, M. N., Suhling, J. C., Lall, P., Shete, T., Gale, H. S., Johnson, R. W., Bozack, M. J., Seto, P., Gupta, T., and Thompson, J. R., “Thermal Cycling Reliability of Chip Resistor Lead Free Solder Joints,” Proceedings of the 2003 ASME International Mechanical Engineering Congress and Exposition, Volume 2, Paper IMECE2003-42117, pp. 1-4, Washington, DC, November 15-21, 2003.

137. Guoyun Tian, G., Liu, Y., Lall, P., Johnson, R. W., Abderrahman, S., Palmer, M., Islam, N., Panchagade, D., Suhling, J., and Crane, L., “Drop-Impact Reliability of Chip-Scale Packages in Handheld Products,” Proceedings of the 2003 ASME International Mechanical Engineering Congress and Exposition, Volume 2, Paper IMECE2003-42075, pp. 1-9, Washington, DC, November 15-21, 2003.

Exhibit 100200123

Exhibit 1002


138. Lall, P., Islam, N, Suhling, J., and Darveaux, R., “Damage Relationships For BGA Reliability In Harsh Environments,” Proceedings of the 2003 ASME International Mechanical Engineering Congress and Exposition, Volume 2, Paper IMECE2003-42077, pp. 1-8, Washington, DC, November 15-21, 2003.

139. Islam, M. S., Suhling, J. C., Lall, P., and Johnson, R. W., “Impact Of Environmental Preconditioning And Composition Parameters On Constitutive Behavior Of Underfills,” Proceedings of the 2003 ASME International Mechanical Engineering Congress and Exposition, Volume 2, Paper IMECE2003-42083, pp. 1-14, Washington, DC, November 15-21, 2003.

140. Lall, P., Islam, N., Rahim, K., Suhling, J., and Gale, S., “Leading Indicators-of-Failure for Prognosis of Electronic and MEMS Packaging,” Proceedings of the 54th Electronic Components and Technology Conference, pp. 1570-1578, Las Vegas, NV, June 1-4, 2004.

141. Lall, P., Islam, N., Shete, T., Evans, J., Suhling, J., and Gale, S., “Damage Mechanics of Electronics on Metal-Backed Substrates in Harsh Environments,” Proceedings of the 54th Electronic Components and Technology Conference, pp. 704-711, Las Vegas, NV, June 1-4, 2004.

142. Lall, P., Panchagade, D., Liu, Y., Johnson, R. W., and Suhling, J. C., “Models for Reliability Prediction of Fine-Pitch BGAs and CSPs in Shock and Drop-Impact,” Proceedings of the 54th Electronic Components and Technology Conference, pp. 1296-1303, Las Vegas, NV, June 1-4, 2004.

143. Lall, P., Singh, N., Suhling, J. C., Strickland, M., and Blanche, J., “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” Proceedings of ITHERM 2004, pp. 259-267, Las Vegas, NV, June 1-4, 2004.

144. Rahim, M. K., Suhling, J. C., Copeland, D. S., Islam, M. S., Jaeger, R. C., Lall, P., Johnson, R. W., “Measurement of Thermally Induced Die Stresses in Flip Chip on Laminate Assemblies,” Proceedings of ITHERM 2004, pp. 219-230, Las Vegas, NV, June 1-4, 2004.

145. Suhling, J. C., Gale, H. S., Johnson, R. W., Islam, M. N., Shete, T., Lall, P., Bozack, M. J., Evans, J. L., Seto, P., Gupta, T., and Thompson, J. R., “Thermal Cycling Reliability of Lead Free Solders for Automotive Applications,” Proceedings of ITHERM 2004, pp. 350-357, Las Vegas, NV, June 1-4, 2004.

146. Islam, M. S., Suhling, J. C., and Lall, P., “Measurement of the Temperature Dependent Constitutive Behavior of Underfill Encapsulants,” Proceedings of ITHERM 2004, pp. 145-152, Las Vegas, NV, June 1-4, 2004.

147. Elkady, Y. A., Knight, R. W., Suhling, J. C., and Lall, P., “Thermal Performance of Underfilled BGAs,” Proceedings of ITHERM 2004, pp. 624-634, Las Vegas, NV, June 1-4, 2004.

148. Abdel-Hady, H., Ma, H., Suhling, J. C., Islam, M. S., Lall, P., “Measurement of the Constitutive Behavior of Lead Free Solders,” Proceedings of the 10th International Congress on Experimental Mechanics, Paper #345, pp. 1-5, Costa Mesa, CA, June 7-10, 2004.

Exhibit 100200124

Exhibit 1002


149. Suhling, J. C., Gale, H. S., Johnson, R. W., Islam, M. N., Shete, T., Lall, P., Bozack, M. J., Evans, J. L., Seto, P., Gupta, T., and Thompson, J. R., “Thermal Cycling Reliability of Chip Resistor Lead Free Solder Joints,” Proceedings of the 10th International Congress on Experimental Mechanics, Paper #346, pp. 1-8, Costa Mesa, CA, June 7-10, 2004.

150. Lall, P., Islam, N., Shete, T., Gale, S., and Suhling, J., “Reliability of Harsh Environment Electronics Assembled on Damage Metal-Backed Printed Circuit Boards,” Proceedings of SECTAM XXII, pp. 1-10, Tuskegee, AL, August 15-17, 2004.

151. Rahim, M. K., Suhling, J. C., Jaeger, R. C., and Lall, P., “Flip Chip Die Stress Characterization,” Proceedings of SECTAM XXII, pp. 1-13, Tuskegee, AL, August 15-17, 2004.

152. Lall, P., Singh, N., Suhling, J., Strickland, M., Blanche, J., “Design Guidelines for Deployment of Area Array Packages in Harsh Environments,” Proceedings of SECTAM XXII, pp. 1-9, Tuskegee, AL, August 15-17, 2004.

153. Lall, P., Panchagade, D., Liu, Y., Johnson, W., and Suhling, J., “Drop-Induced Failure Prediction Model for Fine-Pitch BGAs and CSPs,” Proceedings of SECTAM XXII, pp. 1-10, Tuskegee, AL, August 15-17, 2004.

154. Lall, P., Islam, N., Rahim, K., and Suhling, J., “Methodology for Prognostication of Electronics and MEMS Packaging,” Proceedings of the 2004 SMTA International, pp. 17-26, Chicago, IL, September 26-30, 2004.

155. Lall, P., Islam, N., Shete, T., Evans, J., Suhling, J., Gale, S., “Models for Solder-Joint Reliability of Components on Metal-Backed Printed Circuit Boards,” Proceedings of the 2004 SMTA International, pp. 411-420, Chicago, IL, September 26-30, 2004.

156. Lall, P., Panchagade, D., Liu, Y., Johnson, R. W., and Suhling, J. C., “Shock-Induced Failure Prediction Model for Fine-Pitch BGAs and CSPs,” Proceedings of the 2004 SMTA International, pp. 472-481, Chicago, IL, September 26-30, 2004.

157. Rickett, B., Elmgren, P., Flowers, G., Gale, S., and Suhling, J., “Potential for Whisker Formation in Lead-Free Electroplated Connector Finishes,” Proceedings of the 2004 SMTA International, pp. 707-716, Chicago, IL, September 26-30, 2004.

158. Rahim, M. K., Suhling, J. C., Copeland, D. S., Islam, M. S., Jaeger, R. C., Lall, P., Johnson, R. W., “Die Stress Characterization in Copper/Low-K Flip-Chip Assemblies,” Proceedings of the 2004 IMAPS International Symposium on Microelectronics, pp. 1-13, Long Beach, CA, Nov 14-18, 2004.

159. Lall, P., Panchagade, D., Liu, Y., Johnson, R. W., and Suhling, J. C., “Models for Reliability of Fine-Pitch BGAs and CSPs in Shock and Drop Impact,” Proceedings of the 2004 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2004-62317, pp. 1-9, Anaheim, CA, November 13-19, 2004.

Exhibit 100200125

Exhibit 1002


160. Lall, P., Islam, N., Rahim, K., Suhling, J., “Prognosis Methodologies for Health Management of Electronics and MEMS Packaging,” Proceedings of the 2004 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2004-62319, pp. 1-10, Anaheim, CA, November 13-19, 2004.

161. Lall, P., Islam, N., Shete, T., Evans, J., Suhling, J., Gale, S., “Reliability of BGA and CSP on Metal-Backed Printed Circuit Boards in Harsh Environments,” Proceedings of the 2004 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2004-62320, pp. 1-9, Anaheim, CA, November 13-19, 2004.

162. Suhling, J. C., Jaeger, R. C., Rahim, M. K., Islam, M. S., Ma, H., Lin, C., and Lall, P., “Packaging Stress Characterization at Low Temperatures,” Proceedings of the IMAPS Advanced Technology Workshop on Reliability of Advanced Electronic Packages and Devices in Extreme Cold Environments, pp. 1-9, Pasadena, CA, February 21-25, 2005.

163. Copeland, D. S., Rahim, M. K., Suhling J. C., Jaeger, R. C., Lall, P., Tian, G., and Vasoya, K., “Material Characterization and Die Stress Measurement of Low Expansion PCB for Extreme Environments,” Proceedings of the 2005 IEEE Aerospace Conference, pp. 1-19, Big Sky, MT, March 5-12, 2005.

164. Lall, P., Panchagade, D., Choudhary, P., Suhling, J., Gupte, S., “Failure-Envelope Approach to Modeling Shock and Vibration Survivability of Electronic and MEMS Packaging,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, pp. 1-10, Orlando, FL, June 1-3, 2005.

165. Lall, P., Singh, N., Strickland, M., Blanche, J., Suhling, J., “Decision-Support Models for Thermo-Mechanical Reliability of Leadfree Flip-Chip Electronics in Extreme Environments,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, pp. 127-136, Orlando, FL, June 1-3, 2005.

166. Lall, P., Islam, S., Suhling, J., Tian, G., “Nano-Underfills for High-Reliability Applications in Extreme Environments,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, pp. 212-222, Orlando, FL, June 1-3, 2005.

167. Lall, P., Islam, N., Suhling, J., “Prognostication and Health Monitoring of Leaded and Lead Free Electronic and MEMS Packages in Harsh Environments,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, pp. 1305-1313, Orlando, FL, June 1-3, 2005.

168. Copeland, D. S., Rahim, M. K., Suhling J. C., Tian, G., Lall, P., Jaeger, R. C., and Vasoya, K., “Ultra-High Reliability Flip Chip on Laminate For Harsh Environments,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, pp. 362-375, Orlando, FL, June 1-3, 2005.

169. Rahim, M. K., Suhling, J. C., Jaeger, R. C., and Lall, P., “Fundamentals of Delamination Initiation and Growth in Flip Chip Assemblies,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, pp. 1172-1186, Orlando, FL, June 1-3, 2005.

Exhibit 100200126

Exhibit 1002


170. Lall, P., Islam, N., and Suhling, J., “Prognostic Indicators for Leaded and Lead-Free Electronic Packages in Harsh Environments,” Proceedings of the 2005 SEM Spring Conference on Experimental Mechanics, Paper No. 237, pp. 1-13, Portland, OR, June 7-9, 2005.

171. Lall, P., Islam, S., Suhling, J., Tian, G., “Models for Mechanical Behavior of Nano-Underfills in High Reliability Applications,” Proceedings of the 2005 SEM Spring Conference on Experimental Mechanics, Paper No. 337, pp. 1-13, Portland, OR, June 7-9, 2005.

172. Rahim, M. K., Islam, M. S., Ma, H., Lin, C., Suhling, J. C., Jaeger, R. C., and Lall, P., “Electronic Packaging Stress Characterization at Low Temperatures,” Proceedings of the 2005 SEM Spring Conference on Experimental Mechanics, Paper No. 309, pp. 1-8, Portland, OR, June 7-9, 2005.

173. Lall, P., Islam, N., Choudhary, P., Rahim, K., and Suhling, J., “Life-Cycle Management of Automotive Electronic Systems,” Proceedings of the SMTA Harsh Environment Electronics Workshop, pp. 1-35, Indianapolis, IN, June 28-29, 2005.

174. Lall, P., Islam, N., and Suhling, J., “Leading Indicators of Failure for Prognostication of Leaded and Lead-Free Electronics in Harsh Environments,” Proceedings of InterPACK ’05, Paper IPACK2005-73426, pp. 1-9, San Francisco, CA, July 17-22, 2005.

175. Lall, P., Panchagade, D., Choudhary, P., Suhling, J., Gupte, S., “Models for Shock and Vibration Survivability of Electronic and MEMS Packaging,” Proceedings of InterPACK ’05, Paper IPACK2005-73427, pp. 1-12, San Francisco, CA, July 17-22, 2005.

176. Rahim, M. K., Suhling, J. C., Jaeger, R. C., and Lall, P., “Evolution of Die Stress and Delamination During Thermal Cycling of Flip Chip Assemblies,” Proceedings of InterPACK ’05, Paper IPACK2005-73348, pp. 1-16, San Francisco, CA, July 17-22, 2005.

177. Rahim, M. K., Islam, M. S., Ma, H., Lin, C., Suhling, J. C., Jaeger, R. C., Lall, P., Knight, R. W., Strickland, M., and Blanche, J., “Measurement of Electronic Packaging Material Behavior and Flip Chip Die Stresses at Extreme Low Temperatures,” Proceedings of InterPACK ’05, Paper IPACK2005-73349, pp. 1-10, San Francisco, CA, July 17-22, 2005.

178. Lall, P., Singh, N., Hariharan, G., Strickland, M., Blanche, J., and Suhling, J., “Models for Thermo-Mechanical Reliability Trade-offs for Leaded and Lead-Free Flip-Chip Electronics in Extreme Environments,” Proceedings of the 2005 SMTA International, pp. 500-511, Chicago, IL, September 25-29, 2005.

179. Suhling, J. C., Jaeger, R. C., and Lall, P., “Evaluation of Packaging Reliability Using Stress Test Chips,” Proceedings of the 2005 International Electronic Packaging Symposium, pp. 1-64, GE Global Research Center, Niskayuna, NY, October 18-19, 2005.

Exhibit 100200127

Exhibit 1002


180. Suhling, J. C., Rahim, M. K., Jaeger, R. C., and Lall, P., “Evolution of Die Stress and Delamination During Thermal Cycling of Flip Chip Assemblies,” Proceedings of the IMAPS Garden State Fall Packaging Symposium, pp. 1-46, IBM Research, Hawthorne, NY, November 2, 2005.

181. Lall, P., Islam, N., and Suhling, J., “Methodologies for Prognostication and Health Monitoring of Leaded and Lead-Free Electronics and MEMS Packages in Harsh Environments,” Proceedings of the 2005 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2005-82614, pp. 1-9, Orlando, FL, November 5-11, 2005.

182. Lall, P., Panchagade, D., Choudhary, P., Suhling, J., and Gupte, S., “Shock and Vibration Survivability Prediction using Failure Envelopes for Electronic and MEMS Packaging,” Proceedings of the 2005 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2005-82612, pp, 1-12, Orlando, FL, November 5-11, 2005.

183. Copeland, D. S., Rahim, M. K., Suhling J. C., Tian, G., Lall, P., Jaeger, R. C., and Vasoya, K., “High Reliability Flip Chip Using Low CTE Laminate Substrates,” Proceedings of the 2005 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2005-82662, pp. 1-14, Orlando, FL, November 5-11, 2005.

184. Ma, H., Suhling, J. C., Lall, P., and Bozack, M. J., “Effects of Physical Aging on the Mechanical Behavior of SAC405 Lead Free Solder,” Proceedings of the IEEE International Symposium on Advanced Packaging Materials, pp. 1-14, Atlanta, GA, March 15-17, 2006.

185. Mian, A., Suhling, J. C., and Jaeger, R. C., “A High Sensitive Piezoresistive Sensor for Stress Measurements in Packaged Semiconductor Die,” Proceedings of WMED ’06, pp. 19-20, Boise, ID, April 14, 2006.

186. Lall, P., Gupte, S., Choudhary, P., and Suhling, J., “Solder-Joint Reliability in Electronics Under Shock and Vibration Using Explicit Finite Element Submodeling,” Proceedings of the 56th IEEE Electronic Components and Technology Conference, pp. 428-435, San Diego, CA, May 30-June 2, 2006.

187. Lall, P., Choudhary, P., Gupte, S., and Suhling, J., “Health Monitoring for Damage Initiation and Progression During Mechanical Shock in Electronic Assemblies,” Proceedings of the 56th IEEE Electronic Components and Technology Conference, pp. 85-94, San Diego, CA, May 30-June 2, 2006.

188. Lall, P., Hande, M., Singh, N., Suhling, J., and Lee, J., “Feature Extraction and Damage Data for Prognostication of Leaded and Leadfree Electronics,” Proceedings of the 56th IEEE Electronic Components and Technology Conference, pp. 718-727, San Diego, CA, May 30-June 2, 2006.

189. Ma, H., Suhling, J. C., Lall, P., and Bozack, M. J., “Reliability of the Aging Lead Free Solder Joint,” Proceedings of the 56th IEEE Electronic Components and Technology Conference, pp. 849-864, San Diego, CA, May 30-June 2, 2006.

Exhibit 100200128

Exhibit 1002


190. Lall, P., Panchagade, D., Iyengar, D., and Suhling, J., “Life Prediction and Damage Equivalency for Shock Survivability of Electronic Components,” Proceedings of ITherm 2006, pp. 804-116, San Diego, CA, May 30-June 2, 2006.

191. Lin, C., Islam, S., Suhling, J. C., Lall, P., “Material Behavior Changes in Underfill Encapsulants Exposed to Isothermal Aging,” Proceedings of ITherm 2006, pp. 1137-1146, San Diego, CA, May 30-June 2, 2006.

192. Lall, P., Islam, S., Suhling, J., and Tian, G., “Temperature and Time Dependent Prediction and Validation for Nano-Underfills Using RSA based RVE Algorithms,” Proceedings of ITherm 2006, pp. 906-920, San Diego, CA, May 30-June 2, 2006.

193. Rahim, M. K., Suhling, J. C., Jaeger, R. C., Lall, P., Knight, R., Strickland, M., and Blanche, J., “Reliability of Flip Chip Assemblies Subjected to Extreme Low Temperatures,” Proceedings of ITherm 2006, pp. 1379-1389, San Diego, CA, May 30-June 2, 2006.

194. Copeland, D. S., Rahim, M. K., Suhling, J. C., Jaeger, R. C., Lall, P., Vasoya, K., “Reliability and Die Stress Measurements in Flip Chip Assemblies with Carbon Fiber Core Laminate Substrates,” Proceedings of ITherm 2006, pp. 997-1010, San Diego, CA, May 30-June 2, 2006.

195. Knight, R., Elkady, Y., Suhling, J. C., Lall, P., “Degradation of Thermal Performance of Ball Grid Arrays after Thermal Cycling,” Proceedings of ITherm 2006, pp. 833-841, San Diego, CA, May 30-June 2, 2006.

196. Ma, H., Suhling, J. C., Lall, P., Bozack, M. J., Effects of Aging on the Stress-Strain and Creep Behaviors of Lead Free Solders, Proceedings of ITherm 2006, pp. 961-976, San Diego, CA, May 30-June 2, 2006.

197. Cho, C., Jaeger, R. C., and Suhling, J. C., “Experimental Characterization of the Temperature Dependence of the Piezoresistive Coefficients of Silicon,” Proceedings of ITherm 2006, pp. 928-935, San Diego, CA, May 30-June 2, 2006.

198. Lall, P., Hande, M., Singh, N., Suhling, J., and Lee, J., “Sensor Data-Fusion for Prognostication of Extreme Environment Electronics,” Proceedings of the 2006 SEM Annual Conference, Paper No. 390, pp. 1-13, St. Louis, MO, June 4-9, 2006.

199. Suhling, J.C., Lall, P., Ma, H., Lin, C., Physical Aging Effects in Solders and Underfill Encapsulants, Proceedings of the 2006 SEM Annual Conference, Paper No. 391, pp. 1-13, St. Louis, MO, June 4-9, 2006.

200. Lall, P., Choudhary, P., Gupte, S., and Suhling, J., “Shock-Reliability Prediction Models for Harsh-Environment Electronics,” Proceedings of the 2006 SMTA Harsh Environment Electronics Workshop, pp. 1-14, Indianapolis, IN, July 19-20, 2006.

201. Ma, H., Suhling, J. C., Lall, P., and Bozack, M., Thermal Aging Effects in Lead Free Solder Joints, Proceedings of the 2006 SMTA Harsh Environment Electronics Workshop, pp. 1-22, Indianapolis, IN, July 19-20, 2006.

202. Lall, P., Choudhary, P., Gupte, S., and Suhling, J., “Feature Extraction for Prognostication of Electronics under Shock and Vibration Loads,” Proceedings of the International Military and Aerospace Avionics COTS Conference, pp. 1-31, Santa Clara, CA, August 22-24, 2006.

Exhibit 100200129

Exhibit 1002


203. Lall, P., Hariharan, G., Strickland, M., Blanche, J., and Suhling, J., “Risk Assessment and Decision Support Models for Flip-Chip Electronics in Extreme Environments,” Proceedings of the International Military and Aerospace Avionics COTS Conference, pp. 1-32, Santa Clara, CA, August 22-24, 2006.

204. Chen, Y., Jaeger, R. C., and Suhling, J. C., “Multiplexed CMOS Sensor Arrays for Die Stress Mapping,” Proceedings of the 2006 European Solid-State Circuits Conference (ESSCIRC 2006), pp. 424-427, Montreux, Switzerland, September 19-21, 2006.

205. Lall, P., Panchagade, D., Iyengar, D., and Suhling, J., “Drop-Impact Reliability Prediction Models for Shock-Tolerant Design of Electronic Assemblies,” Proceedings of the 2006 SMTA International, pp. 361-375, Chicago, IL, September 24-28, 2006.

206. Tian, G., Lin, C., Suhling, J. C., Johnson, R. W., Lall, P., and Ghosh, K., “The Effects of Cure Profile Upon the Properties and Thermo-Mechanical Reliability of Flip Chip Underfills,” Proceedings of the 2006 SMTA International, pp. 515-523, Chicago, IL, September 24-28, 2006.

207. Lin, C., Tian, G., Suhling, J. C., Johnson, R. W., and Lall, P., "Effects of Environmental Exposures on Underfill Material Behavior, Proceedings of IMAPS 2006, pp. 76-87, San Diego, CA, October 8-12, 2006.

208. Lall, P., Hariharan, G., Strickland, M., Blanche, J., and Suhling, J., “Risk Management Models for Flip-Chip Electronics in Extreme Environment,” Proceedings of the 2006 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2006-15443, pp. 1-13, Chicago, IL, November 5-10, 2006.

209. Lall, P., Hariharan, G., Strickland, M., Blanche, J., Suhling, J., “Condition-Based Assessment of Damage Progression During Mechanical Shock in Electronic Assemblies,” Proceedings of the 2006 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2006-15450, pp. 1-10, Chicago, IL, November 5-10, 2006.

210. Ma, H., Suhling, J. C., Lall, P., “Evolution of Lead Free Solder Material Behavior During Elevated Temperature Aging,” Proceedings of the 2006 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2006-15491, pp. 1-10, Chicago, IL, November 5-10, 2006.

211. Suhling, J. C., Ma, H., Zhang, Y., Lall, P., and Bozack, M. J., “Effects of Thermal Aging on The Reliability Of Lead Free Solder Joints,” Proceedings of the IMAPS Workshop on Automotive Microelectronics and Packaging, pp. 1-6, Dearborn, MI, April 2007.

212. Lall, P., Hariharan, G., Shirgaokar, A., Suhling, J., Strickland, M., and Blanche, J., “Statistical Models for Area-Array Component Selection, Component Obsolescence, and Design Tradeoffs,” Proceedings of the IMAPS Workshop on Automotive Microelectronics and Packaging, pp. 1-36, Dearborn, MI, April 2007.

Exhibit 100200130

Exhibit 1002


213. Lall, P., Gupte, S., Choudhary, P., Suhling, J., and Darveaux, R., “Cohesive-Zone Explicit Sub-Modeling for Shock Life-Prediction in Electronics,” Proceedings of the 57th IEEE Electronic Components and Technology Conference, pp. 515-527, Reno, NV, May 29-June 1, 2007.

214. Ma, H., Suhling, J. C., Zhang, Y., Lall, P., and Bozack, M. J., “The Influence of Elevated Temperature Aging on Reliability of Lead Free Solder Joints,” Proceedings of the 57th IEEE Electronic Components and Technology Conference, pp. 653-668, Reno, NV, May 29-June 1, 2007.

215. Lall, P., Panchagade, D. Iyengar, D., Shantaram, S., Suhling, J., and Schrier, H., “High Speed Digital Image Correlation for Transient-Shock Reliability of Electronics,” Proceedings of the 57th IEEE Electronic Components and Technology Conference, pp. 924-939, Reno, NV, May 29-June 1, 2007.

216. Lall, P., Hande, M., Bhat, C., Suhling, J., and Lee, J., “Prognostics Health Monitoring for Prior-Damage Assessment in Electronics Equipment under Thermo-Mechanical Loads,” Proceedings of the 57th IEEE Electronic Components and Technology Conference, pp. 1097-1111, Reno, NV, May 29-June 1, 2007.

217. Lall, P., Choudhary, P., Gupte, S., Suhling, J., and Hofmeister, J., “Statistical Pattern Recognition and Built-in Reliability Test for Feature Extraction and Health Monitoring of Electronics under Shock Loads,” Proceedings of the 57th IEEE Electronic Components and Technology Conference, pp. 1161-1178, Reno, NV, May 29-June 1, 2007.

218. Rahim, M. K., Roberts, J. A., Suhling, J. C., Jaeger, R. C., and Lall, P., “Continuous In-Situ Die Stress Measurements During Thermal Cycling Accelerated Life Testing,” Proceedings of the 57th IEEE Electronic Components and Technology Conference, pp. 1478-1489, Reno, NV, May 29-June 1, 2007.

219. Rahim, M. K., Roberts, J. A., Suhling, J. C., Jaeger, R. C., and Lall, P., “Measurement of Die Stresses During Thermal Cycling,” Proceedings of the 2007 SEM Annual Conference, Paper No. 388, pp. 1-12, Springfield, MA, June 3-6, 2007.

220. Lall, P., Panchagade, D. Iyengar, D., Shantaram, S., Suhling, J., and Schrier, H., “Explicit FE-Models and High Speed DIC for Transient-Dynamics of Electronics,” Proceedings of the 2007 SEM Annual Conference, pp. 1-17, Springfield, MA, June 3-6, 2007.

221. Ma, H., Suhling, J. C., Lall, P., and Bozack, M., “Aging of SAC Solder Joints in Harsh Environments,” Proceedings of the SMTA AIMS Harsh Environment Electronics Workshop, pp. 1-18, Indianapolis, IN, June 13-14, 2007.

222. Lall, P., Hariharan, G., Suhling, J., Strickland, M., Blanche, J., “New Package Insertion Risk Assessment Models for Area-Array Electronics in Harsh Thermo-Mechanical Environments,” Proceedings of the SMTA AIMS Harsh Environment Electronics Workshop, pp. 1-20, Indianapolis, IN, June 13-14, 2007.

Exhibit 100200131

Exhibit 1002


223. Lall, P., Hariharan, G., Shirgaokar, A., Suhling, J., Strickland, M., Blanche, J., “Thermo-Mechanical Reliability Based Part Selection Models for Addressing Part Obsolescence in CBGA, CCGA, FLEXBGA, and Flip-Chip Packages,” Proceedings of InterPACK ‘07, Paper IPACK2007-33832, pp. 1-18, Vancouver, British Columbia, Canada, July 8-12, 2007.

224. Lall, P., Choudhary, P., Gupte, S., Gupta, P., and Suhling, J., “Transient-Response Spectral Analysis Based Feature Extraction For Built-In Reliability Test of Electronics Under Shock Loads,” Proceedings of InterPACK ‘07, Paper IPACK2007-33872, pp. 1-19, Vancouver, British Columbia, Canada, July 8-12, 2007.

225. Lall, P., Hande, M., Bhat, C., and Suhling, J., “Leading Prognostic Indicators for Health Management of Electronics Under Thermo-Mechanical Stresses,” Proceedings of InterPACK ‘07, Paper IPACK2007-33876, pp. 1-19, Vancouver, British Columbia, Canada, July 8-12, 2007.

226. Rahim, M. K., Roberts, J. A., Suhling, J. C., Jaeger, R. C., Lall, P., “Die Stress Variation During Thermal Cycling Reliability Tests,” Proceedings of InterPACK ‘07, Paper IPACK2007-33548, pp. 1-12, Vancouver, British Columbia, Canada, July 8-12, 2007.

227. Ma, H., Suhling, J. C., Zhang, Y., Lall, P., and Bozack, M. J., “Evolution of Lead Free Solder Material Behavior Under Elevated Temperature Aging,” Proceedings of InterPACK ‘07, Paper IPACK2007-33545, pp. 1-17, Vancouver, British Columbia, Canada, July 8-12, 2007.

228. Chen, Y., Jaeger, R. C., and Suhling, J. C., “High Resolution Die Stress Mapping Using Arrays of CMOS Sensors,” Proceedings of InterPACK ‘07, Paper IPACK2007-33569, pp. 1-11, Vancouver, British Columbia, Canada, July 8-12, 2007.

229. Knight, R. W., Elkady, Y., Suhling, J. C., and Lall, P., “Causes of Degradation of Thermal Performance of Ball Grid Arrays after Thermal Cycling,” Proceedings of InterPACK ‘07, Paper IPACK2007-33626, pp. 1-8, Vancouver, British Columbia, Canada, July 8-12, 2007.

230. Cho, C. H., Jaeger, R. C., and Suhling, J. C., “Characterization of The Piezoresistive Coefficients of (100) Silicon from -150 to +125 C,” Proceedings of InterPACK ‘07, Paper IPACK2007-33053, pp. 1-14, Vancouver, British Columbia, Canada, July 8-12, 2007.

231. Cho, C. H., Jaeger, R. C., Suhling, J. C., and Rahim, M. K., “Chip-on-Beam and Hydrostatic Calibration of The Piezoresistive Coefficients On (111) Silicon,” Proceedings of InterPACK ‘07, Paper IPACK2007-33570, pp. 1-11, Vancouver, British Columbia, Canada, July 8-12, 2007.

232. Lall, R., Shah, M., Moore, T., Drake, L., and Suhling, J., “Thermo-Mechanical Reliability Management Models for Area-Array Packages on Cu-Core and No-Core Assemblies,” Proceedings of the 2007 SMTA International, pp. 582-596, Orlando, FL, October 7-11, 2007.

Exhibit 100200132

Exhibit 1002


233. Lall, P., Choudhary, P., Gupte, S., Suhling, J., and Hofmeister, J., “Time-Frequency Analysis and Built-in Reliability Test for Health Monitoring of Electronics under Shock Loads,” Proceedings of the 2007 International Mechanical Engineering Congress and Exposition, Paper IMECE2007-42546, pp. 1-19, Seattle, WA, November 11-15, 2007

234. Lall, P., Hande, M., Bhat, C., and Suhling, J., “Methods for System-State Prognostication of Electronics under Thermo-Mechanical Loads,” Proceedings of the 2007 International Mechanical Engineering Congress and Exposition, Paper IMECE2007-42560, pp. 1-16, Seattle, WA, November 11-15, 2007.

235. Xie; F., Flowers, G. T., Chen, C. Bozack, M., Suhling, J., Rickett, B. I., Malucci, R. D., and Manlapaz, C., “Analysis and Prediction of Vibration-Induced Fretting Motion in a Blade/Receptacle Connector Pair,” Proceedings of the 2007 Holm Conference on Electrical Contacts, pp. 222-228, Pittsburgh, PA, September 16-19, 2007.

236. Lall, P., Hande, M., Bhat, C., More, V., Vaidya, R., and Suhling, J., “Prognostication of System-State in Lead-Free Electronics Equipment under Cyclic and Steady-State Thermo-Mechanical Loads,” Proceedings of EuroSimE 2008, pp. 1-14, Freiburg, Germany, April 20-23, 2008.

237. Ma, H., Zhang, Y., Cai, Z., Suhling, J. C., Lall, P., and Bozack, M. J., “Aging Induced Evolution of Lead Free Solder Material Behavior,” Proceedings of EuroSimE 2008, pp. 1-12, Freiburg, Germany, April 20-23, 2008.

238. Lall, P., Iyengar, D., Shantaram, S., Gupta, P., Panchagade, D., and Suhling, J., “Feature Extraction and Health Monitoring using Image Correlation for Survivability of Leadfree Packaging under Shock and Vibration,” Proceedings of EuroSimE 2008, pp. 1-15, Freiburg, Germany, April 20-23, 2008.

239. Zhang, Y., Cai, Z., Suhling, J. C., Lall, P., and Bozack, M. J., “The Effects of Aging Temperature on SAC Solder Joint Material Behavior and Reliability,” Proceedings of the 58th IEEE Electronic Components and Technology Conference, pp. 99-112, Orlando, FL, May 28-30, 2008.

240. Lall, P., Bhat, C., Hande, M., More, V., Vaidya, R., Pandher, R., Suhling, J., and Goebel, K., “Interrogation of System State for Damage Assessment in Lead-Free Electronics Subjected to Thermo-Mechanical Loads, Proceedings of the 58th IEEE Electronic Components and Technology Conference, pp. 919-929, Orlando, FL, May 28-30, 2008.

241. Lall, P., Iyengar, D., Shantaram, S., Pandher, R., Panchagade, D., and Suhling, J., “Design Envelopes and Optical Feature Extraction Techniques for Survivability of SnAgCu Leadfree Packaging Architectures under Shock and Vibration,” Proceedings of the 58th IEEE Electronic Components and Technology Conference, pp. 1036-1047, Orlando, FL, May 28-30, 2008.

Exhibit 100200133

Exhibit 1002


242. Lall, P., Gupta, P., Kulkarni, M., Panchagade, D., Suhling, J., and Hofmeister, J., “Time-Frequency and Auto-Regressive Techniques for Prognostication of Shock-Impact Reliability of Implantable Biological Electronic Systems, Proceedings of the 58th IEEE Electronic Components and Technology Conference, pp. 1196-1207, Orlando, FL, May 28-30, 2008.

243. Roberts, J. C., Rahim, M. K., Suhling, J. C., Jaeger, R. C., Lall, P., Zhang, R., and Jones, J., “Stress Measurements in Large Area Array Flip Chip Microprocessor Chips,” Proceedings of the 58th IEEE Electronic Components and Technology Conference, pp. 1462-1471, Orlando, FL, May 28-30, 2008.

244. Lall, P., Hande, M., Bhat, C., More, V., Vaidya, R., and Suhling, J., “Algorithms for Prognostication of Prior Damage and Residual Life in Lead-Free Electronics Subjected to Thermo-Mechanical Loads,” Proceedings of ITherm 2008, pp. 638-651, Orlando, FL, May 28-31, 2008.

245. Lin, C., Suhling, J. C., and Lall, P., “Physical Aging and Evolving Mechanical Behavior of Underfill Encapsulants,” Proceedings of ITherm 2008, pp. 695-704, Orlando, FL, May 28-31, 2008.

246. Roberts, J. C., Rahim, M. K., Hussain, S., Suhling, J. C., Jaeger, R. C., and Lall, P., “Die Stress Variation in Area Array Components Subjected to Accelerated Life Testing,” Proceedings of ITherm 2008, pp. 705-713, Orlando, FL, May 28-31, 2008.

247. Lall, P., Gupta, P., Choudhary, P., Kulkarni, M., Suhling, J., “Health Monitoring of Implantable Biological Electronic Systems by Statistical Pattern Recognition Techniques,” Proceedings of ITherm 2008, pp. 726-737, Orlando, FL, May 28-31, 2008.

248. Lall, P., Shirgaokar, A., Drake, L., Moore, T., Suhling, J., and Shah, M., “Principal Component Regression Models for Life Prediction of Plastic Ball Grid Arrays on Copper-Core and No-Core Assemblies,” Proceedings of ITherm 2008, pp. 770-785, Orlando, FL, May 28-31, 2008.

249. Lall, P., Iyengar, D., Shantaram, S., Panchagade, D., and Suhling, J., ”Development of Survivability Envelopes for SnAgCu Leadfree Packaging Architectures Under Shock and Vibration,” Proceedings of ITherm 2008, pp. 822-835, Orlando, FL, May 28-31, 2008.

250. Lall, P., Shinde, D., Rickett, B., Suhling, J., “Finite Element Models for Simulation of Wear in Electrical Contacts,” Proceedings of ITherm 2008, pp. 836-841, Orlando, FL, May 28-31, 2008.

251. Roberts, J. C., Rahim, M. K., Suhling, J. C., Jaeger, R. C., and Lall, P., “Characterization of Stress in High Performance Server Microprocessors,” Proceedings of the XIth International Congress on Experimental Mechanics, pp. 1-12, Orlando, FL, June 2-5, 2008.

252. Lall, P., Iyengar, D., Shantaram, S., Panchagade, D., and Suhling, J., “Damage Progression using Speckle-Correlation and High-Speed Imaging for Survivability of Leadfree Packaging under Shock,” Proceedings of the XIth International Congress on Experimental Mechanics, pp. 1-16, Orlando, FL, June 2-5, 2008.

Exhibit 100200134

Exhibit 1002


253. Rodekohr, C. L., Flowers, G. T., Suhling, J. C., and Bozack, M. J., “Auger Electron Spectroscopic (AES) Measurements on High Aspect Ratio Tin Whiskers,” Proceedings of the 2008 Holm Conference on Electrical Contacts, pp. 232-237, Orlando, FL, October 27-29, 2008.

254. Rodekohr, C. L., Flowers, G. T., Suhling, J. C., and Bozack, M. J., “Influence of Substrate Surface Roughness on Tin Whisker Growth,” Proceedings of the 2008 Holm Conference on Electrical Contacts, pp. 245-248, Orlando, FL, October 27-29, 2008.

255. Chen, C. Flowers, G. T., Bozack, M., Suhling, J., Rickett, B. I., Malucci, R. D., and Manlapaz, C., “Modeling and Analysis of a Blade/Receptacle Pair for the Prediction of Vibration-Induced Fretting Degradation,” Proceedings of the 2008 Holm Conference on Electrical Contacts, pp. 276-283, Orlando, FL, October 27-29, 2008.

256. Lall, P., Iyengar, D., Shantaram, S., Panchagade, D., and Suhling, J., “Survivability Assessment of SAC Leadfree Packaging under Shock and Vibration Using Optical High-Speed Imaging,” Proceedings of the 2008 SMTA International Conference, pp. 519-531, Orlando, FL, August 17-21, 2008.

257. Zhang, Y., Mitchell, C., Suhling, J. C., Evans, J. L., Lall, P., and Bozack, M. J., “Properties of Mixed Formulation Solders,” Proceedings of the 2008 SMTA International Conference, pp. 644-651, Orlando, FL, August 17-21, 2008.

258. Lall, P., Bhat, C., Hande, M., More, V., Vaidya, R., Suhling, J., Goebel, K., and Pandher, R., “Interrogation of System State of Aerospace Electronic Systems Subjected To Thermo-Mechanical Loads,” Proceedings of the 2008 SMTA International Conference, pp. 857-869, Orlando, FL, August 17-21, 2008.

259. Lall, P., Bhat, C., Hande, M., More, V., Vaidya, R., Pandher, R., Suhling, J., and Goebel, K., “Latent Damage Assessment and Prognostication of Residual Life in Airborne Lead-Free Electronics under Thermo-Mechanical Loads,” Proceedings of the International Conference on Prognostics and Health Management, pp. 1-12, Denver, CO, October 6-9, 2008.

260. Lall, P., Shirgaokar, A., and Suhling, J., “Models for Component Selection and Thermo-Mechanical Reliability Trade-Offs to Address Component Obsolescence in Military Electronics,” Proceedings of the 2008 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2008-68274, pp. 1-17, Boston, MA, October 31-November 6, 2008.

261. Lall, P., Gupta, P., Kulkarni, M., Panchagade, D., Suhling, J., and Hofmeister, J., “Prognostication and Health Monitoring of Electronics in Implantable Biological Systems,” Proceedings of the 2008 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2008-68275, pp. 1-15, Boston, MA, October 31-November 6, 2008.

Exhibit 100200135

Exhibit 1002


262. Jaeger, R. C., Cho, C. H., Hussain, S., and Suhling, J. C., Impact of Piezoresistive Coefficient Uncertainty on Stress Measurement Using Silicon Multi-Resistor Sensor Rosettes, Proceedings of the 2008 ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2008-67538, pp. 1-12, Boston, MA, October 31-November 6, 2008.

263. Suhling, J. C., Jaeger, R. C., Lall, P., Rahim, M. K., Roberts, J. C., Hussain, S., “Application of Stress Sensing Test Chips to Area Array Packaging,” Proceedings of EuroSimE 2009, pp. 1-12, Delft, The Netherlands, April 26-29, 2009.

264. Lall, P., Gupta, P., Panchagade, D., Kulkarni, M., Suhling, J., and Hofmeister, J., “Prognostics and Condition Monitoring of Electronics,” Proceedings of EuroSimE 2009, pp. 1-14, Delft, The Netherlands, April 26-29, 2009.

265. Lin, C., Suhling, J.C., and Lall, P., “Isothermal Aging Induced Evolution of the Material Behavior of Underfill Encapsulants,” Proceedings of the 59th IEEE Electronic Components and Technology Conference, pp. 134-149, San Diego, CA, May 27-29, 2009.

266. Zhang, Y., Cai, Z., Suhling, J. C., Lall, P., and Bozack, M. J., “The Effects of SAC Alloy Composition on Aging Resistance and Reliability,” Proceedings of the 59th IEEE Electronic Components and Technology Conference, pp. 370-389, San Diego, CA, May 27-29, 2009.

267. Zhang, Y., Kurumaddali, K., Suhling, J. C., Lall, P., and Bozack, M. J., “Analysis of the Mechanical Behavior, Microstructure, and Reliability of Mixed Formulation Solder Joints,” Proceedings of the 59th IEEE Electronic Components and Technology Conference, pp. 759-770, San Diego, CA, May 27-29, 2009.

268. Zhang, Y., Cai, Z., Suhling, J. C., Lall, P., and Bozack, M. J., “Aging Effects In SAC Solder Joints,” Proceedings of the 2009 SEM Spring Conference on Experimental Mechanics, pp. 1-14, Albuquerque, NM, June 1-4, 2009.

269. Zhang, Y., Kurumaddali, K., Suhling, J. C., Lall, P., and Bozack, M. J., “Material Behavior of Mixed Formulation Solder Joints,” Proceedings of InterPACK ’09, Paper IPACK2009-89003, pp. 1-12, San Francisco, CA, July 18-23, 2009.

270. Tian, G., Lin, C., Suhling, J. C., and Lall, P., “Cure Profile Effects on the Mechanical Behavior and Reliability of Flip Chip on Laminate Assemblies,” Proceedings of InterPACK ’09, Paper IPACK2009-89209, pp. 1-8, San Francisco, CA, July 18-23, 2009.

271. Lall, P., Gupta, P., Angral, A., and Suhling, J., “Anomaly-Detection and Prognostication of Electronics Subjected to Shock and Vibration,” Proceedings of InterPACK ’09, Paper IPACK2009-89298, pp. 1-15, San Francisco, CA, July 18-23, 2009.

272. Lall, P., Vaidya, R., More, V., Suhling, J., and Goebel, K., “Remaining Useful-Life Based on Damage Pre-Cursors for Leadfree Electronics Subjected to Multiple Thermal-Environments,” Proceedings of InterPACK ’09, Paper IPACK2009-89299, pp. 1-13, San Francisco, CA, July 18-23, 2009.

Exhibit 100200136

Exhibit 1002


273. Lall, P., Shantaram, S., Angral, A., Kulkarni, M., and Suhling, J., “Damage Accumulation and Life-Prediction Models for SnAgCu Leadfree Electronics Under Shock-Impact,” Proceedings of InterPACK ’09, Paper IPACK2009-89307, pp. 1-15, San Francisco, CA, July 18-23, 2009.

274. Lall, P., Lowe, R., Suhling, J., and Goebel, K., “Leading-Indicators Based on Impedance Spectroscopy for Prognostication of Electronics Under Shock and Vibration Loads,” Proceedings of InterPACK ’09, Paper IPACK2009-89308, pp. 1-12, San Francisco, CA, July 18-23, 2009.

275. Lall, P., Shirgaokar, A., Arunachalam, D., Suhling, J., Strickland, M., and Blanche, J., “PCR for Derivation of Parameter Dependencies, Thermo-Mechanical Norris-Landzberg Acceleration Factors, Goldmann Fatigue Constants for Leadfree Electronics,” Proceedings of InterPACK ’09, Paper IPACK2009-89329, pp. 1-12, San Francisco, CA, July 18-23, 2009.

276. Lin, C., Suhling, J.C., and Lall, P., “Evolution of the Stress-Strain and Creep Behavior of Underfill Encapsulants with Aging,” Proceedings of InterPACK ’09, Paper IPACK2009-89371, pp. 1-17, San Francisco, CA, July 18-23, 2009.

277. Zhang, Y., Cai, Z., Suhling, J. C., and Lall, P., “Aging Effects on the Mechanical Behavior and Reliability of SAC Alloys,” Proceedings of InterPACK ’09, Paper IPACK2009-89373, pp. 1-18, San Francisco, CA, July 18-23, 2009.

278. Roberts, J. C., Rahim, M. K., Suhling, J. C., Jaeger, R. C., Lall, P., and Zhang, R., “Characterization of Die Stress Distributions in Area Array Flip Chip Packaging,” Proceedings of InterPACK ’09, Paper IPACK2009-89383, pp. 1-12, San Francisco, CA, July 18-23, 2009.

279. Jaeger, R. C., Suhling, J. C., Hussain, S., Roberts, J. C., Motalab, M. A., Cho, C. H., “Stress Measurement Errors in Flip Chip Packages Using Multi-Element Sensor Rosettes on (111) Silicon,” Proceedings of InterPACK ’09, Paper IPACK2009-89245, pp. 1-11, San Francisco, CA, July 18-23, 2009.

280. Chen, C., Flowers, G. T., Bozack, M., and Suhling, J., “Modeling and Analysis of a Connector System for the Prediction of Vibration-induced Fretting Degradation,” Proceedings of the 55th IEEE Holm Conference on Electrical Contacts, pp. 131-137, Vancouver, British Columbia, September 14-16, 2009.

281. Angadi, S. V., Jackson, R. L., Choe, S.-Y., Flowers, G. T., Suhling, J. C., Chang, Y.-K., Ham, J.-K., “Reliability and Life Study of Hydraulic Solenoid Valve - Part 1 - A Multi-physics Finite Element Model,” Proceedings of the SAE 2009 World Congress, Detroit, MI, April 20-23, 2009.

282. Roberts, J. C., Rahim, M. K., Hussain, S., Suhling, J. C., Jaeger, R. C., Lall, P., “Stresses in Area Array Assemblies Subjected to Thermal Cycling,” Proceedings of the ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2009-11925, pp. 1-12, Lake Buena Vista, FL, Nov 13-19, 2009.

283. Lall, P., Gupta, P., Angral, A., Suhling, J., “Feature Vector Based Failure Mode Identification And Prognostication Of Electronics Subjected To Shock And Vibration,” Proceedings of the ASME International Mechanical Engineering Congress and Exposition, pp. 1-15, Lake Buena Vista, FL, Nov 13-19, 2009.

Exhibit 100200137

Exhibit 1002


284. Lall, P., Lowe, R., Suhling, J., “Prognostication Based On Resistance-Spectroscopy For High Reliability Electronics Under Shock-Impact,” Proceedings of the ASME International Mechanical Engineering Congress and Exposition, pp. 1-12, Lake Buena Vista, FL, Nov 13-19, 2009.

285. Lall, P., Vaidya, R., More, V., Suhling, J., “Leading Indicators Of Damage For Prognostication Of Leadfree Electronics Subjected To Multiple Thermo-Mechanical Environments,” Proceedings of the ASME International Mechanical Engineering Congress and Exposition, pp. 1-13, Lake Buena Vista, FL, Nov 13-19, 2009.

286. Lall, P., Lowe, R., Suhling, J., “Prognostication For Impending Failure In Leadfree Electronics Subjected to Shock and Vibration Using Resistance Spectroscopy,” Proceedings of the IMAPS 42nd Symposium on Microelectronics, pp. 195-202, San Jose, CA, Nov 1-5, 2009.

287. Lall, P., Shantaram, S., Angral, A., Kulkarni, M., Suhling, J., “Models For Prediction Of Shock Reliability For Leadfree Area-Array Components In Portable Electronics,” Proceedings of the AIMS Harsh Environment Electronics Workshop and SMTAI Technical Conference, pp. 55-69, San Diego, CA, Oct 4-8, 2009.

288. Lall, P., Vaidya, R., More, V., Suhling, J., “Assessment Of Accrued Thermo-Mechanical Damage In Leadfree Parts During Field-Exposure To Multiple Environments,” Proceedings of the AIMS Harsh Environment Electronics Workshop and SMTAI Technical Conference, pp. 907-919, San Diego, CA, Oct 4-8, 2009.

289. Lall, P., Vaidya, R., More, V., Goebel, K., Suhling, J., “Assessment of Residual Damage in Lead-free Electronics Subjected to Multiple Thermal Environments of Thermal Aging and Thermal Cycling,” Proceedings of the 60th IEEE Electronic Components and Technology Conference, pp. 206-218, Las Vegas, NV, June 1-4, 2010.

290. Lall, P., Kulkarni, M., Angral, A., Panchagade, D., Suhling, J., “Digital-Image Correlation and XFEM Based Shock-Reliability Models for Leadfree and Advanced Interconnects,” Proceedings of the 60th IEEE Electronic Components and Technology Conference, pp. 91-105,, Las Vegas, NV, June 1-4, 2010.

291. Roberts, J., Hussain, S., Rahim, M. K., Motalab, M., Suhling, J., Jaeger, R., Lall, P., Zhang, R., “Characterization of Microprocessor Chip Stress Distributions During Component Packaging and Thermal Cycling,” Proceedings of the 60th IEEE Electronic Components and Technology Conference, pp. 1281-1295,, Las Vegas, NV, June 1-4, 2010.

292. Cai, Z., Zhang, Y., Suhling, J., Lall, P., Johnson, R. W., Bozack, M., “Reduction of Lead Free Solder Aging Effects using Doped SAC Alloys,” Proceedings of the 60th IEEE Electronic Components and Technology Conference, pp. 1493-1511, Las Vegas, NV, June 1-4, 2010.

Exhibit 100200138

Exhibit 1002


293. Lall, P., Vaidya, R., More, V., Suhling, J., Goebel, K., “PHM-Based Residual Life Computation of Electronics Subjected to a Combination of Multiple Cyclic-Thermal Environments,” Proceedings of ITherm 2010, pp. 1-12, Las Vegas, NV, June 2-5, 2010.

294. Lall P., Angral, A., Suhling, J., “Board Trace Fatigue Models and Design Guidelines for Electronics Under Shock-Impact,” Proceedings of ITherm 2010, pp. 1-7, Las Vegas, NV, June 2-5, 2010.

295. Lall, P., Hinshaw, R., Harsha, M., Suhling, J., Pandher, R., “Thermo-Mechanical Reliability of SAC Leadfree Alloys,” Proceedings of ITherm 2010, pp. 1-5, Las Vegas, NV, June 2-5, 2010.

296. Roberts, J., Hussain, S., Rahim, M. K., Motalab, M., Suhling, J., Jaeger, R., Lall, P., Zhang, R., Measurement of Die Stress Distributions in Flip Chip CBGA Packaging, Proceedings of ITherm 2010, pp. 1-13, Las Vegas, NV, June 2-5, 2010.

297. Zhang, Y., Cai, Z., Mustafa, M., Suhling, J., Lall, P., Bozack, M., “The Influence of Aging on the Stress-Strain and Creep Behavior of SAC Solder Alloys,” Proceedings of ITherm 2010, pp. 1-18, Las Vegas, NV, June 2-5, 2010.

298. Lin, C., Chhanda, N., Suhling, J. C., and Lall, P., “The Influence of Aging on the Creep Behavior of Underfill Encapsulants,” Proceedings of ITherm 2010, pp. 1-11, Las Vegas, NV, June 2-5, 2010.

299. Hussain, S., Jaeger, R. C., Suhling, J. C., Roberts, J. C., Motalab, M. A., and Cho, C. H., “Error Analysis for Piezoresistive Stress Sensors Used in Flip Chip Packaging,” Proceedings of ITherm 2010, pp. 1-12, Las Vegas, NV, June 2-5, 2010.

300. Rodekohr, C. L., Bozack, M. J., Flowers, G. T., Suhling, J. C., Rodekohr, D. A., “The Effects of Surface Finish Roughness on Intermetallic Layer Growth, Intermetallic Interface Roughness, and Solder Joint Reliability,” Proceedings of the 56th IEEE Holm Conference on Electrical Contacts, Charleston, SC, October 4-7, 2010.

301. Roberts, J. C., Motalab, M., Hussain, S., Suhling, J. C., Jaeger, R. C., Lall, P., “Squeezing the Chip: The Buildup of Compressive Stress in a Microprocessor Chip by Packaging and Heat Sink Clamping,” Proceedings of the 61st IEEE Electronic Components and Technology Conference, pp. 406-423, Orlando, FL, June 1-3, 2011.

302. Mustafa, M., Cai, Z., Suhling, J. C., and Lall, P., “The Effects of Aging on the Cyclic Stress-Strain Behavior and Hysteresis Loop Evolution of Lead Free Solders,” Proceedings of the 61st IEEE Electronic Components and Technology Conference, pp. 927-939, Orlando, FL, June 1-3, 2011.

303. Lall, P., Shantaram, S., Kulkarni, M., Limaye, G., Suhling, J., “High Strain-Rate Mechanical Properties of SnAgCu Leadfree Alloys, Electronic Components and Technology Conference,” Proceedings of the 61st IEEE Electronic Components and Technology Conference, pp. 684-700, Orlando, FL, June 1-3, 2011.

Exhibit 100200139

Exhibit 1002


304. Lall, P., Harsha, M., Kumar, K., Goebel, K., Jones, J., Suhling, J., “Interrogation of Accrued Damage and Remaining Life in Field-Deployed Electronics Subjected to Multiple Thermal Environments of Thermal Aging and Thermal Cycling,” Proceedings of the 61st IEEE Electronic Components and Technology Conference, pp. 775-789, Orlando, FL, June 1-3, 2011.

305. Cai, Z., Suhling, J. C., Lall, P., Bozack, M. J., “The Effects of Dopants on the Aging Behavior of Lead Free Solders,” Proceedings of InterPACK 2011, Paper InterPACK2011-52184, pp. 1-16, Portland, OR, July 6-8, 2011.

306. Roberts, J. C., Motalab, M., Hussain, S., Suhling, J. C., Jaeger, R. C., Lall, P., “Characterization of Die Stresses in CBGA Packages due to Component Assembly and Heat Sink Clamping,” Proceedings of InterPACK 2011, Paper InterPACK2011-52185, pp. 1-14, Portland, OR, July 6-8, 2011.

307. Mustafa, M., Cai, Z., Suhling, J. C., Lall, P., “Characterization of Hysteresis Loop Evolution in Aged Lead Free Solders,” Proceedings of InterPACK 2011, Paper InterPACK2011-52186, pp. 1-12, Portland, OR, July 6-8, 2011.

308. Chhanda, N. J., Suhling, J. C., Lall, P., “Experimental Characterization and Viscoplastic Modeling of the Temperature Dependent Material Behavior of Underfill Encapsulants,” Proceedings of InterPACK 2011, Paper InterPACK2011-52209, pp. 1-13, Portland, OR, July 6-8, 2011.

309. Lall, P., Shantaram, S., Kulkarni, M., Limaye, G., Suhling, J., “Constitutive Behavior of SAC Leadfree Alloys at High Strain Rates,” Proceedings of InterPACK 2011, Paper InterPACK2011-52194, pp. 1-18, Portland, OR, July 6-8, 2011.

310. Lall, P., Arunachalam, D., Suhling, J., “Ridge Regression Based Development of Norris-Landzberg Acceleration Factors and Goldmann Constants for Leadfree Electronics,” Proceedings of InterPACK 2011, Paper InterPACK2011-52195, pp. 1-11, Portland, OR, July 6-8, 2011.

311. Lall, P., Shantaram, S., Kulkarni, M., Suhling, J., “SIF Evaluation Using XFEM and Line Spring Models Under High Strain Rate Environment for Leadfree Alloys,” Proceedings of InterPACK 2011, Paper InterPACK2011-52196, pp. 1-17, Portland, OR, July 6-8, 2011.

312. Lall, P., Angral, A., Suhling, J., “Reliability Studies for Package-on-Package Components in Drop and Shock Environments,” Proceedings of InterPACK 2011, Paper InterPACK2011-52231, pp. 1-12, Portland, OR, July 6-8, 2011.

313. Lall, P., Shantaram, S., Kulkarni, M., Limaye, G., Suhling, J., “Stress-Strain Behavior if SnAgCu Leadfree Alloys at High Strain Rates Typical of Mechanical Shock,” Proceedings of the SMTAI Conference, pp. 617-633, Ft. Worth, TX, October 16-20, 2011.

314. Lall, P., P., Harsha, M., Suhling, J., Goebel, K., Jones, J., “Accrued Damage and Remaining Useful Life in Field Extracted Assemblies Under Sequential Thermo-mechanical Loads,” Proceedings of the ASME International Mechanical Engineering Congress and Exposition, Paper IMECE2011-65834, pp. 1-16, Denver, CO, November 11-17, 2011.

Exhibit 100200140

Exhibit 1002


315. Motalab, M., Cai, Z., Suhling, J. C., Zhang, J., Evans, J. L., Bozack, M. J., Lall, P., “Improved Predictions of Lead Free Solder Joint Reliability that Include Aging Effects,” Proceedings of the 62nd IEEE Electronic Components and Technology Conference, pp. 513-531, San Diego, CA, May 30 - June 1, 2012.

316. Roberts, J. C., Motalab, M., Hussain, S., Suhling, J. C., Jaeger, R. C., Lall, P., “Measurement of Die Stresses in Microprocessor Packaging Due to Thermal and Power Cycling,” Proceedings of the 62nd IEEE Electronic Components and Technology Conference, pp. 756-770, San Diego, CA, May 30 - June 1, 2012.

317. Lall, P., Shantaram, S., Suhling, J., Locker, D., “Effect of High Strain-Rate on Mechanical Properties of SAC105 AND SAC305 Leadfree Alloys,” Proceedings of the 62nd IEEE Electronic Components and Technology Conference, pp. 1312-1326, San Diego, CA, May 30 - June 1, 2012.

318. Lall, P., Harsha, M., Suhling, J., Goebel, K., “Sustained Damage and Remaining Useful Life Assessment in Leadfree Electronics Subjected to Sequential Multiple Thermal Environments,” Proceedings of the 62nd IEEE Electronic Components and Technology Conference, pp. 1695-1708, San Diego, CA, May 30 - June 1, 2012.

319. Lall, P., Narayan, V., Suhling, J., Blanche, J., Strickland, M., “Effect of Reflow Process on Glass Transition Temperature of Printed Circuit Board Laminates,” Proceedings of ITherm 2012, pp. 261-268, San Diego, CA, May 30 - June 1, 2012.

320. Chhanda, N. J., Suhling, J. C., Lall, P., “Implementation of a Viscoelastic Model for the Temperature Dependent Material Behavior of Underfill Encapsulants,” Proceedings of ITherm 2012, pp. 269-281, San Diego, CA, May 30 - June 1, 2012.

321. Lall, P., Harsha, M., Goebel, K., Jones, J., Suhling, J., “Leading Indicator Based Assessment of Operational Readiness in Electronics Subjected To Multiple Environments,” Proceedings of ITherm 2012, pp. 639-653, San Diego, CA, May 30 - June 1, 2012.

322. Lall, P., Limaye, G., Suhling, J., Murtuza, M., Palmer, B., Cooper, W., “Reliability of Lead-free SAC Electronics Under Simultaneous Exposure to High Temperature and Vibration,” Proceedings of ITherm 2012, pp. 753-761, San Diego, CA, May 30 - June 1, 2012.

323. Mustafa, M., Cai, Z., Roberts, J. R., Suhling, J. C., Lall, P., “Evolution of the Tension/Compression and Shear Cyclic Stress-Strain Behavior of Lead-Free Solder Subjected to Isothermal Aging,” Proceedings of ITherm 2012, pp. 765-780, San Diego, CA, May 30 - June 1, 2012.

324. Cai, Z., Suhling, J. C., Lall, P., Bozack, M. J., “Mitigation of Lead Free Solder Aging Effects using Doped SAC-X Alloys,” Proceedings of ITherm 2012, pp. 896-909, San Diego, CA, May 30 - June 1, 2012.

325. Motalab, M., Cai, Z., Suhling, J. C., Lall, P., “Determination of Anand constants for SAC Solders using Stress-Strain or Creep Data,” Proceedings of ITherm 2012, pp. 910-922, San Diego, CA, May 30 - June 1, 2012.

Exhibit 100200141

Exhibit 1002


326. Roberts, J. C., Hussain, S., Suhling, J. C., Jaeger, R. C., Lall, P., “Characterization of Die Stresses in Microprocessor Packages Subjected to Thermal Cycling,” Proceedings of ITherm 2012, pp. 1003-1014, San Diego, CA, May 30 - June 1, 2012.

327. Lall, P., Shantaram, S., Suhling, J., Locker, D., “Mechanical Deformation Behavior of SAC305 at High Strain Rates,” Proceedings of ITherm 2012, pp. 1037-1051, San Diego, CA, May 30 - June 1, 2012.

328. Lall, P., Shantaram, S., Suhling, J., Locker, D., Mechanical Behavior of Sn1Ag0.5Cu and Sn3Ag0.5Cu Alloys at High Strain Rates, Proceedings of the ASME 2012 International Mechanical Engineering Congress and Exposition, Paper Number IMECE2012-93059, pp. 1-15, Houston, Texas, November 9-15, 2012.

329. Hasnine, M., Mustafa, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., Lall, P., “Characterization of Aging Effects in Lead Free Solder Joints Using Nanoindentation,” Proceedings of the 63rd IEEE Electronic Components and Technology Conference, pp. 166-178, Las Vegas, NV, May 28-31, 2013.

330. Motalab, M., Cai, Z., Suhling, J. C., Zhang, J., Evans, J. L., Bozack, M. J., Lall, P., “Correlation of Reliability Models Including Aging Effects with Thermal Cycling Reliability Data,” Proceedings of the 63rd IEEE Electronic Components and Technology Conference, pp. 986-1004, Las Vegas, NV, May 28-31, 2013.

331. Lall, P., Shantaram, S., Suhling, J., Locker, D., “Effect of Aging on the High Strain Rate Mechanical Properties of SAC105 and SAC305 Leadfree Alloys,” Proceedings of the 63rd IEEE Electronic Components and Technology Conference, pp. 1277-1293, Las Vegas, NV, May 28-31, 2013.

332. Lall, P., Mirza, K., Harsha, M., Suhling, J., Goebel, K., “Damage Pre-Cursor Based Assessment of Impact of High Temperature Storage on Reliability of Lead-free Electronics,” Proceedings of the 63rd IEEE Electronic Components and Technology Conference, pp.817-826, Las Vegas, NV, May 28-31, 2013.

333. Hasnine, M., Mustafa, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., and Lall, P., “Nanomechanical Characterization of Lead Free Solder Joints,” in Proceedings of the 2013 SEM Conference on Experimental Mechanics, Paper 446, pp. 1-11, Lombard, IL, June 3-6, 2013.

334. Motalab, M., Mustafa, M., Suhling, J. C., Zhang, J., Evans, J. L., Bozack, M. J., Lall, P., “Thermal Cycling Reliability Predictions for PBGA Assemblies that Include Aging Effects,” Proceedings of InterPACK 2013, InterPACK2013-73230, pp. 1-20, Burlingame, CA, July 16-18, 2013.

335. Motalab, M., Basit, M., Suhling, J. C., Lall, P., “A Revised Anand Constitutive Model for Lead-free Solder that Includes Aging Effects, Proceedings of InterPACK 2013, InterPACK2013-73232, pp. 1-20, Burlingame, CA, July 16-18, 2013.

336. Hasnine, M., Mustafa, M., Zou, J., Suhling, J. C., Prorok, B. C., Bozack, M. J., Lall, P., “Nanomechanical Characterization of Aging Effects in Solder Joints in Microelectronic Packaging,” Proceedings of InterPACK 2013, InterPACK2013-73234, pp. 1-14, Burlingame, CA, July 16-18, 2013.

Exhibit 100200142

Exhibit 1002


337. Mustafa, M., Roberts, J. C., Suhling, J. C., Lall, P., “The Effects of Aging of the Cyclic Stress-Strain and Fatigue Behaviors of Lead-free Solders,” Proceedings of InterPACK 2013, InterPACK2013-73240, pp. 1-12, Burlingame, CA, July 16-18, 2013.

338. Cai, Z., Suhling, J. C., Bozack, M. J., Lall, P., “Aging Induced Mechanical Property Degradation and Microstructure Evolution of SAC+X Lead-free Solder Alloys,” Proceedings of InterPACK 2013, InterPACK2013-73241, pp. 1-13, Burlingame, CA, July 16-18, 2013.

339. Chhanda, N. J., Suhling, J. C., Lall, P., “Effects of Moisture Exposure on the Mechanical Behavior of Polymer Encapsulants in Microelectronic Packaging,” Proceedings of InterPACK 2013, InterPACK2013-73242, pp. 1-9, Burlingame, CA, July 16-18, 2013.

340. Roberts, J. C., Motalab, M., Hussain, S., Suhling, J. C., Jaeger, R. C., Lall, P., “Measurement of Microprocessor Die Stress Due to Thermal Cycling, Power Cycling and Second Level Assembly,” Proceedings of InterPACK 2013, InterPACK2013-73244, pp. 1-11, Burlingame, CA, July 16-18, 2013.

341. Hussain, S., Gnanachchelvi, P., Suhling, J. C., Jaeger, R. C., Hamilton, M. C., Wilamowski, B. M., “The Influence of Uniaxial Normal Stress on the Performance of Vertical Bipolar Transistors,” Proceedings of InterPACK 2013, InterPACK2013-73233, pp. 1-13, Burlingame, CA, July 16-18, 2013.

342. Jaeger, R. C., Motalab, M., Hussain, S., Suhling, J. C., “Four-Wire Bridge Measurements of Van der Pauw Stress Sensors on (100) and (111) Silicon,” Proceedings of InterPACK 2013, InterPACK2013-73249, pp. 1-11, Burlingame, CA, July 16-18, 2013.

343. Lall, P., Limaye, G., Shantaram, S., Suhling, J., Effect of Isothermal Aging and High Strain Rate on Material Properties of Innolot, Proceedings of InterPACK 2013, InterPACK2013-73246, pp. 1-13, Burlingame, CA, July 16-18, 2013.

344. Lall, P., Harsha, M., Suhling, J., Goebel, K., Damage Pre-Cursors Based Prognostication of Accrued Damage and Assessment of Operational Readiness of Lead-free Electronics, Proceedings of InterPACK 2013, InterPACK2013-73251, pp. 1-17, Burlingame, CA, July 16-18, 2013.

345. Lall, P., Mirza, K., Harsha, M., Suhling, J., Method for Assessment of Prolonged and Intermittent Storage on Reliability of Lead-free Electronics using Leading Indicators, Proceedings of InterPACK 2013, InterPACK2013-73309, pp. 1-11, Burlingame, CA, July 16-18, 2013.

346. Jaeger, R. C., Hussain, S., Suhling, J. C., Gnanachchelvi, P., Wilamowski, B. M., Hamilton, M. C., “Impact of Mechanical Stress on Bipolar Transistor Current Gain and Early Voltage,” Proceedings of the IEEE Sensors Conference, pp. 1-4, Baltimore, MD, November 4-6, July 16-18, 2013.

347. Hasnine, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., and Lall, P., “Exploration of Aging Induced Evolution of Solder Joints Using Nanoindentation and Microdiffraction,” Proceedings of the 64th IEEE Electronic Components and Technology Conference, pp. 379-394, Orlando, FL, May 28-30, 2014.

Exhibit 100200143

Exhibit 1002


348. Mustafa, M., Roberts, J. C, Suhling, J. C, and Lall, P., “The Effects of Aging on the Fatigue Life of Lead Free Solders,” Proceedings of the 64th IEEE Electronic Components and Technology Conference, pp. 666-683, Orlando, FL, May 28-30, 2014.

349. Lall, P., Mirza, K., Suhling, J., “Damage Pre-Cursor Based Life Prediction of the Effect of Mean Temperature of Thermal Cycle on the SnAgCu Solder Joint Reliability,” Proceedings of the 64th IEEE Electronic Components and Technology Conference, pp. 990-1003, Orlando, FL, May 28-30, 2014.

350. Lall, P., Yadav, V., Zhang, D., Suhling, J., and Shantaram, S., “High Strain Rate Mechanical Properties of SAC105 Leadfree Alloy at High Operating Temperatures,” Proceedings of the 64th IEEE Electronic Components and Technology Conference, pp. 161-169, Orlando, FL, May 28-30, 2014.

351. Lall, P., Deshpande, S., Wei, J., Suhling, J., “Non-Destructive Crack and Defect Detection in SAC Solder Interconnects Using Cross-Sectioning and X-Ray Micro-CT,” Proceedings of the 64th IEEE Electronic Components and Technology Conference, pp. 1449-1456, Orlando, FL, May 28-30, 2014.

352. Chhanda, N. J., Suhling, J. C., and Canumalla, S., “Effects of Moisture Exposure on the Mechanical Behavior of Polycarbonate Materials Used in Electronic Packaging,” Proceedings of ITherm 2014, pp. 355-364, Orlando, FL, May 28-30, 2014.

353. Basit, M. M., Motalab, M., Suhling, J. C., and Lall, P., “The Effects of Aging on the Anand Viscoplastic Constitutive Model for SAC305 Solder,” Proceedings of ITherm 2014, pp. 112-126, Orlando, FL, May 28-30, 2014.

354. Basit, M. M., Motalab, M., Roberts, J. C., Suhling, J. C., and Lall, P., “The Effects of Silver Content and Solidification Profile on the Anand Constitutive Model for SAC Lead Free Solders,” Proceedings of ITherm 2014, pp. 488-502, Orlando, FL, May 28-30, 2014.

355. Mustafa, M., Roberts, J. C., Suhling, J. C., and Lall, P., “The Effects of Aging on Shear Cyclic Stress Strain and Fatigue Behaviors of Lead Free Solder Joints,” Proceedings of ITherm 2014, pp. 142-151, Orlando, FL, May 28-30, 2014.

356. Hussain, S., Jaeger, R. C., Suhling, J. C., Wilamowski, B. M., Hamilton, M. C., and Gnanachchelvi, P., “Understanding the Impact of Temperature Variations on Measurement of Stress Dependent Parameters of Bipolar Junction Transistors,” Proceedings of ITherm 2014, pp. 1244-1250, Orlando, FL, May 28-30, 2014.

357. Nguyen, Q., Roberts, J. C., Suhling, J. C., and Jaeger, R. C., “Characterization of Moisture and Thermally Induced Die Stresses in Flip Chip on Laminate Assemblies,” Proceedings of ITherm 2014, pp. 503-512, Orlando, FL, May 28-30, 2014.

358. Motalab, M., Basit, M., Suhling, J. C., Bozack, M. J., and Lall, P., “Creep Test Method for Determination of Anand Parameters for Lead Free Solders and their Variation with Aging,” Proceedings of ITherm 2014, pp. 127-141, Orlando, FL, May 28-30, 2014.

Exhibit 100200144

Exhibit 1002


359. Hasnine, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., and Lall, P., “Nanomechanical Characterization of SAC305 Solder Joints – Effects of Aging,” Proceedings of ITherm 2014, pp. 152-160, Orlando, FL, May 28-30, 2014.

360. Chhanda, N., Suhling, J. C., and Lall, P., “Effects of Moisture Exposure on the Mechanical Behavior of Flip Chip Underfills in Microelectronic Packaging,” Proceedings of ITherm 2014, pp. 333-345, Orlando, FL, May 28-30, 2014.

361. Lall, P., Zhang, D., Yadav, V., Suhling, J., Shantaram, S., “Material Behavior of SAC305 under High Strain Rate at High Temperature,” Proceedings of ITherm 2014, pp. 1261-1269, Orlando, FL, May 28-30, 2014.

362. Lall, P., Yadav, V., Zhang, D., Suhling, J., Shantaram, S., “High Strain Rate Mechanical Properties of SAC105 Leadfree Alloy at High Operating Temperatures,” Proceedings of ITherm 2014, pp. 161-169, Orlando, FL, May 28-30, 2014.

363. Thirugnanasambandam, S., Sanders, T., Raj, A., Stone, D., Evans, J., Flowers, G., and Suhling, J., “The Study of Vibrational Performance on Different Doped Low Creep Lead Free Solder Paste and Solder Ball Grid Array Packages,” Proceedings of ITherm 2014, pp. 920-923, Orlando, FL, May 28-30, 2014.

364. Hussain, S., Jaeger, R. C., and Suhling, J. C., “Current Dependence of the Piezoresistive Coefficients of CMOS FETs on (100) Silicon,” Proceedings of the 44th European Solid State Device Research Conference (ESSDERC),” pp. 74-77, Venice, Italy, September 22-26, 2014.

365. Basit, M., Motalab, M., Suhling, J. C., Hai, Z., Evans, J. L., Bozack, M. J., and Lall, P., “Thermal Cycling Reliability of Aged PBGA Assemblies - Comparison of Weibull Failure Data and Finite Element Model Predictions,” Proceedings of the 65th IEEE Electronic Components and Technology Conference, pp. 106-117, San Diego, CA, May 27-29, 2015.

366. Hasnine, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., and Lall, P., “Nanomechanical Characterization of SAC Solder Joints - Reduction of Aging Effects Using Microalloy Additions,” Proceedings of the 65th IEEE Electronic Components and Technology Conference, pp. 1574-1585, San Diego, CA, May 27-29, 2015.

367. Lall, P., Zhang, D., and Suhling, J., “High Strain Rate Properties of SAC305 Leadfree Solder at High Operating Temperature after Long-Term Storage,” Proceedings of the 65th IEEE Electronic Components and Technology Conference, pp. 640-651, San Diego, CA, May 27-29, 2015.

368. Lall, P., Duraisamy, S. M., Suhling, J. and Evans, J., “Principal Components Regression Model for Prediction of Life-Reduction in SAC Leadfree Interconnects During Long-Term High Temperature Storage,” Proceedings of the 65th IEEE Electronic Components and Technology Conference, pp. 2040-2047, San Diego, CA, May 27-29, 2015.

Exhibit 100200145

Exhibit 1002


369. Basit, M., Motalab, M., Suhling, J. C., and Lall, P., “Viscoplastic Constitutive Model for Lead-Free Solder Including Effects of Silver Content, Solidification Profile, and Severe Aging,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48619, San Francisco, CA, pp. 1-18, July 6-9, 2015.

370. Basit, M., Motalab, M., Suhling, J. C., Evans, J. L., and Lall, P., “FEA Based Reliability Predictions For PBGA Packages Subjected to Isothermal Aging Prior to Thermal Cycling,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48620, San Francisco, CA, pp. 1-11, July 6-9, 2015.

371. Chowdhury, P. R., Chhanda, N. J., Suhling, J. C., and Lall, P., “Experimental Characterization of Underfill Materials Exposed to Moisture Including Preconditioning,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48622, San Francisco, CA, pp. 1-9, July 6-9, 2015.

372. Hasnine, M., Suhling, J. C., Prorok, B. C., Bozack, M. J., and Lall, P., “Characterization of the Effects of Silver Content on the Aging Resistance of SAC Solder Joints,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48623, San Francisco, CA, pp. 1-15, July 6-9, 2015.

373. Ahmed, S., Basit, M., Suhling, J. C., and Lall, P., “Characterization of Doped SAC Solder Materials and Determination of Anand Parameters,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48624, San Francisco, CA, pp. 1-14, July 6-9, 2015.

374. Nguyen, Q., Roberts, J. C., Suhling, J. C., Jaeger, R. C., and Lall, P., “Measurement and Simulation of Moisture Induced Die Stresses in Flip Chip on Laminate Assemblies,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48626, San Francisco, CA, pp. 1-13, July 6-9, 2015.

375. Nguyen, Q., Rahim, M. K., Roberts, J. C., Suhling, J. C., and Jaeger, R. C., “Characterization of Die Stresses in Plastic Packages Subjected to Moisture and Thermal Exposures,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48627, San Francisco, CA, pp. 1-12, July 6-9, 2015.

376. Lall, P., Yadav, V., Suhling, J., and Locker, D., “A Study on the Evolution of the High Strain Rate Mechanical Properties of SAC105 Leadfree Alloy at High Operating Temperatures,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48389, San Francisco, CA, pp. 1-17, July 6-9, 2015.

377. Lall, P., Mirza, K., and Suhling, J., “DIC Based Investigation into the Effect of Mean Temperature of Thermal Cycle on the Strain State in SnAgCu Solder Joint,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48727, San Francisco, CA, pp. 1-13, July 6-9, 2015.

378. Shen, C., Hai, Z., Zhao, C., Zhang, J., Bozack, M. J., Suhling, J. C., and Evans, J. L., “Reliability Analysis of Aging in Joint Microstructures for Sn-Ag-Cu Solder Joints During Thermal Cycling,” Proceedings of InterPACK 2015, Paper IPACKICNMM2015-48009, San Francisco, CA, pp. 1-8, July 6-9, 2015.

Exhibit 100200146

Exhibit 1002


379. Jaeger, R. C., Hussain, S., Niu, G., Gnanachchelvi, P., Suhling, J. C., Wilamowski, B. M., and Hamilton, M. C., “Characterization of Residual Stress Levels in Complementary Bipolar Junction Transistors on (100) Silicon,” Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting – BCTM, pp. 60-63, Boston, MA, October 26-28, 2015.

380. Lall, P., Zhang, D., Suhling, J., and Locker, D., “Anand Viscoplasticity Model for the Effect of Aging on Mechanical Behavior of SAC305 Operating at High Strain Rate and High Temperature,” Proceedings of the ASME 2015 International Mechanical Engineering Congress and Exposition, Paper Number IMECE2015 53751, pp. 1-11, Houston, TX, Nov 13-19, 2015.

Exhibit 100200147

Exhibit 1002

Conference Presentations (Abstract Only)

1. Suhling, J. C., “Failure Predictions for Paperboard,” Presented at the 1984 Graduate Conference on Experimental Mechanics, Purdue University, West Lafayette, IN, September 7-8, 1984.

2. Suhling, J. C., “Formulation and Application of Constitutive Relations for Nonlinear Orthotropic Media,” Presented at the 1985 Graduate Conference on Experimental Mechanics, University of Wisconsin, Madison, WI, April 26-27, 1985.

3. Suhling, J. C. and Jaeger, R. C., Kang, Y. L. and Cordes, R. A., “Optimized Piezoresistive Stress Sensor Design for (111) Silicon,” Presented at INTERpack ‘95, Lahaina, HI, March 26-30, 1995.

4. Lin, S. T., Han, B. T. and Suhling, J. C., “Finite Element and Moiré Interferometry Study of Surface Mount Chip Capacitor Reliability,” Presented at the 1996 ASME International Mechanical Engineering Congress and Exposition, Atlanta, GA, November 17-22, 1996.

5. Wilamowski, B. M., Lin, S. T., Suhling, J. C. and Jaeger, R. C., “Design of Optimized (111) Stress Test Chips,” Presented at the 1996 ASME International Mechanical Engineering Congress and Exposition, Atlanta, GA, November 17-22, 1996.

6. Zou, Y., Lin, S. T., Suhling, J. C. and Jaeger, R. C., “Measurement of Plastic Packaging Induced Die Stress,” Presented at the 1996 ASME International Mechanical Engineering Congress and Exposition, Atlanta, GA, November 17-22, 1996

7. Zou, Y., Suhling, J. C., Jaeger, R. C., and Ali, H., “Comparison of Stresses within Delaminated and Non-Delaminated Plastic Packages,” Presented at the 1997 ASME International Mechanical Engineering Congress and Exposition, Dallas, TX, November 16-21, 1997.

8. Jaeger, R. C. and Suhling, J. C., “Integrated Test Chips for Stress Measurement in Electronic Packages,” Presented at the Second Academic Conference on Electronic Packaging Research and Education, Georgia Institute of Technology, Atlanta, GA, March 18-20, 1998.

9. White, J. D., Suhling, J. C., Johnson, R. W., and Knight, R. W., “Reliability Of Surface Mount Solder Joints In Potted Automotive Engine Controllers,” Presented at InterPACK '99, Lahaina, HI, June 13-19, 1999.

10. Zou, Y., Suhling, J. C., Johnson, R. W. and Jaeger, R. C., “Reliability Testing of Chip on Board Assemblies Cured with Convection and Variable Frequency Microwave Testing,” Presented at the 1999 International Mechanical Engineering Congress and Exposition, Nashville, TN, November 14-19, 1999.

11. Suhling, J. C., and Jaeger, R. C., “Measurement of Stress Distributions in Silicon IC Chips Using Piezoresistive Sensors,” Presented at the ASTM Fall Meeting, Kansas City, MO, November 14-19, 1999.

12. Rahim, M. K., Suhling, J. C., and Jaeger, R. C., "Stress Test Chip Measurements in Chip Scale Packages," Presented at the 2000 ASME International Mechanical Engineering Congress and Exposition, Orlando, FL, November 5-10, 2000.

Exhibit 100200148

Exhibit 1002

Conference Presentations (Abstract Only) (Continued)

13. Suhling, J. C., and Jaeger, R. C., “Silicon Piezoresistive Stress Sensors and Their Application in Electronic Packaging,” Presented at the 14th US National Congress on Theoretical and Applied Mechanics, Blacksburg, VA, June 24-28, 2002.

14. Lall, P., Singh, N., Suhling, J., “Design Guidelines for Deployment of Area Array Packages in Harsh Environments,” Presented at the International Military & Aerospace/Avionics COTS Conference, Newton, MA, August 27-29, 2003.

15. Lall, P., Islam, N., Rahim, K., Suhling, J., Gale, S., “Prognosis and Health Monitoring of Electronics and MEMS Packaging,” Presented at the International Military & Aerospace Avionics COTS Conference, Seattle, WA, August 3-5, 2004.

16. Lall, P., Panchagade, D., Liu, Y., Johnson, W., Suhling, J., “Shock and Drop-Impact Reliability Prediction for Fine-Pitch BGAs and CSPs,” Presented at the International Military & Aerospace Avionics COTS Conference, Seattle, WA, August 3-5, 2004.

17. Ma, H., Suhling, J. C., Lall, P., and Bozack, M. J., “Aging of Lead Free Solder Mechanical Properties,” Presented at InterPACK ’05, San Francisco, CA, July 17-22, 2005.

18. Lall, P., Islam, N., Choudhary, P., Rahim, K., and Suhling, J., “Framework for Health Monitoring of Advanced Electronic Systems,” Presented at the International Military and Aerospace Avionics COTS Conference, Portsmouth, VA, August 2-4, 2005.

19. Lall, P, Panchagade, D., Choudhary, P., Gupte, S., and Suhling, J., “Development of Survivability-Envelopes for Electronic Components in Extreme Shock and Vibration Environments,” Presented at the International Military and Aerospace Avionics COTS Conference, Portsmouth, VA, August 2-4, 2005.

20. Ma, H., Suhling, J. C., Lall, P., and Bozack, M. J., “Evolution of Lead Free Solder Mechanical Properties During Isothermal Aging,” Presented at the 2005 ASME International Mechanical Engineering Congress and Exposition, Orlando, FL, November 5-11, 2005.

21. Zhang, Y., Ma, H., Suhling, J. C., Lall, P., and Bozack, M. J., “Mechanical Behavior of Mixed Formulation Solders,” Presented at InterPACK ‘07, Vancouver, British Columbia, Canada, July 8-12, 2007.

22. Tian, G., Lin, C., Suhling, J. C., and Lall, P., “Cure Profile Effects on the Mechanical Behavior and Reliability of Flip Chip on Laminate Assemblies,” Presented at InterPACK ‘07, Vancouver, British Columbia, Canada, July 8-12, 2007.

23. Zhang, Y., Ma, H., Suhling, J. C., Lall, P., and Bozack, M. J., “Stress-Strain Behavior of Mixed Formulation Solder Joints,” Presented at the 2007 International Mechanical Engineering Congress and Exposition, Seattle, WA, November 11-15, 2007

24. Ma, H., Suhling, J. C., Zhang, Y., Lall, P., and Bozack, M. J., “Aging Effects in SAC Lead Free Solder Joints,” Presented at the 2007 International Mechanical Engineering Congress and Exposition, Seattle, WA, November 11-15, 2007

Exhibit 100200149

Exhibit 1002

Conference Presentations (Abstract Only) (Continued)

25. Suhling, J. C., “Reliability Challenges for Automotive and Other Harsh Environment Electronics,” Automotive Science and Technology Keynote Presentation, Presented at the 2008 US-Korea Conference (UKC) on Science, Technology, and Entrepreneurship, San Diego, CA, August 14-17, 2008.

26. C-H, Cho, C. H., Hussain, S., Jaeger, R. C., and Suhling, J. C., “Impact of Piezoresistive Coefficient Uncertainty on Stress Measurement Using Multi Element Sensor Rosettes,” Presented at the 2008 IEEE International Sensors Conference, Lecce, Italy, October 26-29, 2008.

27. Zhang, Y., Cai, Z., Suhling, J. C., Lall, P., and Bozack, M. J., “Properties and Aging of Mixed Formulation Solders,” Presented at the 2008 ASME International Mechanical Engineering Congress and Exposition, Boston, MA, October 31-November 6, 2008.

28. Cai, Z., Zhang, Y., Suhling, J., Lall, P., “Creep and Aging Behaviors of SAC and SACX Alloys,” Presented at the 2009 ASME International Mechanical Engineering Congress and Exposition, Lake Buena Vista, FL, Nov 13-19, 2009.

29. Kurumaddali, K., Mustafa, M., Cai, Z., Suhling, J. C., Lall, P., Strickland, M., Blanche, J., “Solder and Underfill Stress-Strain Behavior at Extreme Low Temperatures,” Presented at the 2010 ASME International Mechanical Engineering Congress and Exposition (IMECE), Vancouver, Canada, November 14-18, 2010.

30. Roberts, J., Bhat, C., Suhling, J. C., Lall, P., Kirkman, S., Zhang, R., “Reliability of a CBGA Microprocessor Package Incorporating a Decoupling Capacitor Array,” Presented at the 2010 ASME International Mechanical Engineering Congress and Exposition (IMECE), Vancouver, Canada, November 14-18, 2010.

31. Motalab, M., Roberts, J. C., Suhling, J. C., Jaeger, R. C., and Lall, P., “Finite Element Modeling of the Buildup of Compressive Stresses in a Microprocessor Chip by Packaging and Heat Sink Clamping,” Presented at InterPACK 2011, Portland, OR, July 6-8, 2011.

32. Mustafa, M., Cai, Z., Suhling, J., Lall, P., “The Effects of Aging on the Cyclic Stress- Strain Behavior of Leadfree Solders,” Presented at the ASME International Congress and Exposition (IMECE), Paper IMECE2011-65179, Denver, CO, November 11-17, 2011.

Exhibit 100200150

Exhibit 1002

RESEARCH FUNDING

Contracts and Grants

1. Suhling, J. C., “Investigation of the Mechanical Behavior of Corrugated Fiberboard,” Auburn University Grant-In-Aid, 1/1/86 to 12/31/86, $3,000.

2. Suhling, J. C., “A Combined Analytical-Experimental Analysis of Cylindrically Deformed Paperboard Sheets,” Auburn University Grant-In-Aid, 6/1/86 to 8/31/88, $3,000.

3. Jang, B. Z., Suhling, J. C., Valaire, B. T. and Zee, R., “Optimization of Fracture Resistance in Composites,” Army Research Office, 10/1/86 to 9/30/89, $900,000.

4. Suhling, J. C., “Investigation on the Effects of Moisture Content on the Biaxial Mechanical Behavior of Paperboard,” USDA, 8/15/87 to 6/30/88, $3,500.

5. Suhling, J. C., “Mechanical Behavior of Paperboard,” PPREC, 10/1/87 to 9/30/89, $57,199.

6. Suhling, J. C., “Analysis of Paperboard Structures Using Nonlinear Finite Element Models,” PPREC/ASN, 4/1/88 to 3/31/89, $120,000.

7. Jaeger, R. C., Beaty, R. E., Suhling, J. C. and Johnson, R. W., “A Test Chip to Evaluate and Predict Reliability of Packaged Integrated Circuits,” Semiconductor Research Corporation, 1/1/88 to 12/31/90, $265,000.

8. Suhling, J. C., “Structural Analysis of Paperboard Containers,” PPREC/ASN, 7/1/89 to 6/30/90, $60,000.

9. Suhling, J. C., “Prediction of Residual Stresses and Curl in Layered Materials,” PPREC/ASN, 7/1/89 to 6/30/90, $36,000.

10. Suhling, J. C., “Travel Assistance Grant for Trip to the International Conference on Composite Materials,” Auburn University Grant-In-Aid, 3/1/89 to 12/31/89, $500.

11. Suhling, J. C., “Investigation on the Mechanical Behavior of Corrugated Board,” PPREC, 10/1/89 to 9/30/90, $12,000.

12. Suhling, J. C., “Analytical-Experimental Investigation on the Effects of Moisture on the Mechanical Response of Paperboard,” USDA, 4/1/90 to 9/30/93, $57,479.

13. Suhling, J. C., “Evaluation of the Shear Stress-Strain Behavior of Single-Wall and Laminated Papers,” Sonoco Products Company, 5/1/90 to 4/30/91, $32,112.

14. Suhling, J. C., “Modeling of the Embossing of Towel and Tissue Using the Finite Element Method,” James River Corporation, 8/1/90 to 9/30/93, $150,951.

15. Johnson, R. W., Suhling, J. C. and Knight, R. W., “High Temperature Electronics,” NASA, 12/1/90 to 11/30/93, $750,000.

16. Suhling, J. C., “Experimental Analysis of Paperboard Biaxial Strength,” USDA, 1/1/92 to 9/30/92, $7,225.

17. Jaeger, R. C. and Suhling, J. C., “Piezoresistive Stress Sensor Calibration and Design,” Sandia National Laboratories, 2/1/92 to 9/30/92, $49,871.

18. Madsen, N. H., Suhling, J. C., and Montgomery, R. D., “Development of a Dynamic in Vitro Knee Testing Device,” Hughston Sports Medicine Foundation, 6/1/92 to 12/31/95, $20,230.

19. Jaeger, R. C. and Suhling, J. C., “Piezoresistive Stress Sensor Calibration,” Texas Instruments, 6/16/92 to 9/30/92, $4,599.

Exhibit 100200151

Exhibit 1002

Contracts and Grants (Continued)

20. Suhling, J. C., “Analytical-Experimental Investigation on the Mechanical Response of Corrugated Paperboard Structures,” USDA, 8/1/92 to 12/31/94, $86,700.

21. Johnson, R. W., Knight, R. W. and Suhling, J. C., “Thermal and Stress Analysis of the Acustar Jeep/Truck Engine Controller,” Chrysler-Acustar Inc., 10/8/92 to 1/31/93, $30,599.

22. Jaeger, R. C. and Suhling, J. C., “Stress Sensor Calibration,” Sandia National Laboratories, 7/1/93 to 9/30/93, $10,087.

23. Jaeger, R. C. and Suhling, J. C., “High Accuracy Measurements of Stress in Packaged Integrated Circuits,” Semiconductor Research Corporation, 9/1/93 to 12/31/96, $569,382.

24. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Advanced Electronic Packaging,” NASA, Chrysler Electronics, and Rocketdyne; 11/1/93 to 10/31/96, $1,539,000.

25. Madsen, N. H., Suhling, J. C. and Goodling, J. S., “Biomechanics Graduate Student Fellowship,” Hughston Sports Medicine Foundation, 1/1/94 to 12/31/94, $15,000.

26. Suhling, J. C. and Beckett, R., “Acoustic Holography and Optical Image Processing Equipment Donation,” Contract DAAH01-88-C-0561, Army MICOM and Office of Naval Research, 5/1995, $106,400.

27. Suhling, J. C., “Finite Element Corroboration of Buckling Phenomena of Corrugated Fiberboard Structures,” USDA, 9/15/94 to 6/30/98, $42,000.

28. Suhling, J. C., Johnson, R. W. and Knight, R. W., “Reliability Modelling for Surface Mount Chip Capacitors,” Chrysler Corporation, 1/1/96 to 9/30/96, $49,728.

29. Jaeger, R. C., Goodling, J. S., Johnson, R. W., Nelson, V. P., Singh, A. D. and Suhling, J. C., “Acquisition of Packaging Research Equipment for the Alabama Microelectronics Science and Technology Center,” National Science Foundation, 10/1/95 to 9/30/97, $644,866.

30. Suhling, J. C. and Thakur, M., “Piezoresistive Sensor Development Using Organic Polymer Semiconductors,” Alabama DOE/EPSCoR, 6/1/96 to 9/30/96, $5,000.

31. Suhling, J. C., “Mechanical Behavior of Paper and Paperboard,” PPREC, 10/1/95 to 9/30/02, $117,000.

32. Johnson, R. W. and Suhling, J. C., “Simplified Flip-Chip Manufacture Using Multilayer Underfill Encapsulation,” DARPA, 10/1/96 to 3/31/97, $140,202.

33. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Commercial Development of Advanced Electronic Packaging,” NASA Lewis Research Center, Chrysler Electronics, Caterpillar, United Technologies; 11/1/96 to 10/31/99, $1,800,784.

34. Jaeger, R. C. and Suhling, J. C., “Innovative Stress Sensors for Stress Measurement in Packaged Integrated Circuits,” Semiconductor Research Corporation, 1/1/97 to 12/31/99, $472,061.

35. Johnson, R. W., Suhling, J. C., Knight, R. W. and Bozack, M., “NSF Industry/University Cooperative Center for Advanced Vehicle Electronics (CAVE),” National Science Foundation, 9/1/99 to 8/31/04, $350,000.

Exhibit 100200152

Exhibit 1002


36. Johnson, R. W., Suhling, J. C., Knight, R. W. and Bozack, M., “NSF Industry/University Cooperative Center for Advanced Vehicle Electronics (CAVE),” Industrial Membership Fees, 9/1/99 to 8/31/04, $2,875,450.

37. Suhling, J. C., “Equipment Grant for Purchase of a Microscale Testing Machine and Semiconductor Parameter Analyzer,” NASA, 6/1/99 to 5/31/00, $115,000.

38. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Chip Scale Packaging Reliability Study,” NASA, 3/1/00 to 1/31/02, $132,648.

39. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Lead Free Solders for Space Electronics,” NASA, 3/1/00 to 1/31/02, $123,035.

40. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Investigation on Ball Grid Array Thermal Performance and Mechanical Reliability,” NASA, 3/1/00 to 1/31/02, $175,962.

41. Jaeger, R. C., and Suhling, J. C., “Student Support for Stress Sensor Research,” Semiconductor Research Corporation, 1/1/00 to 12/31/00, $19,000.

42. Johnson, R. W., Suhling, J. C., Smith, A., Knight, R., Flowers, G., Tippur, H., Bozack, M., Chin, B., Gale, W., “In-Process Non-Destructive Analytical Equipment for Electronics Manufacturing Research,” COE Research Infrastructure Award, 10/1/2000 to 9/30/2002, $100,000.

43. Suhling, J. C., “Development of FEA Analytical Model for Predicting Solder Bump Stresses in Flip-Chip DCA Electronic Packages,” NASA and Boeing Corporation, 2/1/2001 to 1/31/2002, $28,600.

44. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Area Array Packaging,” NASA, 11/1/01 to 10/31/02, $221,229.

45. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Measurement of Thermal and Mechanical Properties of Packaging Materials,” NASA, 11/1/01 to 10/31/02, $220,614.

46. Suhling, J. C., US Army AMCOM Membership Fees in the Center for Advanced Vehicle Electronics (CAVE),” 10/1/2000 to 9/30/2004, $300,000.

47. Suhling, J. C., NASA Membership Fees in the Center for Advanced Vehicle Electronics (CAVE),” 10/1/2002 to 9/30/2004, $150,000.

48. Knight, R. W, Lall, P., Johnson, R. W., and Suhling, J. C., “Ultra Reliable Electronics,” NASA, 11/1/02 to 10/31/03, $177,555.

49. Johnson, R. W., Suhling, J. C. and Knight, R. W., “SiC Smart Power Electronics,” NASA, 11/1/02 to 10/31/03, $111,197.

50. Suhling, J. C., Johnson, R. W., and Knight, R. W., “Low Temperature Material Property Measurements,” NASA, 11/1/02 to 10/31/03, $152,259.

51. Johnson, R. W., and Suhling, J. C., “Flip Chip Attachment Process and Reliability,” Harris Corporation, 11/5/03 to 7/31/2003, $25,389.

52. Johnson, R. W., Suhling, J. C., and Gale, W. F., “Reliability Evaluation of Pb-Free Solder Alloys,” NASA, $65,000.

53. Smith, A. E., and Suhling, J. C., “Research Experiences for Teachers in the Center for Advanced Vehicle Electronics,” National Science Foundation, 7/1/03 to 6/30/04, $20,000.

Exhibit 100200153

Exhibit 1002


54. Smith, A. E., and Suhling, J. C., “Research Experiences for Undergraduates in the Center for Advanced Vehicle Electronics,” National Science Foundation, 7/1/03 to 6/30/04, $12,000.

55. Knight, R. W, Lall, P., Suhling, J. C., and Johnson, R. W., “Advanced Enclosures for Maintenance Free Electronics,” NASA, 11/1/03 to 10/31/04, $130,811.

56. Johnson, R. W., Suhling, J. C. and Knight, R. W., “Packaging of High Temperature SiC Electronics,” NASA, 11/1/03 to 10/31/04, $100,711.

57. Suhling, J. C., Johnson, R. W., and Knight, R. W., “Extreme Temperature Material Characterization,” NASA, 11/1/03 to 10/31/04, $117,664.

58. Smith, A. E., and Suhling, J. C., “Research Experience for Teachers in the Center for Advanced Vehicle Electronics,” National Science Foundation, 3/1/04 to 2/28/05, $20,000.

59. Bevly, D. M., and Suhling, J. C., “Faculty Mentoring Grant: Design, Control, and Application of MEMS Sensors in Harsh Environments,” Auburn University OVPR, 3/1/04 to 2/28/05, $7,000.

60. Suhling, J. C., Flowers, G. T., Evans, J. L., Bozack, M. J., and Lall, P., “Center for Advanced Vehicle Electronics - Five Year Renewal,” National Science Foundation, 9/1/04 to 8/31/09, $215,000.

61. Suhling, J. C., “Industrial Membership Fees in the NSF Center for Advanced Vehicle Electronics (CAVE),” 9/1/04 to 8/31/05, $503,000.

62. Suhling, J. C., “US Army AMCOM Membership Fees in the Center for Advanced Vehicle Electronics (CAVE),” 9/1/04 to 8/31/05, $75,000.

63. Suhling, J. C., “NASA Membership Fees in the Center for Advanced Vehicle Electronics (CAVE),” 9/1/04 to 8/31/05, $75,000.

64. Choe, S. Y., Fergus, J. W., Lall, P., and Suhling, J. C., “Research and Develop Advanced Sensors, Instrumentations and Controls to Substantially Improve Efficiency, Durability, Safety, and Cost of Fuel Cell Components and Systems,” Hyundai Motor Corporation, 8/1/04 to 7/31/05, $150,000.


66. Suhling, J. C., Knight, R. W., and Lall, P. “Development of a 3D Embedded Chip Electronic Module for Space Applications,” NASA, 11/1/04 to 10/31/05, $162,367.





Exhibit 100200154

Exhibit 1002


71. Suhling, J. C., and Lall, P., “A Unified Prognostics Approach for Vehicle Electronics using Physics-of-Failure Driven Sensor Fusion,” National Science Foundation, 10/1/05 to 9/30/07, $200,000.

72. Lall, P., and Suhling, J. C., “FPGA-BGA Solder Joint Prognostics Phase 1,” Naval Air Systems Command, Ridgetop Group, 5/15/2006 to 8/31/2006, $7,000.


74. Suhling, J. C., “Research Experiences for Undergraduates in the Center for Advanced Vehicle Electronics,” National Science Foundation, 9/1/06 to 8/31/07, $6,000.




78. Lall, P., and Suhling, J. C., “Embedded Packaging Technology,” NASA, 9/1/06 to 8/31/08, $40,000.

79. Lall, P., and Suhling, J. C., “Methodologies for Engine Prognostics,” DRS Test and Energy Management, 11/1/06 to 3/31/07, $85,000.

80. Suhling, J. C., “Stress Measurements in Plastic Ball Grid Array Components,” Freescale Semiconductor, 3/1/2007 to 2/28/2008, $39,000.

81. Lall, P., and Suhling, J. C., “FPGA-BGA Solder Joint Prognostics Phase 2,” Naval Air Systems Command, Ridgetop Group, 3/1/07 to 2/28/11, $240,000.

82. Suhling, J. C., “Mechanical Testing of BGA Underfills,” General Dynamics Corporation, 6/1/07 to 5/31/08, $17,849.

83. Suhling, J. C., “Analysis of Flip Chip Fluxes,” Henkel Loctite, 9/1/08 to 8/31/08, $15,700.



86. Suhling, J. C., “US Navy Membership Fees in the Center for Advanced Vehicle Electronics (CAVE),” 9/1/07 to 8/31/08, $75,000.


88. Suhling, J. C., and Lall, P., “Characterization and Modeling of Aging Solder Material Behavior in Harsh Environment Electronics,” National Science Foundation, 10/1/07 to 9/30/10, $150,000.


Exhibit 100200155

Exhibit 1002


90. Lall, P., Evans, J., Bozack, M., Flowers, G., Suhling, J., CAVE3 Industrial and Agency Memberships, NSF IUCRC, 9/1/2008 to 8/31/2009, $1,581,707.

91. Suhling, J. C., “Flip Chip and Underfills,” CAVE Research Project, 9/1/08 to 8/31/09, $100,000.

92. Bozack, M. J., and Suhling, J. C., “Lead Free Soldering,” CAVE Research Project, 9/1/08 to 8/31/09, $100,000.

93. Suhling, J. C., “Cryogenic Behavior of Solders,” NASA, 12/1/08 to 11/30/09, $21,000.


95. Suhling, J. C., “Flip Chip and Underfills,” CAVE Research Project, National Science Foundation and Center Industrial Members, $100,000, 9/1/09 to 8/31/10.


97. Suhling, J. C., “Effects of Aging on the Cyclic Stress-Strain Behavior and Hysteresis Loop Evolution of Lead Free Solders,” US Army, 9/1/09-8/31/11, $67,485.

98. Lall, P., Evans, J., Bozack, M., Flowers, G., Suhling, J., Phase-III: NSF Center for Advanced Vehicle and Extreme Environment Electronics, National Science Foundation, 1/1/2010-12/31/2014, $145,000.




102. Suhling, J. C., Jaeger, R. C., Wilamowski, B. M., “Characterization, Modeling, and Mitigation of the Impacts of Mechanical Stress on the Performance of Precision Analog Devices,” Semiconductor Research Corporation, 6/1/11 to 5/31/14, $420,000.

103. Lall, P., Evans, J., Bozack, M., Flowers, G., Suhling, J., CAVE3 Industrial Memberships, NSF IUCRC, 9/1/11 to 8/31/12, $1,541,886.





Exhibit 100200156

Exhibit 1002










116. Suhling, J. C., and Cremaschi, L., “Developing a High Performance Integrated Building Energy Systems and Technologies (HPI-BEST) Research Program at Auburn University,” Alabama Innovation Fund, $801,292, 1/1/2016 to 12/31/2017.

Exhibit 100200157

Exhibit 1002

PROFESSIONAL AND TECHNICAL SOCIETY ACTIVITIES

1. American Society of Mechanical Engineers (ASME) Member, 1985-Present Fellow, 2009-Present Faculty Advisor, Auburn University Student Section, 1987-2006

Electronic and Photonic Packaging Division (EPPD) Executive Board Member, 1998-2003 Secretary, 1998-2000 Treasurer, 2000-2001 Vice Chairman, 2001-2002 Chairman, 2002-2003 Advisory Board, 2004-Present Awards Chairman, 2012-2013

Experimental Mechanics Committee (AMD) Member, 1989-Present Secretary, 1992-1995 Chairman, 1995-1997

K16 Committee on Heat Transfer in Electronics (HTD-EPPD) Member, 2006-Present

Chattahoochee Local Section Member Interests Chairman, 1986-87 Executive Board, 1988-1993 Treasurer, 1989-1990

Symposium Organizer “Applications of Experimental Mechanics to Electronic Packaging” 1995 International Mechanical Engineering Congress and Exposition San Francisco, CA, November 12-17, 1995 Organized 5 Sessions with 20 Papers

Symposium Organizer “Symposium on Experimental Mechanics” 1996 International Mechanical Engineering Congress and Exposition Atlanta, GA, November 17-22, 1996 Organized 3 Sessions with 15 Papers

Session Organizer “Reliability of Surface Mount Packages” “Device and First Level Reliability Issues,” InterPACK ’97, Kohala, HI, June 15-19, 1997 Organized 2 Sessions with 12 Papers

Exhibit 100200158

Exhibit 1002

1. American Society of Mechanical Engineers (ASME) (Continued)

Symposium Organizer “Applications of Experimental Mechanics to Electronic Packaging - 1997” 1997 International Mechanical Engineering Congress and Exposition Dallas, TX, November 16-21, 1997 Organized 5 Sessions with 25 Papers

Session Organizer “Applications of Experimental Mechanics to Electronic Packaging” 1998 International Mechanical Engineering Congress and Exposition Anaheim, CA, November 15-20, 1998 Organized 1 Session with 6 Papers

Technical Track Chair “Modeling and Characterization” InterPACK ’99 Lahaina, HI, June 13-19, 1999 Organized 8 Sessions with 40 Papers

Session Organizer “Testing, NDT, and Product Decisions I” InterPACK ’01 Kauai, HI, June 8-13, 2001 Organized 1 Session with 5 Papers

Finance Chair InterPACK ’03 Lahaina, HI, June 6-11, 2003

Technical Track Chair “Reliability” InterPACK ’05 San Francisco, CA, July 17-22, 2005 Organized 8 Sessions with 40 Papers

Conference Technical Program Chair InterPACK ’07 Vancouver, CANADA, July 2007

- 12 Technical Tracks, 70 Sessions, and 275 Papers - 832 Total Attendees - Co-located with the ASME-JSME Thermal Engineering Conference

(AJTEC) and the 2007 ASME Summer Heat Transfer Conference (SHTC)

Exhibit 100200159

Exhibit 1002

1. American Society of Mechanical Engineers (ASME) (Continued)

Conference General Chair InterPACK ’09 San Francisco, CA, July, 19-23, 2009

- 12 Technical Tracks, 80 Sessions, and 390 Papers - 1050 Total Attendees - Co-located with the 2009 ASME Summer Heat Transfer Conference (SHTC) and the ASME 3rd International Conference on Energy Sustainability (ES2009)

Conference Honors and Awards Chair InterPACK ’11 Portland, OR, July 6-8, 2011

InterPACK Advisory Committee Member, 2009-Present

2. Institute of Electrical and Electronics Engineers (IEEE)

Member, 2000-Present Affiliate Member, 1992-2000 CPMT Society Member, 1992-Present

Conference Service ECTC Applied Reliability Committee, Member, 2003-Present ECTC Professional Development Course Committee, Co-Chair, 2006-Present Vice Program Chair, ITherm 2017 Conference

CPMT Society CPMT Society Board of Governors, Member, 2014-Present CPMT Society, Director of Membership Services, 2016-Present

3. Society for Experimental Mechanics (SEM) Member, 1981-Present Executive Board, Member, 2004-2006 Administrative Council, Member, 1987-1992

Membership Committee Vice-Chairman, 1987 Chairman, 1988-1990

Exhibit 100200160

Exhibit 1002

3. Society for Experimental Mechanics (SEM) (Continued)

Local Sections Committee Vice-Chairman, 1990-1991 Chairman, 1992

Electronic Packaging Division Member, 1994-Present Paper Review Committee, 1994-1996, 2000-2006 Chairman, 1999-2003

Optical Methods Division Member, 1986-Present Paper Review Committee, 1991-1994 Secretary, 1987-1990 Vice-Chairman, 1993-1995 Chairman, 1995-1997

Composite Materials Division Member, 1986-1992 Wood and Wood-Based Composites Subdivision, Member, 1995-Present Wood and Wood-Based Composites Subdivision, Secretary, 1995

Session Organizer “Optical Methods Applied to Electronic Packaging” 1995 SEM Spring Conference Grand Rapids, MI, June 11-14, 1995 Organized 1 Session with 5 Papers

General Chairman 4th Symposium on Experimental/Numerical Mechanics in Electronic Packaging, 9th International Congress on Experimental Mechanics, Orlando, FL, June 5-8, 2000 Organized 10 Sessions with 40 Papers

4. Technical Association of the Pulp and Paper Industry (TAPPI)

Member, 1982-Present

International Paper Physics Committee Member, 1990-Present Secretary, 1995-1997 Vice-Chairman, 1997-1999 Chairman, 1999-2001

Exhibit 100200161

Exhibit 1002

4. Technical Association of the Pulp and Paper Industry (TAPPI) (Continued)

Program Secretary 1999 International Paper Physics Conference San Diego, CA, September 26-30, 1999 Organized Four-Day Conference with 48 Papers.

Program Chairman 2000 International Paper Physics Conference Grenoble, France, September 11-15, 2000 Organized Four-Day Conference with 55 Papers.

General Chairman 2003 International Paper Physics Conference Victoria, British Columbia, Canada, September 7-12, 2003 Organized Five-Day Conference with 100 Papers

5. Surface Mount Technology Association (SMTA)

Member, 2003-Present Technical Committee, 2003-Present

6. International Microelectronics and Packaging Society (IMAPS)


7. British Society for Strain Measurement (BSSM)


8. American Society of Engineering Education (ASEE)


9. American Academy of Mechanics (AAM)


Exhibit 100200162

Exhibit 1002

OTHER PROFESSIONAL SERVICE

1. Journal Editorships Associate Editor, Experimental Mechanics, 2002-2005 Associate Editor, Journal of Electronic Packaging, 2014-Present

2. Journals for Which Papers have been Reviewed: Experimental Mechanics TAPPI Journal Journal of Pulp and Paper Science IEEE Transactions on Components and Packaging Technologies IEEE Transactions on Advanced Packaging IEEE Transactions on Electronic Packaging Manufacturing ASME Journal of Electronic Packaging ASME Journal of Engineering Materials and Technology ASME Journal of Applied Mechanics

3. Agencies for Which Proposals have been Reviewed: National Science Foundation USDA DOE/EPSCoR Australian Research Council Hong Kong Research Council

4. Regional Conference Organization

[a] Organized the 1991 Southeastern Graduate Student Conference on Experimental Mechanics held on March 22-23, 1991 at Auburn University (co-sponsored by SEM). The conference had 85 Attendees from 10 Universities.

[b] Co-Organized (with H. V. Tippur) the 1995 Southeastern Graduate Student Conference on Experimental Mechanics held on March 17-18, 1995 at Auburn University (co-sponsored by SEM). The conference had 55 Attendees from 7 Universities.

Exhibit 100200163

Exhibit 1002

UNIVERSITY SERVICE (Auburn University)

University 1. Academic Computing Committee [Member, 1992-1995] 2. AU Phi Beta Kappa Chapter [Charter Member, 2001-Present] 3. Bangladesh Student Organization [Advisor, 1996-2004] 4. Vandegrift Award Committee, Cooperative Education Program

[Member, 2002] 5. Ross Hall Renovation Committee [Member, 2001-2006] 6. SACS Administrative Services Committee [Member, 2001-2003] 7. Provost Search Committee [Member, 2003] 8. Competitive Research Grant Committee [Member, 2006-2009] 9. Administrator Review Committee [Chair, 2011-2013]

College of Engineering 1. Birdsong Award Selection Committee [Chairman, 1995] 2. ME Department Head Search Committee [Member, 1995] 3. Extension and Outreach Committee [Member, 1993-1994] 5. Computing Committee [Member, 1994-2000] 6. WWW Oversight Committee [Member, 1995-2000] 7. Engineering 2005 Facilities Planning Committee [Member, 1997-2000] 8. Information Technology Peak Committee [Member, 1998-2008] 9. Year 2000 Committee [Member, 1999-2000] 10. Dean of Engineering Search Committee [Member, 1999-2000] 11. Associate Dean for Research Search Committee [Member, 2001-2002] 12. NSF-MRI Proposal Review Committee [Member, 2001] 13. Dean of Engineering Search Committee [Member, 2011-2012]

Departmental (Mechanical Engineering) 1. Auburn University ASME Student Section [Advisor, 1987-2006] 2. Computer Committee [Member, 1986-1992] 3. Computer Committee [Chairman, 1993-2002] 4. Mechanics Group [Member, 1985-Present] 5. Mechanics Group [Chair, 2003-2008] 6. Undergraduate Curriculum Committee [Member, 1986-1990, 2003-2008] 7. Undergraduate Curriculum Committee [Chairman, 1991-1994] 8. Graduate Program Committee [Member, 1995-1996] 9. Undergraduate Mechanics of Materials Laboratory [Supervisor, 1987-Present] 10. Undergraduate Mechanical Testing Laboratory [Supervisor, 1987-Present] 11. Computational and Experimental Mechanics Research Laboratory [Supervisor,

1987-Present] 12. Pulp and Paper Specialization Student Advisor [1991-2005] 13. E-Day Committee [Chairman, 1985-1990] 14. E-Day Committee [Member, 1991-1992] 15. Centennial Committee [Member, 1986] 16. Space/Facilities Committee [Member, 1986-1990]

Exhibit 100200164

Exhibit 1002

Departmental (Mechanical Engineering) (Continued)

17. Resource Committee [Member, 1996-Present] 18. Miscellaneous Department Service: [a] Developed and Installed Current Networked PC Laboratory [b] Developed Departmental WWW Pages [c] Developed the Pulp and Paper Specialization in the Mechanical Engineering

Undergraduate Curriculum. Supervise the ME Pulp and Paper Scholarship Program.

Exhibit 100200165

Exhibit 1002

EXTENSION AND OUTREACH ACTIVITIES

Shortcourses Taught

1. Jaeger, R. C. and Suhling, J. C., “Design and Application of Silicon Piezoresistive Sensors in Electronic Packaging,” American Society of Mechanical Engineers (ASME) Short Course, Given during the InterPACK ’95 Conference, Lahaina, HI, March 26-30, 1995.

2. Suhling, J. C., “Electronic Packaging Stress Analysis,” NSF-CAVE Short Course, November 13, 2000.

3. Suhling, J. C., “BGA Reliability,” NSF-CAVE Short Course, October 24, 2001. 4. Suhling, J. C., and Jaeger, R. C., “Stress and Thermal Test Chips for Evaluation of

Electronic Packaging Reliability,” American Society of Mechanical Engineers (ASME) Short Course, Given during the InterPACK ’03 Conference, Lahaina, HI, July 6-11, 2003.

5. Suhling, J. C., “Stress and Thermal Test Chips for Evaluation of Electronic Packaging Reliability,” NSF-CAVE Short Course, October 30, 2003.

6. Suhling, J. C., “Stress and Thermal Test Chips for Evaluation of Electronic Packaging Reliability,” IEEE, Short Course, Given during the ITHERM 2004 Conference, Las Vegas, NV, June 1-4, 2004.

7. Suhling, J. C., “Structural Mechanics Issues in Electronic Packaging,” American Society of Mechanical Engineers (ASME) Short Course, Given during 2004 International Mechanical Engineering Congress and Exposition, Anaheim, CA, November 17, 2004.

8. Suhling, J. C., and Jaeger, R. C., “Stress and Thermal Test Chips for Evaluation of Electronic Packaging Reliability,” American Society of Mechanical Engineers (ASME) Short Course, Given during the InterPACK ’05 Conference, San Francisco, CA, July 17-22, 2005.

9. Suhling, J. C., “Stress and Thermal Test Chips for Evaluation of Electronic Packaging Reliability,” IEEE, Short Course, Given during the ITHERM 2006 Conference, San Diego, CA, May 30-June 2, 2006.

10. Suhling, J. C., “Applications of Experimental Mechanics to Electronic Packaging,” Given during the InterPACK ’08 Conference, Vancouver, Canada, July 8-12, 2007.

11. Suhling, J. C., “Applications of Experimental Mechanics to Electronic Packaging,” Given during the EuroSimE 2009 Conference, Delft, The Netherlands, April 26-29, 2009.

Video Based Outreach Courses Taught (College of Engineering Graduate Outreach Program)

1. ME 633 - Advanced Experimental Stress Analysis, Winter 1989, 1 Student. 2. ME 636 - Mechanics of Composite Materials, Fall 1989, 5 Students. 3. ME 633 - Advanced Experimental Stress Analysis, Winter 1990, 4 Students. 4. ME 543 - Photoelastic Stress and Strain Analysis, Spring 1990, 6 Students. 5. ME 632 - Theory of Elasticity II, Spring 1990, 3 Students.

Exhibit 100200166

Exhibit 1002

Video Based Outreach Courses Taught (Continued)

6. ME 636 - Mechanics of Composite Materials, Fall 1990, 2 Students. 7. ME 637 - Theory of Plates, Winter 1991, 2 Students. 8. ME 639 - Variational Mechanics, Spring 1991, 8 Students. 9. ME 533 - Experimental Stress Analysis, Fall 1991, 6 Students. 10. ME 632 - Theory of Elasticity II, Winter 1992, 4 Students. 11. ME 636 - Mechanics of Composite Materials, Spring 1992, 4 Students. 12. ME 534 - Photoelastic Stress and Strain Analysis, Fall 1992, 1 Student. 13. ME 637 - Theory of Plates, Winter 1993, 5 Students. 14. ME 636 - Mechanics of Composite Materials, Spring 1993, 4 Students. 15. ME 533 - Experimental Stress Analysis, Fall 1993, 2 Students. 16. ME 632 - Theory of Elasticity II, Winter 1994, 2 Students. 17. ME 636 - Mechanics of Composite Materials, Spring 1994, 5 Students. 18. ME 534 - Photoelastic Stress and Strain Analysis, Winter 1995, 1 Student. 19. ME 637 - Theory of Plates, Winter 1995, 4 Students. 20. ME 636 - Mechanics of Composite Materials, Spring 1995, 2 Students. 21. ME 533 - Experimental Stress Analysis, Fall 1995, 3 Students. 22. ME 534 - Photoelastic Stress and Strain Analysis, Winter 1996, 1 Student. 23. ME 632 - Theory of Elasticity II, Winter 1996, 2 Students. 24. ME 636 - Mechanics of Composite Materials, Fall 1996, 6 Students. 25. ME 639 - Variational Mechanics, Winter 1997, 3 Students. 26. ME 637 - Theory of Plates, Spring 1997, 2 Students. 27. ME 636 - Mechanics of Composite Materials, Spring 1998, 1 Student. 28. ME 632 - Theory of Elasticity II, Winter 2000, 1 Student. 29. ME 636 - Mechanics of Composite Materials, Spring 2000, 3 Students. 30. MECH 7330 - Experimental Mechanics, Fall 2000, 1 Student. 31. MECH 6310 - Mechanics of Electronic Packaging, Spring 2001, 1 Student 32. MECH 7370 - Theory of Plates and Shells, Fall 2001, 2 Students 33. MECH 6310 - Mechanics of Electronic Packaging, Spring 2003, 1 Student 34. MECH 7340 - Inelastic Stress Analysis, Spring 2004, 1 Student 35. MECH 7360 - Mechanics of Composite Materials, Fall 2004, 4 Students 36. MECH 6310 - Mechanics of Electronic Packaging, Spring 2007, 1 Student 37. MECH 7340 - Inelastic Stress Analysis, Spring 2008, 1 Student 38. MECH 7360 - Mechanics of Composite Materials, Fall 2008, 4 Students 39. MECH 7330 - Experimental Mechanics, Fall 2009, 4 Students

Scientific Consulting and Technical Assistance to Local/State/National Industries

1. Sonoco Products Company 2. Samsung Electronics 3. Reliance COMMTEC 4. Lummus Industries 5. Continental Eagle 6. Palmetto Hammock Company

Exhibit 100200167

Exhibit 1002

Scientific Consulting and Technical Assistance to Local/State/National Industries (Continued)

7. Valmet Corporation 8. Amkor 9. LSI Logic 10. Solo Cup 11. Knox Kershaw, Inc. 12. Boeing 13. Henkel/Loctite 14. Cookson 15. Raytheon 16. National Semiconductor 17. Advanced Semiconductor Engineering (ASE) 18. Freescale Semiconductor 19. Qualcomm 20. ST Microelectronics 21. ChipMOS 22. Medtronic 23. SanDisk Corporation 24. Microsoft Corporation 25. SiO2 Medical

Other International Activities

1. Technical presentations at international conferences and foreign university seminars have been presented in Canada, China (PRC), China (ROC/Taiwan), Denmark, England, France, Germany, India, Japan, Korea, The Netherlands, New Zealand, Romania, Scotland, Sweden, and Switzerland.

2. Nine lectures (out of a total of 27) were presented as a part of a team-taught graduate course titled “Paper Mechanics - Important Research Issues” given at the Royal Institute of Technology - KTH, Stockholm, Sweden, May 4-7, 1998.

3. Nine lectures (out of a total of 24) were presented as a part of a team-taught graduate course titled “Engineering Mechanics of Paper” given at the Royal Institute of Technology - KTH, Stockholm, Sweden, May 14-18, 2001.

Exhibit 100200168

united states patent and trademark office before the … · 2017-05-25 · continental automotive,...

Documents