unit2_mos scaling and packaging

7/23/2019 Unit2_MOS Scaling and Packaging

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VLSI Technology and Applications



Constant Field ScalingConstant Voltage Scaling

Short Channel Effects

Narrow Channel effects

Limits of Small Device geometry

Device ac!aging

"#SFET Scaling



"#SFET ScalingFor high density chips: Size of MOSFET as small as possible.

Scaling$ Reduction in device dimensions operational

characteristics !ill be same".

#hysical limits restrict the e$tent of scaling.

Scaling Factor% S&'



%& Constant Field Scaling$ (ttempt to preserve the magnitude

of internal electric field.

Scale all potential proportionallyScaling: )% *% To$% $ +% ,ds% ,gs all divide by S

-oping: (% - multiplied by S

Significant reduction in po!er dissipation: #/S0

1g: Scaled by S2 1harging and -ischarging improved

Reduction in various parasitic capacitance

1FS: not practical in some applications:

eg. #eripheral and interface circuitry may re3uire certain voltage level

for all 4/# 5 O/# devices.

Types of Scaling

%& Constant Field Scaling

'& Constant Voltage Scaling



%& Constant Voltage Scaling$ (ll dimensions reduces by factor

S% but terminal voltages 6ept constant.

-oing density increased by S0 in order to preserve charge field

relations.

Scaling: )% *% To$% $ +% all divide by S

Terminal voltages constant: ,ds% ,gs Remain same"

-oping: (% - multiplied by S0

(s voltage constant% po!er dissipation increased



Short Channel Effects"o(ility red)ction

Vth red)ction



Vth *ed)ction



7

-48): (s ,ds increases% current starts flo!ing from 9S to

9- !ithout applying ,gs.

Sub threshold )ea6age 1urrent: -ue to ,th reduction

Short Channel Effects



Narrow Channel Effects

* of the order of $dm 4;, characteristics diff. from <1(

1ause of discrepancy: reduction in To$ and Fringe charge



+ot Electron Effect

(t high ,ds% at !hich lateral electric field accelerate the channel carriers



''

#hysical )imits and Effects

To$ Reduction: -ue to physical limit.-ifficult to process a very thin layer.

8rea6 do!n field effect

#unch Through: For larger ,ds% depletion region of 9- can

e$tend farther to!ard 9S and the t!o depletion regionscan eventually merge.

4d in crease sharply

-evice damage permanently



'0

1hip #ac6aging



'=

ac!aging

> 8ringing signals 5 supply !ires 4/O of silicon die.

> Remove heat generated by circuit.

> #rovide mechanical support.

> #rotect die against environmental conditions such as moisture.



'?

Need of ac!aging

> Many high performance ,)S4 chips fail after pac6aging.

> )ength of !ire b/! the chip and pac6age determine the

inductive voltage drop in the o/p circuit.

> ( good pac6age should provide lo! thermal resistance.

> 1hoice of proper pac6aging technology is critical to the success

of chip development.

Important ac!aging Concerns are$

> #revent the penetration of moisture.

> Thermal conductivity 5 thermal e$pansion coefficient.

> #in density

> #arasitic inductances and capacitances.

> @;partials protection.



'A

ac!aging Important Factors

> Electrical$ )o! #arasitic capacitance% inductance

and resistance.

> "echanical$ Reliable and robust

> Thermal$ Efficient heat removal> Economical$ 1heap

1ost of heat sin6% li3uid cooling hard!are% heat pipes and fan.



'B

ac!aging INs Co)nt

> 4ncreasing comple$ity of 41 on single die also translates into aneed for more 4/O pins.

in Co)nt$ ,y E& *ent

Rents Rule: # C D $ <8

#Cno. of pins

DCaverage no. of 4/O per gate

<Cno. of gates

8CRent e$ponent .' to ."

,alue of 8 depends on application area% architecture andorganization of the circuit



'

ac!aging Classifications

> According to soldering methods

> According to material )sed



'7


> According to soldering methods

'. Trough Gole Mounting: Re3uire precise hole be drilled in #18% !hich

is not cost effective. 4ne$pensive soldering process.

0. Surface Mount: The pac6age pins can be directly soldered on the

#18. SMT more cost 5 space effective. More e$pensive soldering

e3uipment re3uired.

(a) Through-Hole Mounting (b) Surface Mount



'H


> According to material )sed

%& lastic pac!aging$ -ominating material for 41

pac6aging. )o! cost but permeable to environmentalmoisture. Geat dissipate ' ! to 0 !. 1hip dissipating over0 ! re3uires special heat sin6 attachments.

'& Ceramic ac!aging$ Gigh performance% po!erdissipation% relatively high cost.



0

IC ac!aging Types

> -ual;4n;)ine pac6age -4#"

> #in <rid (rray #<(" pac6age

> 1hip 1arrier pac6age 11#"

> Multiple chip module



0'

IC ac!aging Types

> D)al-In-Line pac!age .DI/$ Through Gole Mounting

#eriphery pins".

Adv&$ )o! cost

Disadv&$Gigh interconnect inductance% !hich leads to significant noise

problem in high fre3uency application.

Ma$imum pin count limited to B?.



00

IC ac!aging Types

> in 0rid Array .0A/ ac!age$ )eads on entire bottom

surface instead of only on periphery.

#<( pac6age re3uire large #18 area and pac6age cost is higher

than -4#.

#<( can have large pin count over ? pins are possible".

(dv.: #<( has less parasitic capacitance and inductance than -4#.

-isadv.: *ea6en board% because of holes on !hole body.



0=

IC ac!aging Types

> Chip Carrier pac!age .CC/ SMT Surface Mounted

Technology" pac6age

)eadless chip carrier: mounted directly on #18% high pin

count.

)eaded chip carrier:



0?

Multiple;1hip Modules

> ,ery high performance% multiple chips are assembled on a commonsubstrate contained a single pac6age.

(dv.: Small system size% reduced pac6age lead count% faster operation aschips placed very close.



0A

Interconnect Levels of pac!aging

> Chip to S)(strate

> S)(strate to Leads or ins



0B

8onding Techni3ues

Lead Frame

Substrate

Die

Pad

1ire ,onding

> *ires must be attached serially% one after the other. This leads tolonger manufacturing times !ith increasing pin count.

> )arge pin count ma6es more comple$ity.

> 4nferior electrical properties such as individual inductance.



0

Tape;(utomated 8onding T(8"

> e! Techni3ue

> -ie is attached to a metal lead frame that is printed on a polymer film.

> (dv.: (utomatic process% connections made simultaneously% eliminate long

!ires%



07

#ac6age Types

-ie

-4#

#<( Small

outline 41

Iuad flat

pac6

#lastic

)ead 1hip

1arrier

)eadless

1hip

1arrier



0H



Layo)t Design *)les .sample set/

*)le n)m(er Description 2-*)le

R' Minimum active area !idth = 2

R0 Minimum active area spacing = 2

R= Minimum poly !idth 0 2

R? Minimum poly spacing 0 2

RA Minimum gate e$tension of poly over active 0 2

RB Minimum poly;active edge spacing ' 2

poly outside active area"

R Minimum poly;active edge spacing = 2

poly inside active area"

R7 Minimum metal !idth = 2RH Minimum metal spacing = 2

R' #oly contact size 0 2

R'' Minimum poly contact spacing 0 2



*)le n)m(er Description 2 -*)le

R'0 Minimum poly contact to poly edge spacing ' 2

R'= Minimum poly contact to metal edge spacing ' 2

R'? Minimum poly contact to active edge spacing = 2

R'A (ctive contact size 0 2R'B Minimum active contact spacing 0 2on the same active region"

R' Minimum active contact to active edge spacing ' 2

R'7 Minimum active contact to metal edge spacing ' 2

R'H Minimum active contact to poly edge spacing = 2

R0 Minimum active contact spacing B 2on different active regions"

Layo)t Design *)les .sample set/



D i * l



Layo)t Design *)les

L t D i * l



Layo)t Design *)les



Layo)t ,asics

Flo! of -ata 8et!een the -esign Gouse and the Foundry



T!o Types of design Rules: Resolution and (lignment



(lternative )ayout of a Minimum Transistor



MOS )ayout and Schematic for S#41E Modeling



MOS4S )ayout -esign Rules



-esign Flo! for #roduction

of a Mas6 )ayout

- i Fl f # d ti



-esign Flo! for #roduction

of a Mas6 )ayout

-esign Rules *hich -etermines the -imensions of a



-esign Rules *hich -etermines the -imensions of a

Minimum;Size Transistor

-esign Rules *hich -eterminene the Separation b/! the nMOS 5 pMOS



-esign Rules *hich -eterminene the Separation b/! the nMOS 5 pMOS

transistor of the 1MOS 4nverter



1omplete )ayout of the 1MOS 4nverter



Fabrication and )ayout Slide A=

Simplified -esign Rules

> 1onservative rules to get you started



Fabrication and )ayout Slide A?

4nverter )ayout

> Transistor dimensions specified as *idth /

)ength

J Minimum size is ?λ / 0λ, sometimes called '

unit

J For .B µm process% *C'.0 µm% )C.B µm

unit2_mos scaling and packaging

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