unit - ii · stld unit ii 5 analysis procedure to obtain the output boolean functions from a logic...

UNIT - IIMinimization and Design of

Combinational Circuits

P.VIDYA SAGAR ( ASSOCIATE PROFESSOR)

VIDYA SAGAR POTHARAJU , Department of Electronics and Communication Engineering, VBIT

STLD UNIT II

Minimization and Design of Combinational Circuits: Introduction, The

Minimization of switching function using theorem, The Karnaugh Map

Method-Up to Five Variable Maps, Don’t Care Map Entries, Tabular

Method.

Design of Combinational Logic: Adders, Subtractors, comparators,

Multiplexers, Demultiplexers, Decoders, Encoders and Code converters,

Hazards and Hazard Free Relations.

UNIT - II

2019/2/172


STLD UNIT IICombinational Circuits

It consists of input variables, logic gates and output variables.

Output is function of input only

i.e. no feedback

When input changes, output changes (after a delay)

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•••

•••

n inputs m outputsCombinational

Circuits

3


STLD UNIT IICombinational Circuits

Analysis

Given a circuit, find out its function

Function may be expressed as:

Boolean function

Truth table

Design

Given a desired function, determine its circuit

Function may be expressed as:

Boolean function

Truth table

2019/2/17

?

?

?

C

BA

C

BA

BA

CA

CB

F1

F2

4


STLD UNIT II

5

Analysis procedure

To obtain the output Boolean functions from a logic diagram, proceed as follows:

1.Label all gate outputs that are a function of input variables with arbitrary symbols.

Determine the Boolean functions for each gate output.

2.Label the gates that are a function of input variables and previously labeled gates with

other arbitrary symbols. Find the Boolean functions for these gates.

3.Repeat the process outlined in step 2 until the outputs of the circuit are obtained.

4.By repeated substitution of previously defined functions, obtain the output Boolean

functions in terms of input variables.

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STLD UNIT IIAnalysis Procedure

Boolean Expression Approach

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F1=T2+T3= AB'C'+A'BC'+A'B'C+ABC

F2=AB+AC+BC

C

BA

C

BA

BA

CA

CB

F1

F2

T2=ABCT1=A+B+C

F2=AB+AC+BC

F’2=(A’+B’)(A’+C’)(B’+C’)

T3=AB'C'+A'BC'+A'B'C

6


STLD UNIT II

C

BA

C

BA

BA

CA

CB

F1

F2

Analysis Procedure

We can obtain the truth table directly from the logic diagram

Truth Table Approach

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A B C F1 F2

0 0 0= 0

= 0

= 0

= 0

= 0

= 0

= 0

= 0

= 0

= 0

= 0

= 0

T2 = 0

T1 = 0

0

0

0

F2 = 0

F’2 = 1T3 = 0

0 0 0

7


STLD UNIT IIFull Adder Circuit

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STLD UNIT II

C

BA

C

BA

BA

CA

CB

F1

F2

Analysis Procedure


2019/2/17

= 0

= 0

= 1

= 0

= 0

= 1

= 0

= 0

= 0

= 1

= 0

= 1

0

1

0

0

0

0

1

1

1

A B C F1 F2

0 0 0 0 0

0 0 1 1 0

9


STLD UNIT II

C

BA

C

BA

BA

CA

CB

F1

F2

Analysis Procedure


2019/2/17

= 0

= 1

= 0

= 0

= 1

= 0

= 0

= 1

= 0

= 0

= 1

= 0

0

1

0

0

0

0

1

1

1

A B C F1 F2

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

10


STLD UNIT II

C

BA

C

BA

BA

CA

CB

F1

F2

Analysis Procedure


2019/2/17

= 0

= 1

= 1

= 0

= 1

= 1

= 0

= 1

= 0

= 1

= 1

= 1

0

1

0

0

1

1

0

0

0

A B C F1 F2

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

11


STLD UNIT II

C

BA

C

BA

BA

CA

CB

F1

F2

Analysis Procedure


2019/2/17

= 1

= 1

= 1

= 1

= 1

= 1

= 1

= 1

= 1

= 1

= 1

= 1

1

1

1

1

1

1

0

0

1

A B C F1 F2

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

B

0 1 0 1

A 1 0 1 0

C

B

0 0 1 0

A 0 1 1 1

C

F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC

12


STLD UNIT IIDesign Procedure

Given a problem statement:

Determine the number of inputs and outputs

Derive the truth table

Simplify the Boolean expression for each output

Produce the required circuit

Example:

Design a circuit to convert a “BCD” code to “Excess -3” code

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4-bits

0-9 values 4-bits

Value+3

?

13



BCD-to-Excess 3 Converter

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A B C D w x y z

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

C

1 1 1B

Ax x x x

1 1 x x

D

C

1 1 1

1B

Ax x x x

1 x x

D

C

1 1

1 1B

Ax x x x

1 x x

D

C

1 1

1 1B

Ax x x x

1 x x

D

w = A+BC+BD x = B’C+B’D+BC’D’

y = C’D’+CD z = D’

14


STLD UNIT II

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BCD-to-Excess 3 Converter

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w

x

D

C

z

y

B

A

w = A + B(C+D)

x = B’(C+D) + B(C+D)’

y = (C+D)’ + CD

z = D’

A B C D w x y z

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x

x x x x x x x x16


STLD UNIT IISeven-Segment Decoder (digital clock)

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a

b

c

g

e

d

f

?

w

x

y

z

abcdefg

w x y z a b c d e f g

0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 1 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 1 0 1 1

1 0 1 0 x x x x x x x

1 0 1 1 x x x x x x x

1 1 0 0 x x x x x x x

1 1 0 1 x x x x x x x

1 1 1 0 x x x x x x x

1 1 1 1 x x x x x x x

y

1 1 1

1 1 1x

wx x x x

1 1 x x

z

BCD code

a = w + y + xz + x’z’ b = . . .c = . . .

d = . . .17


STLD UNIT IIBinary Adder

Half Adder

Adds 1-bit plus 1-bit

Produces Sum and Carry

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HAx

y

S

C

x y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

x

+ y

───

C S

x

y

S

C

18



Full Adder

Adds 1-bit plus 1-bit plus 1-bit

Produces Sum and Carry

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x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

x

+ y

+ z

───

C S

FAxyz

S

C

y

0 1 0 1

x 1 0 1 0

z

y

0 0 1 0

x 0 1 1 1

z

S = xy'z'+x'yz'+x'y'z+xyz = x y z

C = xy + xz + yz

19



Full Adder

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x

y

z

S

C

xy

xz

yz

xyzxyzxyzxyz

xyz

x

y

z

xy

xz

yz

S

C

S = xy'z'+x'yz'+x'y'z+xyz = x y z

C = xy + xz + yz

Implementation of full adder in sum of products form

20



Implementation of Full Adder with two half adder and an OR gate.

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x

y

z

S

C

HAxy

z

HAS

C

21



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c3 c2 c1 .

+ x3 x2 x1 x0

+ y3 y2 y1 y0

────────

Cy S3 S2 S1 S0

FA

x3 x2 x1 x0

FAFAFA

y3 y2 y1 y0

S3 S2 S1 S0

C4 C3 C2 C1

0

Binary Adder

x3x2x1x0 y3y2y1y0

S3S2S1S0

C0C4

Carry

Propagate

Addition

22


STLD UNIT II

Subscript i 3 2 1 0

Input carry 0 1 1 0 Ci

1 0 1 1 xi

0 0 1 1 yi

Sum 1 1 1 0 Si

Output carry 0 0 1 1 Ci+1

2019/2/1723

VIDYA SAGAR POTHARAJU , Department of Electronics and Communication Engineering, VBIT 2019/2/17

Carry propagation

When the correct outputs are available

The critical path counts :

(A0, B0, C0) → C1 → C2 → C3 → (C4, S3)

When 4-bits full-adder → 8 gate levels (n-bits: 2n gate

levels)

Figure 4.10 Full Adder with P and G Shown

24


Binary Adders (Parallel)

Reduce the carry propagation delay

Employ faster gates

Look-ahead carry (more complex mechanism, yet

faster)

Carry propagate: Pi = AiBi

Carry generate: Gi = AiBi

Sum: Si = PiCi

Carry: Ci+1 = Gi + PiCi

C0 = Input carry

C1 = G0+P0C0

C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+P1P0C0

C3 = G2+P2C2 = G2+P2G1+P2P1G0+ P2P1P0C0

25


Carry Look-ahead Adder (1/2) Logic diagram

Fig. 4.11 Logic Diagram of Carry Look-ahead Generator

26


Carry Look-ahead Adder (2/2)

4-bit carry-look ahead adder

Propagation delay of C3, C2 and C1

are equal.

Fig. 4.12 4-Bit Adder with Carry Look-ahead

27


STLD UNIT IIBinary Subtractor

Use 2’s complement with binary adder

x – y = x + (-y) = x + y’ + 1

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Binary Adder

A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy 1

x3 x2 x1 x0 y3 y2 y1 y0

F3 F2 F1 F0

28


STLD UNIT IIBinary Adder/Subtractor

M: Control Signal (Mode)

M = 0 F = x + y

M = 1 F = x – y

F = x + y’+ 1

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Binary Adder

A3 A2 A1 A0 B3 B2 B1 B0

S3 S2 S1 S0

CiCy

Mx3 x2 x1 x0 y3 y2 y1 y0

F3 F2 F1 F0

y 0 = yy 1 = y'

29


STLD UNIT IIOverflow Discussion

Overflow

The storage is limited.

Add two positive numbers and obtain a negative number

number Add two negative numbers and obtaina positive

V = 0,no overflow;

V = 1, overflow

Example:

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STLD UNIT IIBCD Adder

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4-bits plus 4-bits

Operands : 0 to 9

This is called BCD adder. In order to add two decimal digits with a

possible carry-in of 1, then the maximum sum is 19. The following

table shows the sum when performed in binary and compared to the

sum when performed in BCD. In both cases five outputs are needed.

+ x3 x2 x1 x0

+ y3 y2 y1 y0

────────

Cy S3 S2 S1 S0

31


STLD UNIT II

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STLD UNIT II

From the table, when the sum is greater than 9, a correction is needed. The correction is

adding 6 to the binary sum. The BCD adder will then consist of the 4-bit binary adder. A

second 4-bit binary adder is needed to add 6 to the sum when it is greater than 9.

01010 + 0110 = 10000

The required logic circuit needed to detect if correction is needed can be obtained as follows:

C = K + Z8Z4 +Z8Z2

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STLD UNIT IIBCD Adder

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STLD UNIT IIBinary Multiplier

To multiply two 2-bit binary numbers B1 B0 and A1 A0, we may use half adders & AND gates.

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STLD UNIT II

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STLD UNIT II

For J multiplier bits and K multiplicand bits, we need (J x K) AND gates and (J – 1) K-bit

adders to produce a product of J + K bits.

In the previous example, K = 4, J = 3, so we need 12 AND gates and 2 four-bit adders to

produce a product of seven bits.

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STLD UNIT IIMagnitude Comparator

Compare 4-bit number to 4-bit number

3 Outputs: < , = , >

Expandable to more number of bits

0010, 1000 (Using XNOR Gates for equality)

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Magnitude

Comparator

A3A2A1A0 B3B2B1B0

A<B A=B A>B

33333 BABAx

22222 BABAx

11111 BABAx

00000 BABAx

0123)( xxxxBA

00123112322333)( BAxxxBAxxBAxBABA

00123112322333)( BAxxxBAxxBAxBABA

38


STLD UNIT IIMagnitude Comparator

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STLD UNIT IIDecoders

Is a combinational circuit that converts binary information from n input lines to a maximum of

2n unique output lines :

Extract “Information” from the code

n-to-m line decoder ( n inputs, m<= 2n

output)

Binary Decoder

Example: 2-bit Binary Number

2019/2/17

Binary

Decoder

x1

x0

Only one

lamp will

turn on

0

0

1

0

0

0

40



2-to-4 Line Decoder

2019/2/17

I1 I0 Y0 Y1 Y2 Y3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

Bin

ary

Dec

od

erI1

I0

Y0

Y1

Y2

Y3

I1

I0

Y3

Y2

Y1

Y0

013 IIY 012 IIY

011 IIY 010 IIY

41



3-to-8 Line Decoder (Binary to Octal conversion)

2019/2/17

Bin

ary

Dec

od

erI2

I1

I0

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

I2

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

I1

012 III

012 III

012 III

012 III

012 III

012 III

012 III

012 III

42


STLD UNIT II

2019/2/1743



“Enable” Control

2019/2/17

Bin

ary

Dec

od

erI1

I0

E

Y0

Y1

Y2

Y3

E I1 I0 Y0 Y1 Y2 Y3

0 x x 0 0 0 0

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

EI0

Y3

Y2

Y1

Y0

I1

44


STLD UNIT II4 x16 decoder constructed with two 3 x 8 decoders

2019/2/1745



Expansion

2019/2/17

E I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 1 0 0 0 0 0 0 1 0 0

0 1 1 0 0 0 0 1 0 0 0

1 0 0 0 0 0 1 0 0 0 0

1 0 1 0 0 1 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0

1 1 1 1 0 0 0 0 0 0 0

I2 I1 I0

Bin

arD

Dec

od

erI0

I1

E

D3

D2

1

D0

D7

D6

D5

D4

D3

D2

D1

D0Bin

ary

Dec

od

erI0

I1

E

D3

D2

D1

D0

3 x8 decoder constructed with two 2 x 4 decoders

46



Active-High / Active-Low

2019/2/17

I1 I0 Y0 Y1 Y2 Y3

0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

I1 I0 Y0 Y1 Y2 Y3

0 0 0 1 1 1

0 1 1 0 1 1

1 0 1 1 0 1

1 1 1 1 1 0

Bin

ary

Dec

od

erI1

I0

Y0

Y1

Y2

Y3

I1

I0

Y3

Y2

Y1

Y0

Bin

ary

Dec

od

erI1

I0

Y0

Y1

Y2

Y3

47


STLD UNIT IIImplementation Using Decoders

Each output is a minterm

All minterms are produced

Sum the required minterms

Example: Full Adder

S(x, y, z) = ∑(1, 2, 4, 7)

C(x, y, z) = ∑(3, 5, 6, 7)

2019/2/17

x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

48


STLD UNIT II

A function with a long list of minterms requires an OR gate with a large number of inputs.

If the number of minterms in the function is greater than 2n/2, then F’ can be expressed with

fewer minterms.

So we use a NOR gate to sum the minterms of F’.

The output of NOR gate complements this sum and generates the normal output F.

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STLD UNIT IIImplementation Using Decoders with NAND gates

2019/2/17

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

BinaryDecoder

x

y

z

S C

50


STLD UNIT IIEncoders

Encoder is a digital circuit that performs the inverse operation of a decoder Generates a

unique binary code from several input lines.

Generally encoders produce2-bit, 3-bit or 4-bit code. n bit encoder has 2n input lines

Put “Information” into code (it generates the binary code corresponding to the input value).

Binary Encoder

Example: 4-to-2 Binary Encoder

2019/2/17

x0 x1 x2 x3 y1 y0

1 0 0 0 0 0

0 1 0 0 0 1

0 0 1 0 1 0

0 0 0 1 1 1

Binary

Encoder

y1

y0

x0

x1

x2

x3

Only one

switch

should be

activated

at a time

51


STLD UNIT IIEncoders

Octal-to-Binary Encoder (8-to-3)

2019/2/17

I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Bin

ary

En

cod

er Y2

Y1

Y0

I7

I6

I5

I4

I3

I2

I1

I0

13570

23671

45672

IIIIY

IIIIY

IIIIY

I7

I6

I5

I4

I3

I2

I1

I0

Y2

Y1

Y0

52


STLD UNIT IIPriority encoder

If two inputs are active simultaneously, the output produces an undefined combination. We

can establish an input priority to ensure that only one input is encoded.

Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated

when all the inputs are 0; the output is the same as when D0 is equal to 1.

2019/2/17

V=0no valid inputs

V=1valid inputs

X’s in output columns represent

don’t-care conditions X’s in the

input columns are useful for

representing a truth table in

condensed form. Instead of listing

all 16 minterms of four variables.

53


STLD UNIT IIPriority Encoders

4-Input Priority Encoder ( V is a valid bit indicator)

2019/2/17

Pri

ori

ty

En

cod

er V

y

x

D3

D2

D1

D0

54


STLD UNIT II

1

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STLD UNIT II

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STLD UNIT IIEncoder / Decoder Pairs

2019/2/17

Y2

Y1

Y0

I7

I6

I5

I4

I3

I2

I1

I0

I2

I1

I0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Binary

Encoder

Binary

Decoder

57


STLD UNIT IIMultiplexers (Data Selector)

It Selects binary information from one of many

input lines and directs it to a single output line.

2019/2/17

MUX Y

I0

I1

I2

I3 S1 S0

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

58


STLD UNIT II2-to-1 MUX

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STLD UNIT IIMultiplexers

2-to-1 MUX or 2 x 1 MUX

4-to-1 MUX

2019/2/17

MUX Y

S

I1

I0

S

Y

MUX Y

I0

I1

I2

I3

S1 S0

I1

I0

S1

YI2

I3

S0

I0

I1

60


STLD UNIT IIMultiplexers

Quad 2-to-1 MUX

2019/2/17

MUX Y0I0

I1 S

MUX Y1I0

I1 S

MUX Y2I0

I1 S

MUX Y3I0

I1 S

A0

A1

A2

A3

B0

B1

B2

B3

S

MUX

A0

A1

A2

A3

S E

Y3

Y2

Y1

Y0B0

B1

B2

B3

(two 4-bits input, one 4-bits output)

61


STLD UNIT II

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STLD UNIT IIImplementation Using Multiplexers

Example

F(x, y, z) = ∑(1, 2, 6, 7)

2019/2/17

MUX Y

I0

I1

I2

I3 S1 S0

x y z F

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1

x y

FF = zz

F = z

z

F = 0

0

F = 1

1

63


STLD UNIT II

MUX Y

I0

I1

I2

I3

I4

I5

I6

I7S2 S1 S0

Implementation Using Multiplexers

Example

F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

2019/2/17

A B C D F

0 0 0 0 0

0 0 0 1 1

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1 A B C

F

F = D

D

F = D D

F = D D

F = 00

F = 0

F = D

F = 1

F = 1

0

D

1

1

64


STLD UNIT II

Y

I0

I1

I2

I3

I4

I5

I6

I7

S2 S1 S0

Multiplexer Expansion

8-to-1 MUX using Dual 4-to-1 MUX & one 2x1 Mux

2019/2/17

MUX Y

I0

I1

I2

I3 S1 S0

MUX Y

I0

I1

I2

I3 S1 S0

MUX YI0

I1S

0 01

65


STLD UNIT IIDeMultiplexers

2019/2/17

DeMUXI

Y3

Y2

Y1

Y0

S1 S0

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

I

Y3

Y2

Y1

Y0

S0

S1

66


STLD UNIT IIDeMultiplexers / Decoders

2019/2/17

Bin

ary

Dec

od

erI1

I0

E

Y0

Y1

Y2

Y3

E I1 I0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

DeMUXI

Y0

Y1

Y2

Y3

S1 S0

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

67

unit - ii · stld unit ii 5 analysis procedure to obtain the output boolean functions from a logic...

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